High Performance Configurable 8-bit RISC Microcontroller ver 1.42 OVERVIEW The DFPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast memory (typically on-chip). The core has been designed with a special concern about low power consumption. The DFPIC1655X is software compatible with the industry standard PIC16C554 and PIC16C558. It employs a modified RISC architecture (2 times faster than original implementation). The DFPIC1655X have enhanced core features, configurable hardware stack, and multiple internal and external interrupt sources. The separate instruction and data buses allow a 14 bit wide instruction word with the separate 8 -bit wide data. The DFPIC1655X typically achieve a 2:1 code compression and a 8:1 speed improvement over other 8-bit microcontrollers in their class. The power-down mode SLEEP allow user to reduce power consumption. User can wake up the controller from SLEEP through several external and internal interrupt and reset. An integrated Watchdog Timer with it's own clock signal provides protection against software lock-up. The DFPIC1655X Microcontroller fits perfectly in applications ranging from highspeed automotive and appliance motor control All trademarks mentioned in this document are trademarks of their respective owners. to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices make this IP perfect for applications applications with space and power consumption limitations. DFPIC1655X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow CPU FEATURES Software compatible with industry standard PIC16C55X Harvard architecture 2 times faster compared to original implementation 35 instructions 14 bit wide instruction word Up to 512 bytes of internal Data Memory Up to 64K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with no internal tri-states Scan test ready Technology Code independent HDL Source http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PERIPHERALS Two 8 bit I/O ports Two 8-bit corresponding TRIS registers Interrupt feature on PORTB(7:4) change Timer 0 8-bit timer/counter Readable and Writable 8-bit software programmable prescaler CONFIGURATION The following parameters of the DFPIC1655X core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. - synchronous asynchronous - 1-16 default 8 * RAM size - up to 512 default 256 * Program Memory size - up 64 kWords default 8k * SLEEP mode - used unused * WATCHDOG Timer - used / width unused * Timer system - used unused * PORTS A,B - used unused * RAM memory type Internal or external clock select Interrupt generation on timer overflow Edge select for external clock Watchdog Timer Configurable Time out period * Number of hardware stack levels 7-bit software programmable prescaler Dedicated independent Watchdog Clock input Interrupt Controller Three individually maskable Interrupt sources External interrupt INT Timer Overflow interrupt Port B[7:4] change interrupt DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Unlimited Designs license for SYMBOL HDL Source clk clkwdt por mclr Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs prgdata(13:0) prgaddr(15:0) ramdatai(7:0) ramdatao(7:0) ramaddr(8:0) ramwe ramoe PINS DESCRIPTION PIN TYPE DESCRIPTION int clk input Global clock t0cki clkwdt input Watchdog clock por input Global reset Power On Reset portai(7:0) portbi(7:0) mclr input User reset prgdata[13:0] input Data bus from program memory ramdati[7:0] input Data bus from int. data memory int input External interrupt t0cki input Timer 0 input portai[7:0] input Port A input portbi[7:0] input Port B input prgaddr[15:0] output Program memory address bus ramdatao[7:0] output Data bus for internal data memory ramaddr[8:0] output RAM address bus ramwe output Data memory write ramoe output Data memory output enable sleep output Sleep signal portao[7:0] output Port A output portbo[7:0] output Port B output trisa[7:0] output Data direction pins for Port A trisb[7:0] output Data direction pins for Port B All trademarks mentioned in this document are trademarks of their respective owners. sleep portao(7:0) portbo(7:0) trisa(7:0) trisb(7:0) BLOCK DIAGRAM ALU - Arithmetic Logic Unit performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register. Control Unit - It performs the core synchronization and data flow control. This module manages execution of all instructions. Performs decode and control functions for all other blocks. It contains program counter (PC) and hardware stack. Hardware Stack - The DFPIC1655X configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when CALL instruction is executed or an interrupt causes a branch. The stack is popped while RETURN, RETFIE and RETLW instruction execution. The stack operates as a circular buffer. This means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. RAM Controller - It performs interface functions between Data Memory and DFPIC1655X internal logic. It assures correct Data memory addressing and data transfers. The DFPIC1655X supports two addressing modes: direct or indirect. In Direct Addressing the 9-bit direct address is computed from RP(1:0) bits (STATUS) and 7 least significant bits of instruction word. Indirect addressing is possible by using the INDF register. Any instruction using INDF register actually accesses data pointed to by the file select register FSR. Reading INDF register indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation. An effective 9-bit address is obtained by concatenating the IRP bit (STATUS) and the 8-bit FSR register. clk por mclr sleep prgdata prgaddr int Hardware Stack ALU Control Unit RAM Controller Interrupt Controller I/O Ports t0cki Timer 0 clkwdt Watchdog Timer ramdatai ramdatao ramaddr ramwe ramoe portai portbi portao portbo trisa trisb Interrupt Controller - Interrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register called INTCON The DFPIC1655X has three interrupt sources: A global interrupt enable bit, GIE enables all unmasked interrupts. Each interrupt source has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before reenabling interrupts. Timer 0 - Main system's timer and prescaler. The DFPIC1655X Timer operates in two modes: 8-bit timer or 8-bit counter. In the "timer mode", timer registers are incremented every 4 CLK periods. When the prescaler is assigned into the TIMER prescale ration can be divided by 2, 4 .. 256. In the "counter mode" the timer register is incremented every falling or rising edge of T0CKI pin, dependent on T0SE bit in OPTION register. Watchdog Timer- it's a free running timer. WDT has own clock input separate from system clock. It means that the WDT will run even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT time-out generates a Watchdog reset. If the device is in SLEEP mode the WDT time-out causes the device to wake-up and continue with normal operation. I/O Ports - Block contains DFPIC1655X's general purpose I/O ports and data direction registers (TRIS). The DFPIC1655X has two 8bit full bi-directional ports PORT A, PORT B. Read and write accesses to the I/O port are performed via their corresponding SFR's PORTA, PORTB. The reading instruction always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA and TRISB registers. When the bit of TRIS register is set this means that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance). External interrupt INT TMR0 overflow interrupt PORTB change interrupt (pins B7:B4) The interrupt control register INTCON records individual interrupt requests in flag bits. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. OPTIONAL MODULES PERFORMANCE There are also available an optional peripherals, not included in presented DFPIC1655X Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. The following tables give a survey about the Core area and performance in the Programmable Logic Devices after Place & Route (all CPU features and peripherals have been included): Full duplex UART Device ORCA 3T ORCA 4E ispXPGA SPI - Master and Slave Serial Peripheral Interface Supports speeds up 1/4 of system clock Mode fault error Write collision error Component rial clock SCK CPU* Timer 0 Watchdog Timer I/O Ports Total area System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) PWM - Pulse Width Modulation Timer Fmax 28 MHz 54 MHz 54 MHz Area utilized by the each unit of DFPIC1655X core in vendor specific technologies is summarized in table below. Software selectable polarity and phase of se- Interrupt generation Speed grade -7 -3 -5 [LC / PFU] [FFs] 456 / 83 60 / 10 42 / 9 37 / 5 601 / 109 236 22 26 41 325 *CPU - consisted of ALU, Control Unit, Bus Controller, Hardware Stack, External INT pin Interrupt Controller Core components area utilization 2 independent 8-bit PWM channels, concate- nated on one 16-bit PWM channel Software-selectable duty from 0% to 100% and pulse period Software-selectable polarity of output wave- form I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies IMPROVEMENT Most instruction of DFPIC1655X is executed within 2 CLK cycles. Except the conditional program memory branches in case that the condition of branch instruction is met. The table below shows sample instructions execution times: Mnemonic DFPIC1655X operands (CLK cycles) ADDWF 2 ANDWF 2 RLF 2 BCF 2 DECFSZ 2(4)1 INCFSZ 2(4)1 BTFSC 2(4)1 BTFSS 2(4)1 CALL 2 GOTO 2 RETFIE 2 RETLW 2 RETURN 2 PIC16C554 (CLK cycles) Impr. 4 4 4 4 4(8)1 4(8)1 4(8)1 4(8)1 8 8 8 8 8 2 2 2 2 2 2 2 2 4 4 4 4 4 1 User defined data setup time on I2C lines - number of clock in case that result of operation is 0. Interrupt generation All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. DFPIC FAMILY OVERVIEW 1 1 2 8 8 - Speed rate 5 5 Wake up on port pin change 24 16 32 Levels of hardware stack 33 35 35 Internal Interrupts I/O Ports 12 14 14 External interrupts Number of instructions 128 512 512 Sleep Mode Program word length 2k 64k 64k Watchdog Timer Data Memory space DFPIC165X DFPIC1655X DRPIC1655X Timer 0 Design Program Memory space The family of DCD DFPICXX IP Cores combine a high-performance, low cost, and small compact size, offering the best price/performance ratio in the IP Market. The DCD's Cores are dedicated for use in cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security and telecommunication applications. DCD DFPICXX IP Cores family contains three 8-bit microcontroller Cores to best meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, and DRPIC1655X single cycle microcontroller with 14-bit program word. All three microcontroller cores are binary compatible with widely accepted PIC16C5X and PIC16CXXX. It employ a modified RISC architecture two or four times faster than the original ones. The DFPICXXX IP Cores are written in pure VHDL/VERILOG HDL languages which makes them technologically independent. All of the DFPICXX family members supports a power saving SLEEP mode and allows the user to configure the watchdog time-out period and a number of hardware stack levels. DFPICXX can be fully customized according to customer needs. 2 2 4 DFPIC family of High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinnffoo@ @ddccdd..ppll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinnffooU USS@ @ddccdd..ppll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY MTTC Ciinnffoo@ @m mttcc..ddee e-mail : M tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.