IRFZ44V
HEXFET® Power MOSFET
1/29/03
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 55
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 39 A
IDM Pulsed Drain Current 220
PD @TC = 25°C Power Dissipation 115 W
Linear Derating Factor 0.77 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy115 mJ
IAR Avalanche Current55 A
EAR Repetitive Avalanche Energy11 mJ
dv/dt Peak Diode Recovery dv/dt 4.5 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.3
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62
Thermal Resistance
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VDSS = 60V
RDS(on) = 16.5mΩ
ID = 55A
S
D
G
TO-220AB
Advanced HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 watts. The low thermal
resistance and low package cost of the TO-220 contribute
to its wide acceptance throughout the industry.
lAdvanced Process Technology
lUltra Low On-Resistance
lDynamic dv/dt Rating
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
lOptimized for SMPS Applications
Description
PD - 93957B
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S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 2.5 V TJ = 25°C, IS = 51A, VGS = 0V
trr Reverse Recovery Time ––– 70 105 ns TJ = 25°C, IF = 51A
Qrr Reverse Recovery Charge ––– 146 219 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
55
220
A
Starting TJ = 25°C, L = 89µH
RG = 25Ω, IAS = 51A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
ISD ≤ 51A, di/dt ≤ 227A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 – –– – –– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.062 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 16.5 mΩVGS = 10V, ID = 31A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 24 ––– ––– S VDS = 25V, I D = 31A
––– ––– 25 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 48V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge –– – ––– 67 ID = 51A
Qgs Gate-to-Source Charge ––– ––– 18 nC VDS = 48V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 25 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 13 ––– VDD = 30V
trRise Time ––– 97 ––– ID = 51A
td(off) Turn-Off Delay Time –– – 40 ––– RG = 9.1Ω
tfFall Time ––– 57 ––– RD = 0.6Ω, See Fig. 10
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 1812 ––– VGS = 0V
Coss Output Capacitance ––– 393 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 103 ––– pF ƒ = 1.0MHz, See Fig. 5
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
0.1
1
10
100
1000
0.1 1 10 100
20µs PU LSE WIDT H
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
1
10
100
1000
0.1 1 10 100
20µs PU LSE WIDT H
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain -to-Sou rce Vol tage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Tem pera t ur e ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
55A
1
10
100
1000
45678910 11 12
V = 25V
20µs PULS E WI DTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
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Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
110 100
VDS, Drai n-to-S ource Voltage (V)
0
1000
2000
3000
4000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V , f = 1 MHZ
Cis = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
020 40 60 80 100
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gat e-to-Sour ce Vol t age (V)
G
GS
I =
D51A
V = 12V
DS
V = 30V
DS
V = 48V
DS
1
10
100
1000
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Dr ain Current ( A)I , Dr ain Current ( A)
DS
D
10us
100us
1ms
10ms
0.1
1
10
100
1000
0.2 0.7 1.2 1.7 2.2
V ,Source-to- Drain Volt age (V)
I , Reverse D rain Curr ent (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
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RD
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VGS
RG
D.U.T.
10V
+
-
25 50 75 100 125 150 175
0
10
20
30
40
50
60
T , Case Tem perature( C)
I , Drai n Curr ent (A)
°
C
D
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VGS
RG
D.U.T.
10V
VDD
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1 . Duty f actor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response(Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
25 50 75 100 125 150 175
0
50
100
150
200
250
Starti ng T , Junct ion Tem perat ur e ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
21A
36A
51A
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
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LEAD ASSIG NMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3. 78 (. 1 49)
3. 54 (. 1 39)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15. 2 4 (. 6 00 )
14. 8 4 (. 5 84 )
14. 0 9 (. 5 55 )
13. 4 7 (. 5 30 )
3X 1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0. 3 6 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSI ONI NG & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
Part Marking Information
TO-220AB
Package Outline
TO-220AB Outline
Dimensions are shown in millimeters (inches)
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
E XAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
LOT CODE 9B1M
ASSEMBLY
LOT CODE
DATE CODE
(YYWW)
YY = YE A R
WW = WEEK
9246
IRF1010
9B 1M
A
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 1/03
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Note: For the most current drawings please refer to the IR website at:
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