S6AP413A
4ch DC/DC Converter with I2C Interface
and Internal SW FETs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-08448 Rev.*A Revised February 26, 2016
S6AP413A contains 3ch buck DC/DC converter and 1ch buck-boost DC/DC converter. S6AP413A can supply the main power line in
several systems by using only its chip. The current mode control is adopted for the DC/DC converter, and it is possible to use the
small chip inductor with the high switching frequency operation which contains internal switching FETs. S6AP413A contains the
output setting resistor and the phase compensation circuit, and contributes to reduce the number of external components and its
mount area. Also it contains the CTL input pin which can control the ON/OFF for each DC/DC converter, the Power Good signal
output pin and I2C communication interface, therefore it is easy to design the power supply sequence. It is possible to tune in the
output voltage exactly using the I2C communication.
Features
Operating input voltage range: 2.5V to 5.5V (Maximum rating: 6.5V)
Output voltage setting range: DD1*:0.7V to 1.32V (20mV/step)
DD2*:1.2V to 1.95V (50mV/step)
DD3*:2.8Vto 3.5V (100mV/step)
DD4*:0.7V to 1.32V (20mV/step)
Maximum output current: DD1:2A, DD2:1.2A, DD3:0.6A, DD4:2A
Internal switching FETs, output voltage setting resistor, phase compensation circuit and output discharge resistor (all DC/DC
converters)
Buck-boost DC/DC converter is seamless to change operation mode
Soft start time setting range: 1 ms to 16 ms (approximately 1ms/step)
Switching frequency for the DC/DC converter: 3 MHz
Communication interface: I2C (ON/OFF, Output voltage, Soft start time)
Internal PFM/PWM auto switching mode
Each DC/DC converter Power Good function (open drain)
Several protection functions: Under voltage lockout (UVLO), Over current protection (OCP), Thermal shut down (TSD)
Small package: QFN32 (5mm × 5mm × 0.71mm, 0.5mm pitch)
*: DD1, DD2, DD3, and DD4: DC/DC converter blocks 1,2,3,4
Applications
Network equipment, Factory automation, Security system, Surveillance camera, Electrical music instrument, Multi-function printer,
Scanner, Printer, Copy machine, Home appliances, Data storage (HDD, SSD), Mobile equipment for Li+ battery (1 cell)
Document Number: 002-08448 Rev.*A Page 2 of 69
S6AP413A
Contents
1. Application Circuit Example ............................................................................................................................................ 4
2. Recommended Application Specification ....................................................................................................................... 5
3. Pin Configuration .............................................................................................................................................................. 8
4. Pin Descriptions ................................................................................................................................................................ 9
5. Block Diagram ................................................................................................................................................................. 10
6. Absolute Maximum Ratings ........................................................................................................................................... 11
7. Recommended Operating Conditions ........................................................................................................................... 12
8. Electrical Characteristics ............................................................................................................................................... 13
8.1 Reference Control Block .............................................................................................................................................. 13
8.2 DD1 ............................................................................................................................................................................. 14
8.3 DD2 ............................................................................................................................................................................. 15
8.4 DD3 ............................................................................................................................................................................. 16
8.5 DD4 ............................................................................................................................................................................. 17
8.6 Digital Block ................................................................................................................................................................. 18
9. Operation Mode List ....................................................................................................................................................... 19
10. State Transition Diagram ................................................................................................................................................ 20
11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3, CTL4) .......................................................... 21
12. Turning ON and OFF Sequence (AVCC →CTLMAIN→CTL1→CTL2→ CTL3→ CTL4) ............................................... 22
13. Turning ON and OFF Sequence (AVCC→CTLMAIN→I2C) ........................................................................................... 23
14. CTL Pin Threshold Voltage ............................................................................................................................................ 24
15. Protection Operation Sequence..................................................................................................................................... 25
16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit ..................................................... 26
17. DD Soft Start Operation .................................................................................................................................................. 27
18. Discharge Operation ....................................................................................................................................................... 28
19. PG Function ..................................................................................................................................................................... 29
20. I2CInterface ...................................................................................................................................................................... 30
20.1 Structure of I2CInterface .............................................................................................................................................. 30
20.2 Definition of Signal Lines ............................................................................................................................................. 30
20.3 Validity of Data ............................................................................................................................................................ 31
20.4 Definition of Start and Stop Condition.......................................................................................................................... 31
20.5 ACK Signal .................................................................................................................................................................. 32
20.6 I2C Interface Input Timing ............................................................................................................................................ 33
20.7 Slave Address ............................................................................................................................................................. 34
20.8 Bit Structure of Data on I2C Interface .......................................................................................................................... 35
21. Structure of I2C Interface and Data ................................................................................................................................ 37
21.1 About DD1, DD4Output Voltage Setting ...................................................................................................................... 38
21.2 About DD2 Output Voltage Setting .............................................................................................................................. 39
21.3 About DD3 Output Voltage Setting .............................................................................................................................. 40
21.4 About Soft Start Time .................................................................................................................................................. 41
21.5 DC/DC Operation Mode .............................................................................................................................................. 42
21.6 ON/OFF for DC/DC ..................................................................................................................................................... 43
21.7 About Error Monitor ..................................................................................................................................................... 44
21.8 About Power Good Monitor ......................................................................................................................................... 45
22. I/O Pin Equivalent Circuit Diagram ................................................................................................................................ 46
23. Measurement Circuit for Characteristics of General Operation ................................................................................. 49
24. Reference Data ................................................................................................................................................................ 51
25. Ordering Information ...................................................................................................................................................... 63
26. Preset Code List .............................................................................................................................................................. 64
Document Number: 002-08448 Rev.*A Page 3 of 69
S6AP413A
27. Layout .............................................................................................................................................................................. 65
28. Package Dimensions ...................................................................................................................................................... 66
29. Major Changes ................................................................................................................................................................ 67
Document History ................................................................................................................................................................. 68
Document Number: 002-08448 Rev.*A Page 4 of 69
S6AP413A
1. Application Circuit Example
Figure 1. Application Circuit
Document Number: 002-08448 Rev.*A Page 5 of 69
S6AP413A
2. Recommended Application Specification
[Input Voltage Range]
Input Voltage Vin(V)
Min
Typ
Max
2.5
3.3
5.5
[Output specification]
(Ta=+25°C)
Channel
Symbol
Accuracy
Output Voltage (V)
Output
Current(mA)
Limit
Current(mA)
Mode
Switching
Frequency(MH
z)
Inductor(µH)
Output
Capacitance
Soft-start Time
(ms)
Discharge
Resistance
(kΩ)
Remarks
Min
Typ
Max
Max
Min
DD1
VO1
±1.2
%
0.692
0.700
0.708
2000
(2400)
Buck
(synchro
nous
rectificati
on)
C-mode
3.0
1.0
22
1 to
16ms
At the
time of
1.0V
setting,
the
details
are cf.
Contents
17
5.0
Built-in
SWFET
Built-in
output
setting
resistor
s
Built-in
phase
compe
nsation
circuit
0.711
0.720
0.729
0.731
0.740
0.749
0.751
0.760
0.769
0.771
0.780
0.789
0.790
0.800
0.810
0.810
0.820
0.830
0.830
0.840
0.850
0.850
0.860
0.870
0.869
0.880
0.891
0.889
(*1)
0.900
(*1)
0.911
(*1)
0.909
0.920
0.931
0.929
0.940
0.951
0.948
0.960
0.972
0.968
0.980
0.992
0.988
(*1)
1.000
(*1)
1.012
(*1)
1.008
1.020
1.032
1.028
1.040
1.052
1.047
1.060
1.073
1.067
1.080
1.093
1.087
(*1)
1.100
(*1)
1.113
(*1)
1.107
1.120
1.133
1.126
1.140
1.154
1.146
1.160
1.174
1.166
1.180
1.194
1.186
(*1)
1.200
(*1)
1.214
(*1)
1.205
1.220
1.235
1.225
1.240
1.255
1.245
1.260
1.275
1.265
1.280
1.295
1.284
1.300
1.316
1.304
1.320
1.336
Document Number: 002-08448 Rev.*A Page 6 of 69
S6AP413A
Channel
Symbol
Accuracy
Output Voltage (V)
Output
Current(mA)
Limit
Current(mA)
Mode
Inductor(µH)
Output
Capacitance
Soft-start Time
(ms)
Discharge
Resistance
(kΩ)
Remarks
Min
Typ
Max
Max
Min
DD2
VO2
±1.2
%
1.186
(*1)
1.200
(*1)
1.214
(*1)
1200
(15
00)
Buck
(synchronou
s
rectification)
C-mode
1.
0
10
1 to
16ms
At the
time
of
1.8V
settin
g, the
detail
s are
cf.
Conte
nts 17
5.0
Built-in
SWFE
T
Built-in
output
setting
resistor
s
Built-in
phase
compe
nsation
circuit
1.235
1.250
1.265
1.284
1.300
1.316
1.334
(*1)
1.350
(*1)
1.366
(*1)
1.383
1.400
1.417
1.433
1.450
1.467
1.482
(*1)
1.500
(*1)
1.518
(*1)
1.531
1.550
1.569
1.581
1.600
1.619
1.630
1.650
1.670
1.680
1.700
1.720
1.729
1.750
1.771
1.778
(*1)
1.800
(*1)
1.822
(*1)
1.828
1.850
1.872
1.877
1.900
1.923
1.927
1.950
1.973
DD3
VO3
±1.8
%
2.74
(*1)
2.80
(*1)
2.86
(*1)
600
(75
0)
Buck-boost
(synchronou
s
rectification)
C-mode
1.
0
22
1
to16m
s
At the
time
of
3.3V
settin
g, the
detail
s are
cf.
Conte
nts 17
5.0
Built-in
SWFE
T
Built-in
output
setting
resistor
s
Built-in
phase
compe
nsation
circuit
2.84
2.90
2.96
2.94
(*1)
3.00
(*1)
3.06
(*1)
3.04
3.10
3.16
3.14
3.20
3.26
3.23
(*1)
3.30
(*1)
3.37
(*1)
3.33
3.40
3.47
3.43
(*1)
3.50
(*1)
3.57
(*1)
Document Number: 002-08448 Rev.*A Page 7 of 69
S6AP413A
Channel
Symbol
Accuracy
Output Voltage (V)
Output
Current(mA)
Limit
Current(mA)
Mode
Switching
Frequency(MH
z)
Inductor(µH)
Output
Capacitance
Soft-start Time
(ms)
Discharge
Resistance
(kΩ)
Remarks
Min
Typ
Max
Max
Min
DD4
VO4
±1.2
%
0.692
0.700
0.708
2000
(2400)
Buck
(synchr
onous
rectificat
ion)
C-mode
3.0
1.
0
22
1
to16ms
At the
time of
1.8V
setting,
the
details
are cf.
Content
s 17
5.0
Built-in
SWFE
T
Built-in
output
setting
resistor
s
Built-in
phase
compe
nsation
circuit
0.711
0.720
0.729
0.731
0.740
0.749
0.751
0.760
0.769
0.771
0.780
0.789
0.790
0.800
0.810
0.810
0.820
0.830
0.830
0.840
0.850
0.850
0.860
0.870
0.869
0.880
0.891
0.889
(*1)
0.900
(*1)
0.911(
*1)
0.909
0.920
0.931
0.929
0.940
0.951
0.948
0.960
0.972
0.968
0.980
0.992
0.988
(*1)
1.000
(*1)
1.012
(*1)
1.008
1.020
1.032
1.028
1.040
1.052
1.047
1.060
1.073
1.067
1.080
1.093
1.087
(*1)
1.100
(*1)
1.113
(*1)
1.107
1.120
1.133
1.126
1.140
1.154
1.146
1.160
1.174
1.166
1.180
1.194
1.186
(*1)
1.200
(*1)
1.214
(*1)
1.205
1.220
1.235
1.225
1.240
1.255
1.245
1.260
1.275
1.265
1.280
1.295
1.284
1.300
1.316
1.304
1.320
1.336
*1:default(It is selectable with the default output voltage)
Document Number: 002-08448 Rev.*A Page 8 of 69
S6AP413A
3. Pin Configuration
(TOP VIEW)
(WNT032)
VO3
PG4
PG3
PG2
PG1
AVCC
VREF18
CTLMAIN
32 31 30 29 28 27 26 25
LX3-2 124 IN1
PGND3 223 PVCC1
LX3-1 322 LX1
PVCC3 4top view 21 PGND1
PVCC2 520 PGND4
LX2 619 LX4
PGND2 7
EP(Exposed Pad)
18 PVCC4
IN2 817 IN4
910 11 12 13 14 15 16
CTL1
CTL2
CTL3
CTL4
GND
SCL
SDA
DVCC
Document Number: 002-08448 Rev.*A Page 9 of 69
S6AP413A
4. Pin Descriptions
Block
Pin
Name
Pin
Num
ber
I/O
Description
Pull-
down
Resis
tor
Unuse
d DD1
Unuse
d DD2
Unused
DD3
Unused
DD4
Unus
ed
I2C
DD1
Buck
IN1
24
I
DD1 output voltage feedback
-
GND
-
-
-
-
PVCC
1
23
-
DD1output block power supply
-
AVCC
-
-
-
-
LX1
22
O
DD1 inductor connection
-
Open
-
-
-
-
PG1
28
O
DD1 Power Good output
-
GND
-
-
-
-
PGND
1
21
O
DD1 output block ground
-
GND
-
-
-
-
DD2
Buck
IN2
8
I
DD2 output voltage feedback
-
-
GND
-
-
-
PVCC
2
5
-
DD2 output block power supply
-
-
AVCC
-
-
-
LX2
6
O
DD2 inductor connection
-
-
Open
-
-
-
PG2
29
O
DD2 Power Good output
-
-
GND
-
-
-
PGND
2
7
-
DD2 output block ground
-
-
GND
-
-
-
DD3
Buck-boos
t
PVCC
3
4
-
Power supply for DD3 output
block
-
-
-
AVCC
-
-
VO3
32
O
Output voltage for DD3
-
-
-
GND
-
-
LX3-1
3
O
DD3 inductor connection1
-
-
-
Open
-
-
LX3-2
1
O
DD3 inductor connection2
-
-
-
Open
-
-
PG3
30
O
Output for DD3 Power Good
-
-
-
GND
-
-
PGND
3
2
-
Ground for DD3 output block
-
-
-
GND
-
-
DD4
Buck
IN4
17
-
DD4 output voltage feedback
-
-
-
-
GND
-
PVCC
4
18
-
DD4 output block power supply
-
-
-
-
AVCC
-
LX4
19
O
DD4 inductor connection
-
-
-
-
Open
-
PG4
31
O
DD4 Power Good output
-
-
-
-
GND
-
PGND
4
20
-
DD4 output block ground
-
-
-
-
GND
-
CTL
CTLM
AIN
25
I
Control for reference voltage
output
Exist
-
-
-
-
-
CTL1
9
I
DD1 control
Exist
Open
-
-
-
-
CTL2
10
I
DD2 control
Exist
-
Open
-
-
-
CTL3
11
I
DD3control
Exist
-
-
Open
-
-
CTL4
12
I
DD4 control
Exist
-
-
-
Open
-
I2C
DVCC
16
I
Power supply for I2C
communication
-
-
-
-
-
GND
SCL
14
I
Clock for I2C communication
-
-
-
-
-
Open
SDA
15
I/O
Data for I2C communication
Exist
-
-
-
-
Open
Reference
control
AVCC
27
-
Power supply for reference
voltage
-
-
-
-
-
-
VREF1
8
26
O
Output reference voltage
-
-
-
-
-
-
GND
13
-
Ground for reference voltage
-
-
-
-
-
-
GND
EP
-
Ground for reference voltage
-
-
-
-
-
-
Document Number: 002-08448 Rev.*A Page 10 of 69
S6AP413A
5. Block Diagram
ErrAMP
PVCC2
SLP
CMP
PWM
Logic
Control
ICOMP LX2
LV
CNV
AST
L Priority
PGND2
VCC VCC VCC
PG2
B
IN2
B
scp2
SLP
CMP
VCC
AST
LV
CNV
PWM
Logic
Control AST
ErrAMP ICOMP
L Priority
VCC VCC
mode
cs3 scp3
PVCC3
LX3-1
LX3-2
VO3
PGND3
PG3
Common Block
VREF BGR
(1.8V)
RT
VREF18
CT
OSC
cIK
VREF18
AVCC
GND
cs*
xclk
DAC
VREF18
cs2
<<DD2>>
UVLO
POR
ctl2
DAC
VREF18
<<DD3>>
UVLO
POR
ctl3
mode clk
xclk
Under
Voltage
Locked-Out
Thermal
Shut
Down
scp*
CTL1
CTL2
CTL3
ctl1
ctl2
ctl3
mode
Logic Control
Short Circuit Protection
(Timer & Latch)
Output Voltage Ajuster
Soft Start Control
CTLMAIN
DVCC
SCL
SDA
Logic
Control
CTL4
ErrAMP
<<DD1>> PVCC1
SLP
CMP
PWM
Logic
Control
ICOMP
LX1
LV
CNV
AST
L Priority
PGND1
VCC VCC VCC
cs4 scp4
mode
UVLO
POR
PG1
ctl1
PVCC4
SLP
CMP
PWM
Logic
Control
ICOMP LX4
LV
CNV
AST
PGND4
VCC VCC
A
IN1
A
VCC:2.5V to 5.5V
DAC
VREF18
clk
cs1 scp1
L Priority VCC
UVLO
POR
ctl4
DAC
VREF18
PG4
D
IN4 <<DD4>>
D
mode clk
Document Number: 002-08448 Rev.*A Page 11 of 69
S6AP413A
6. Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Min
Max
Power supply voltage
VVCC1
AVCC,PVCC input voltage
-0.3
6.5
V
VVCC2
DVCC input voltage
-0.3
6.5
V
Terminal voltage
VCTL1
CTL1, CTL2, CTL3 input voltage
-0.3
6.5
V
VCTL2
CTLMAIN input voltage
-0.3
6.5
V
VLOGIC
SDA,SCL input voltage
-0.3
6.5
V
VPG
PG1, PG2, PG3, PG4 drain voltage
-0.3
6.5
V
VOUT
IN1, IN2, IN3, IN4 input voltage
-0.3
6.5
V
LX voltage
VLX
LX1, LX2, LX3, LX4 voltage
-1.0
6.5
V
Permission loss
PD
Ta≤+25°C
Thermal resistance(θja):(29.2°C /W(*1))
0
3420
mW
Maximum junction temperature
Tjmax
-
-
+125
°C
Storage temperature
TSTG
-
-55
+125
°C
*1: When the IC is mounted on 74mm × 74mm four-layer square epoxy board. IC is mounted on a four-layer
epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board.
WARNING:
1. Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of
these ratings.
Figure 2. Power Dissipation vs. Operation Ambient Temperature
0
500
1000
1500
2000
2500
3000
3500
4000
-40 -20 0 20 40 60 80 100
Pd [mW]
Temperature[˚C]
Power dissipation vs. Operation ambient temperature
Document Number: 002-08448 Rev.*A Page 12 of 69
S6AP413A
7. Recommended Operating Conditions
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
1. Reference control block
Power supply voltage
VVCC
AVCC
2.5
3.3
5.5
V
Output current for reference voltage
IREF
VREF18
-1
-
0
mA
Operating temperature
Ta
-
-30
+25
+85
°C
2. DC/DC channel
Power supply voltage
VVCC
PVCC1, PVCC2, PVCC3,
PVCC4
2.5
3.3
5.5
V
Input voltage
VOUT
IN1,IN2
0
-
AVCC
V
PG input voltage
VPG
PG1, PG2, PG3, PG4
0
-
5.5
V
3. Input block
Input voltage
VCTL
VMODE
CTL1, CTL 2, CTL3, mode
CTLMAIN
0
-
AVCC
V
4. I2C communication block
Power supply voltage
VVCC
DVCC
1.70
-
3.50
V
Input voltage
VLOGIC
SDA,SCL
0
-
DVCC
V
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-08448 Rev.*A Page 13 of 69
S6AP413A
8. Electrical Characteristics
8.1 Reference Control Block
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V, Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
1. Reference voltage [ VREF18 ]
Output voltage
VVREF1
VREF18 pin = 0mA
1.773
1.800
1.827
V
VVREF2
AVCC pin = 2.5V to 5.5V
VREF18 pin = 0mA
1.768
1.800
1.832
V
VVREF3
VREF18 pin =0mA to -1mA
1.768
1.800
1.832
V
2. Under voltage lockout [ VCC UVLO ]
Threshold voltage
VTH
AVCC rising
2.156
2.20
2.244
V
Hysteresis width
VH
-
-
0.20(*1)
-
V
3. Over current protection [ OCP ]
Timer
tOCP1
DD1, DD2, DD3, DD4
0.9
1
1.1
ms
4. Thermal shut down [ TSD ]
Stop temperature
TTSDH
-
125(*2)
150
-
°C
5. Input block (CTL,mode,CTLMAIN) [ CTL,CTLMAIN ]
Input voltage
VIH
CTL1, CTL2, CTL3, CTL4 pin
CTLMAIN pin
AVCC
×0.7
-
AVCC
V
Input voltage
VIL
CTL1, CTL2, CTL3, CTL4 pin
CTLMAIN pin
0
-
0.4
V
Input current
ICTLH
IMODEH
CTL1, CTL2, CTL3, CTL4 pin =
3.3V
CTLMAIN pin = 3.3V
2.5
3.3
4.7
µA
ICTLL
IMODEL
CTL1, CTL2, CTL3, CTL4 pin = 0V
CTLMAIN pin = 0V
-
-
1
µA
Input pull-down resistor
RP
CTL1, CTL2, CTL3, CTL4 pin
CTLMAIN pin
-
1(*1)
-
MΩ
6. Consumption current (DC/DC converter block)
Power supply current
IVCCS1
CTL1, CTL2, CTL3, CTL4 pin = 0V
CTLMAIN pin = 0V
-
0
1.0
µA
IVCCS2
CTL1, CTL2, CTL3, CTL4 pin = 0V
CTLMAIN pin =3.3V
-
30
45
µA
IVCC
DD1,DD2,DD3,DD4=ON,
All DD are 0mA
(operation mode: PFM/PWM
mode)
-
450
670
µA
IVCC
DD1,DD2,DD3,DD4=ON,
All DD are 0mA
(operation mode: Fixed PWM
mode)
-
18
27
mA
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08448 Rev.*A Page 14 of 69
S6AP413A
8.2 DD1
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
1. DC/DC converter block [ DD1 ]
Output voltage
VOUT
IOUT = -10mA,
Output voltage setting: 1.0V
0.988
1.000
1.012
V
Input stability
VLINE
IOUT = -10mA,
PVCC1= 2.5V to 5.5V
-5
-
+5
mV
Load stability
VLOAD
IOUT = -1mA to -4000mA
(Fixed PWM mode)
-10
-
+10
mV
Load stability
VLOAD
IOUT = -1mA to -4000mA
(PFM/PWM mode)
-10
-
+15
mV
IN1 input impedance
RIN
IN1 = 2.0V
-
190(*1)
-
kΩ
SW PMOS-Tr
on resistance
RPMOS
LX1 = -30mA
-
120(*1)
-
mΩ
SW NMOS-Tr
on resistance
RNMOS
LX1 = 30mA
-
80(*1)
-
mΩ
SW PMOS-Tr
leakage current
ILEAK
LX1 = 0V
-3
-
-
µA
SW NMOS-Tr
Leakage current
ILEAK
LX1 = 3.3V
-
-
3
µA
Over current
protection value
ILIMIT
L=1.0µH
2400(*2)
-
-
mA
PFM/PWM mode
changeover current
IPFM
L=1.0µH
-
100(*1)
-
mA
Discharge resistor
RDIS
-
-
5(*1)
-
kΩ
Soft start time
Tss
Soft start time setting: 1ms
0.9
1
1.1
ms
Switching frequency
fOSC
-
2.7
3.0
3.3
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08448 Rev.*A Page 15 of 69
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8.3 DD2
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
2. DC/DC converter block [ DD2 ]
Output voltage
VOUT
IOUT = -10mA,
Output voltage setting:1.8V
1.778
1.800
1.822
V
Input stability
VLINE
IOUT = -10mA
PVCC2= 2.5V to 5.5V
-5
-
+5
mV
Load stability
VLOAD
IOUT = -1mA to -1200mA
(Fixed PWM mode)
-10
-
+10
mV
Load stability
VLOAD
IOUT = -1mA to -1200mA
(PFM/PWM mode)
-10
-
+20
mV
IN2 input impedance
RIN
IN2 = 2.0V
-
150(*1)
-
kΩ
SW PMOS-Tr
on resistance
RPMOS
LX2 = -30mA
-
190(*1)
-
mΩ
SW NMOS-Tr
on resistance
RNMOS
LX2 = 30mA
-
135(*1)
-
mΩ
SW PMOS-Tr
leakage current
ILEAK
LX2 = 0V
-3
-
-
µA
SW NMOS-Tr
leakage current
ILEAK
LX2 = 3.3V
-
-
3
μA
Over current
protection value
ILIMIT
L=1.0µH
1500(*2)
-
-
mA
PFM/PWM mode
changeover current
IPFM
L=1.0µH
-
65(*1)
-
mA
Discharge resistor
RDIS
-
-
5(*1)
-
kΩ
Soft start time
Tss
Soft start time setting:1ms
0.9
1
1.1
ms
Switching frequency
fOSC
-
2.7
3.0
3.3
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08448 Rev.*A Page 16 of 69
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8.4 DD3
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
3. DC/DC converter block [ DD3 ]
Output voltage
VOUT
IOUT = -10mA,
Output voltage setting:3.3V
3.241
3.300
3.359
V
Input stability
VLINE
IOUT = -10mA,
PVCC3= 2.5V to 5.5V
-5
-
+5
mV
Load stability
VLOAD
IOUT = -1mA to -600mA
(Fixed PWM mode)
-10
-
+10
mV
Load stability
VLOAD
IOUT = -1mA to -600mA
(PFM/PWM mode)
-10
-
+15
mV
VO3 impedance
RVo3
VO3= 2.0V
-
550(*1)
-
kΩ
SW PMOS-Tr
on resistance
RPMOS
LX3-1 = -30mA
-
115(*1)
-
mΩ
SW NMOS-Tr
on resistance
RNMOS
LX3-1 = 30mA
-
140(*1)
-
mΩ
SW PMOS-Tr
on resistance
RPMOS
LX3-2 = -30mA
-
155(*1)
-
mΩ
SW NMOS-Tr
on resistance
RNMOS
LX3-2 = 30mA
-
220(*1)
-
mΩ
SW PMOS-Tr
leakage current
ILEAK
LX3-1 = 0V
-3
-
-
μA
SW NMOS-Tr
leakage current
ILEAK
LX3-1 = 3.3V
-
-
1
μA
SW PMOS-Tr
leakage current
ILEAK
LX3-2 = 0V
-3
-
-
μA
SW NMOS-Tr
leakage current
ILEAK
LX3-2 = 3.3V
-
-
1
μA
Over current
protection value
ILIMIT
L=1.0µH
1000(*2)
-
-
mA
PFM/PWM mode
changeover current
IPFM
L=1.0µH
-
200(*1)
-
mA
Discharge resistor
RDIS
-
-
5(*1)
-
kΩ
Soft start time
Tss
Soft start time setting:1ms
0.9
1
1.1
ms
Switching frequency
fOSC
-
2.7
3.0
3.3
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08448 Rev.*A Page 17 of 69
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8.5 DD4
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
4. DC/DC converter block [ DD4 ]
Output voltage
VOUT
IOUT = -10mA,
Output voltage setting: 1.0V
0.988
1.000
1.012
V
Input stability
VLINE
IOUT = -10mA,
PVCC4 = 2.5V to 5.5V
-5
-
+5
mV
Load stability
VLOAD
IOUT = -1mA to -4000mA
(Fixed PWM mode)
-10
-
+10
mV
Load stability
VLOAD
IOUT = -1mA to -4000mA
(PFM/PWM mode)
-10
-
+15
mV
IN4 input impedance
RIN
IN4 = 2.0V
-
190(*1)
-
kΩ
SW PMOS-Tr
on resistance
RPMOS
LX4 = -30mA
-
120(*1)
-
mΩ
SW NMOS-Tr
on resistance
RNMOS
LX4 = 30mA
-
80(*1)
-
mΩ
SW PMOS-Tr
leakage current
ILEAK
LX4 = 0V
-3
-
-
µA
SW NMOS-Tr
Leakage current
ILEAK
LX4 = 3.3V
-
-
3
µA
Over current
protection value
ILIMIT
L=1.0µH
2300(*2)
-
-
mA
PFM/PWM mode
changeover current
IPFM
L=1.0µH
-
75(*1)
-
mA
Discharge resistor
RDIS
-
-
5(*1)
-
kΩ
Soft start time
Tss
Soft start time setting: 1ms
0.9
1
1.1
ms
Switching frequency
fOSC
-
2.7
3.0
3.3
MHz
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
*2: No production tested, ensure by design.
Document Number: 002-08448 Rev.*A Page 18 of 69
S6AP413A
8.6 Digital Block
(AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply,
PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25°C, unless otherwise noted.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
1. Power Good block [ Power Good ]
Output voltage
VOL
PG1, PG2, PG3, PG4 IOL = 1mA
-
-
0.4
V
Output current
IOL
PG1, PG2, PG3, PG4
1
-
-
mA
Low voltage detection
VTH
IN1, IN2, IN4 = falling
VO3 = falling
-
Vo0.90
(*1)
-
V
Power on detection
VTH
IN1, IN2, IN4 = rising
VO3 = rising
-
Vo0.93
(*1)
-
V
2. I2C block [ I2C ]
Input voltage
VIH
SCL,SDA
DVCC
×0.7
-
DVCC
V
VIL
SCL,SDA
0
-
DVCC
×0.3
V
Input current
IIH
SCL,SDA
DVCC = 3.3V
-
-
10
µA
IIL
SCL,SDA
DVCC = 3.3V
-10
-
-
µA
Output voltage
VOL
SDA IOL = 3mA
-
-
0.4
V
Output current
IOL
SDA
3
-
-
mA
*1: This parameter is not be specified. This should be used as a reference to support designing the circuits.
Document Number: 002-08448 Rev.*A Page 19 of 69
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9. Operation Mode List
Table 1. Operation Mode List
Mode
Stand-by
Stand-by2
Normal
Error Detection
CTL signal
CTLMAIN (external)
L
H
H
H
CTL1 (external/I2C)
L
L
H/L(*1)
X
CTL2 (external/I2C)
L
L
H/L(*1)
X
CTL3 (external/I2C)
L
L
H/L(*1)
X
CTL4 (external/I2C)
L
L
H/L(*1)
X
Operation Block
Reference
OFF
ON
ON
ON
Digital
OFF
ON
ON
ON
DD1
OFF
OFF
ON/OFF
OFF
DD2
OFF
OFF
ON/OFF
OFF
DD3
OFF
OFF
ON/OFF
OFF
DD4
OFF
OFF
ON/OFF
OFF
I2Ccommunicati
on
I2Ccommunication
disable
enable
enable
enable
Protection
operating
Thermal shut down (TSD)
Not available
Not available
available
(*2)
Over current
protection(OCP)
Not available
Not available
available
(*2)
*1: normal mode means that CTLMAIN pin is "H" level and each DD CTL pin is "H" level
*2: This state is after each err detection. Error state will release, when the power supply voltage
or CTLMAIN pin will turn off and on.
Priority of the External CTL Pin and I2C Communication
CTLMAIN
(External)
CTL1, CTL2,
CTL3, CTL4
(External)
30h Resistor
(I2C)
Relevant
Channel
H
H
1
ON
H
H
0
ON
H
L
1
ON
H
L
0
OFF
L
X
disable
OFF
Notes:
• The I2C communication is valid after the reference control block and digital block activation setting the external CTLMAIN pin
to "H" level.
• Please attention below note about ON/OFF control of DD1, DD2,DD3, DD4 by I2C communication.
When each DD control is turned off by I2C communication and external CTL pin remains "H" level, DCDC converter keep
operating.
Document Number: 002-08448 Rev.*A Page 20 of 69
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10. State Transition Diagram
(1)
External CTLMAIN pin is "H" level.
(2)
External CTLMAIN pin is "L" level.
(3)
External CTL pin or I2C communication "relevant CH_ON"
(4)
External CTL pin or I2C communication "relevant CH_OFF"
(5)
Error detection (TSD, OCP 1ms continuation)
(6)
Turning on the power supply again (equal to or less than uvlo_vcc rest voltage) or setting CTLMAIN to
"L" level
Stand-by
Stand-by 2
General
(1)
(4)
(5)
Error
detection
(6)
(2)
(3)
(2)
Document Number: 002-08448 Rev.*A Page 21 of 69
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11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3, CTL4)
*1: PVCC1, PVCC2, PVCC3, PVCC4
*2: CTL1, CTL2, CTL3, CTL4
*3: DD1, DD2, DD3, DD4
*4: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
93%
DD1
PG1
CTLMAIN
CTL*
DD2
PG2
VREF18
1.8V
Discharge
Discharge
93%
DD3
PG3
Discharge
93%
AVCC
PVCC*
AVCC=2.2V
AVCC=2.0V
DD4
PG4
Discharge
93%
Soft-start timeUVLO release to DD* activation
Time till start (*1)
Typ : (820)µs
Max : TBD µs
osc
(
IC internal signal)
uvlo_vcc
(IC internal signal)
Document Number: 002-08448 Rev.*A Page 22 of 69
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12. Turning ON and OFF Sequence (AVCC →CTLMAIN→CTL1→CTL2→ CTL3→ CTL4)
*1: PVCC1, PVCC2, PVCC3, PVCC4
*2: DD1, DD2, DD3, DD4
*3: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
AVCC
PVCC*
3.3V
93%
DD1
PG1=CTL2
CTLMAIN
CTL1
DD2
PG2=CTL3
VREF18
1.8V
93%
DD3
PG3=CTL4
93%
DD4
PG4
93%
Discharge
Discharge
Discharge
Discharge
Soft-start timeUVLO release to DD* activation
osc
(
IC internal signal)
uvlo_vcc
(IC internal signal)
Time till start (*1)
Typ : (820)µs
Max : TBD µs
Document Number: 002-08448 Rev.*A Page 23 of 69
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13. Turning ON and OFF Sequence (AVCC→CTLMAIN→I2C)
*1: PVCC1, PVCC2, PVCC3, PVCC4
*2: CTL1, CTL2, CTL3
*3: DD1, DD2, DD3
*4: VREF18 activations depend on the VREF18 pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF18 pin capacitance: 1.0µF
AVCC
PVCC*
3.3V
93%
DD1
PG1
CTLMAIN
ctl* (IC internal signal)
DD2
PG2
VREF18
1.8V
93%
DD3
PG3
93%
I2C(DD ON/OFF)
OFF
ON
OFF
DD4
PG4
93%
Discharge
Discharge
Discharge
Discharge
Soft-start timeUVLO release to DD* activation
osc
(
IC internal signal)
uvlo_vcc
(IC internal signal)
Time till start (*1)
Typ : (820)µs
Max : TBD µs
Document Number: 002-08448 Rev.*A Page 24 of 69
S6AP413A
14. CTL Pin Threshold Voltage
The input circuit structure for the CTL(*1) pin is the Schmitt trigger style, and the threshold voltage shows the hysteresis
characteristics when CTL(*1) OFF to ON and ON to OFF.
(See "CTL (*1) Pin Equivalent Circuit Diagram" below.)
Also, the threshold voltage level depends on the VCC pin voltage.
Moreover, make sure to input either the "H" level (>"VCC×0.7"V) or "L" level (<0.4V) to the CTL(*1)pin when in use.
Figure 3. CTL (*1) Pin Equivalent Circuit Diagram
*1: CTLMAIN, CTL1, CTL2, CTL3, CTL4
GND
CTL*
AVCC
ESD protection
element
The CTL threshold voltage
shows the hysteresis
characteristics.
ESD protection
element
Document Number: 002-08448 Rev.*A Page 25 of 69
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15. Protection Operation Sequence
Over Current Protection (DD channel)
The DD channel monitors the peak current of FET at any time during the operation. When the DD output becomes the over current
state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress.
When one of each DD channel stops operation by over current protection, all DD channels stop operation.
Thermal Shut Down
If the temperature at the junction part reaches +150°C, the thermal shutdown protection circuit turns all channels off.
Error Detection Sequence
Figure 4. Error Detection Sequence
Error Detection Mode Release
It is necessary to turn the power supply turning on again, or to turn CTLMAIN turning on again to release the error detection mode.
DD1,DD2,DD3,DD4
Voltage drop
1ms
Continue for 1ms?
No
Normal
operation
Yes
Over current
detection
Normal
operation
Thermal
shutdown
protection
The whole IC
Error detection mode
Error signal output (I2C address 40h)
Document Number: 002-08448 Rev.*A Page 26 of 69
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16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit
Channel
Operation
Whilst
Under
Protection
Over Current Protection
(OCP)
Under Voltage Lockout
Protection
(UVLO)
Thermal Shutdown
Protection
(TSD)
DD1,DD2,DD3,
DD4
Discharge
Operating condition:
After about 1ms progress
in the over current
condition
Process during protection
operation:
DD1, DD2, DD3, DD4
stop
Recovery condition:
(1) Power supply
reasserted
(2) CTLMAIN reasserted
Operating condition:
Input voltage drop
Process during protection
operation:
DD1, DD2, DD3, DD4 stop
Recovery condition: Input
voltage rise
UVLO operates only when
CTLMAIN is "H" (at VREF18
output).
Operating condition:
Chip temperature increment
Process during protection
operation:
DD1, DD2, DD3, DD4 stop
Recovery condition:
(1) Power supply reasserted
(2) CTLMAIN reasserted
Only when CTLMAIN is in
the "H" state and CTL(*1) is
in the "H" state, or when
DD(*2) in operating
condition by I2C, will
operate.
Error output
(address 40h)
-
Write "1" when detecting
OCP
No change
Write "1" when detecting
TSD
Thermal shutdown protection (TSD) operation during over current protection timer operation
When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal
shutdown protection has priority.
Operation when releasing under voltage lockout protection (UVLO)
• DD1,DD2,DD3,DD4: Activation following the condition for CTL(*1) pin or I2C
Note:
• When VREF18 decreases at the time of UVLO operation, I2C register is reset, and all DD does OFF.
It is necessary to let you do ON by CTL(*1) pin and communication again to let DD have ON."
*1: CTL1, CTL2, CTL3, CTL4
*2: DD1, DD2, DD3, DD4
Document Number: 002-08448 Rev.*A Page 27 of 69
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17. DD Soft Start Operation
The soft-start operation for DD1, DD2, DD3 and DD4 is enabled in order to prevent the rush current during the DD activation. The
soft-start time can be controlled by I2C.
About output voltage changing option, soft start time is showed by follow equation.
Tss=Tslp × Vset/Vdef (ms)
Tss: soft start time
Tslp: slope coefficient of soft start
Vset: output voltage setting
Vdef: DD1=1.0, DD2=1.8, DD3=3.3, DD4=1.0
Figure 5. DD Soft Start
t
Output voltage1 setting value
Soft-start time
Channel ON/OFF signal (internal signal)
Output voltage2 setting value
Output voltage3 setting value
Document Number: 002-08448 Rev.*A Page 28 of 69
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18. Discharge Operation
DD Channel
When executing the DD OFF operation at the channel ON/OFF signal, the DC/DC smooth capacitance charged for each output
voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the
discharge time changes depending on the DC/DC converter load current.
The discharge time is calculated by the following equation.
Discharge time (time till the output becomes 10% without load)
toff(s) ≈2.3 ×R_DIS ×COUT (F)
Note:
• See the table in Electrical Characteristics for the discharge resistor value.
Figure 6. Discharge Function
*1: IN1, IN2, IN3, IN4
*2: PVCC1, PVCC2, PVCC3, PVCC4
*3: LX1, LX2, LX3, LX4
*4: PGND1, PGND2, PGND3, PGND4
Error
Amp
R1
R2
Channel ON/OFF Cont.
A
LX(*3)
PVCC(*2)
PGND(*4)
A
Resistor for discharge
Cout
IN(*1)
Reference
voltage
DAC
Document Number: 002-08448 Rev.*A Page 29 of 69
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19. PG Function
The following pins for each channel Power Good output are prepared.
PG1
It is the pin for DD1 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD1 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD1 OFF mode.
PG2
It is the pin for DD2 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD2 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD2 OFF mode.
PG3
It is the pin for DD3 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD3 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD3 OFF mode.
PG4
It is the pin for DD4 Power Good output.
When the output voltage exceeds 93% of the setting value at the DD4 ON mode, "H" is output.
Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output
at the DD4 OFF mode.
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20. I2CInterface
20.1 Structure of I2C Interface
The I2C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a
SDA (serial data line).
This bus is connected to multiple devices;
Master: device to generate the clock signal and to control the data transfer (CPU and so on)
Slave: device that an address is specified by a master.
This IC is set as the slave and has no function to be the master.
Each device is defined due to the communication direction as described below.
Transmitter: device to send data to bus
Receiver: device to receive data from bus
The IC has the function both transmitter and receiver.
The IC defines the followings;
Write: data is transmitted from master and the IC receives data
Read: The IC transmits data and master receives data.
20.2 Definition of Signal Lines
SCL and SDA are connected to the power supply by the pull-up resistor.
The output circuit is the open Drain output.
When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state.
Note:
• SCL and SDA pins adopt a different ESD protection system from standard I2C specification because of ESD enhancement
(See 22.I/O Pin Equivalent Circuit Diagram). When the power supply is in the bus line, do not shut off the power supply for an
IC (DVCC).
SDA
SCL
RR
Pull Up
input
output
input
Inside of IC
I2C bus line power supply
maser
SDA
SCL
slave1 slave2
transmitter
receiver
transmitter
receiver
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20.3 Validity of Data
Data has the following characteristics;
• Change when SCL is the "L" level
• Valid if the state is kept while SCL is the "H" level.
The SDA signal change means the start or stop condition when SCL is the "H" level.
20.4 Definition of Start and Stop Condition
The start and stop conditions are output from the master and shows start and stop of communications to the slave.
• Start: SDA changes from "H" to "L" when SCL is "H".
• Stop: SDA changes from "L" to "H" when SCL is "H".
SDA
SCL
data
state
data
change
data
state
SDA
SCL
S
start
condition
P
stop
condition
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20.5 ACK Signal
This is a signal to confirm the data reception during communication.
The receiver replies the ACK signal to show the data reception to a transmitter every time
1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master
generates.
• A transmitter keeps SDA output "open H" in SCL9clk.
• A receiver informs the data reception situation to a transmitter outputting the followings in SCL
9 calk ;
When data was received: SDA output "L" (ACK)
When no data was received: SDA output "open H" (NACK)
However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open
stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the
stop condition reception waiting state from the master.
SDA
by transmitter
SCL
from master
SDA
by receiver
1
bit0
bit7
8
9
10
H hold
ACK
NACK
bit0
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20.6 I2C Interface Input Timing (Within recommended operating conditions)
Parameter
Symbol
Value
Unit
SCL=100kHz
SCL=400kHz
Min
Max
Min
Max
SCL clock frequency
fSCL
-
100
-
400
kHz
Start condition hold time
tHD:start
4.0
-
0.6
-
µs
Restart condition setup time
tSU:start
4.7
-
0.6
-
µs
Stop condition setup time
tSU:stop
4.0
-
0.6
-
µs
Stop to Start bus open time
tbuf
4.7
-
1.3
-
µs
SCL "L" time
tLow
4.7
-
1.3
-
µs
SCL "H" time
tHigh
4.0
-
0.6
-
µs
SCL/SDA rising time
tr
-
1.0
-
0.3
µs
SCL/SDA falling time
tf
-
0.3
-
0.3
µs
Data hold time
tHD:data
0.0
-
0.0
-
µs
Data setup time
tSU:data
0.25
-
0.10
-
µs
SCL/SDA capacitor load
Cb
-
400
-
400
pF
VIH/VIL level reference
Conform to I2C bus specifications
SDA
SCL
S
Sr
tr
P
tf
tLow
tHigh
tHD:data
tSU:data
tHD:start
tSU:stop
tbuf
tSU:start
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20.7 Slave Address
This is a slave address when communicating with the I2C interface.
The slave address of this IC is set by the first seven bits as shown below.
The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will
be written from the master to the slave.
The bit "1" shows that the master reads information from the slave.
This does not support the general call address.
0 1 0 1 1 0 0 R/W
MSB LSB
S
T
A
R
T
slave address
A
C
K
S
T
O
P
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20.8 Bit Structure of Data on I2C Interface
1. Writing Data to Register and Reading Data
The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB).
Output the "stop" condition after sending the Write data.
: Signal which a master sends, : Signal which this IC sends
No. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
S 0 1 0 1 1 0 0 W 0 0 0 0 0 0 1 0 a b c d e f g h P
slave address register address data
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
D07 D06 D05 D04 D03 D02 D01 D00
00H
01H
02Ha b c d e f g h
03H
04H
:
:
address
data
register
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2. I2C Interface Data Format
About I2C Communication
1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address.
2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting.
3. If a non-existing register address is specified, data is not written to a register.
4. Output the "stop" condition after sending the write data.
<Write (W)>
Write is allowed per one address. (Sequential writing is not allowed.)
Send register address and data as one unit.
: Signal which a master sends, : Signal which this IC sends
<Read(R)>
Read is allowed per one address. Be sure to perform read by specifying the register addresses.
(Sequential reading is not allowed.)
: Signal which a master sends, : Signal which this IC sends
S 0 1 0 1 1 0 0 W P
slave address
register address
data
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
S 0 1 0 1 1 0 0 W S 0 1 0 1 1 0 0 R P
slave address
register address
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
data
A
C
K
S
T
A
R
T
slave address
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21. Structure of I2C Interface and Data
Table 2. Register map
Addr
ess
Data
Writing
Timing
Remarks
d07
d06
d05
d04
d03
d02
d01
d00
Defa
ult
Output
voltage
00H
0
0
0
D04
D03
D02
D01
D00
0FH
ACK
DD1 output voltage
setting
01H
0
0
0
0
D03
D02
D01
D00
0CH
ACK
DD2 output voltage
setting
02H
0
0
0
0
0
D02
D01
D00
05H
ACK
DD3 output voltage
setting
03H
0
0
0
D04
D03
D02
D01
D00
0FH
ACK
DD4 output voltage
setting
Soft start
10H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD1 soft-start time
setting
11H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD2 soft-start time
setting
12H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD3 soft-start time
setting
13H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD4 soft-start time
setting
DD
operation
mode
20H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD operation mode
setting
"0": Fixed PWM
mode,
"1":PFM/PWM mode
ON/OFF
30H
0
0
0
0
D03
D02
D01
D00
00H
ACK
DD output ON/OFF
setting
"0":Output OFF /
"1":Output ON
Error
40H
0
0
0
D04
D03
D02
D01
D00
00H
-
DD error state
monitoring register
(read only)
"0":Normal / "1":Error
detection
PG
50H
0
0
0
0
D03
D02
D01
D00
00H
-
DD PG state
monitoring register
(read only)
"0":Non-output /
"1":output
For test
EXH
-
-
-
-
-
-
-
-
-
-
Disabled
For test
FXH
-
-
-
-
-
-
-
-
-
-
Disabled
Note:
• Address FXH and address EXH are for test.
Do not write/read FXH and EXH.
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21.1 About DD1, DD4 Output Voltage Setting
Address 00H DD1 is allocated as resisters for the DC/DC output voltage setting.
Address 03H DD4 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD1 is controlled by writing data to address 00H.
The DC/DC output voltage setting of DD4 is controlled by writing data to address 03H.
address00H: For DD1 output voltage setting
address03H: For DD4 output voltage setting
D04 to D00: Set the output voltage
DD1, DD4 Output Voltage Setting Table
Data
Output Voltage (V)
Data
Output Voltage (V)
00H
0.700
10H
1.020
01H
0.720
11H
1.040
02H
0.740
12H
1.060
03H
0.760
13H
1.080
04H
0.780
14H
1.100 (*1)
05H
0.800
15H
1.120
06H
0.820
16H
1.140
07H
0.840
17H
1.160
08H
0.860
18H
1.180
09H
0.880
19H
1.200 (*1)
0AH
0.900 (*1)
1AH
1.220
0BH
0.920
1BH
1.240
0CH
0.940
1CH
1.260
0DH
0.960
1DH
1.280
0EH
0.980
1EH
1.300
0FH
1.000 (*1)
1FH
1.320
*1: Preset value
0 0 0 D04 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.2 About DD2 Output Voltage Setting
Address 01H DD2 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD2 is controlled by writing data to address 01H.
address01H: For DD2 output voltage setting
D03 to D00: Set the output voltage
DD2 Output Voltage Setting Table
Data
Output
Voltage(V)
00H
1.200 (*1)
01H
1.250
02H
1.300
03H
1.350 (*1)
04H
1.400
05H
1.450
06H
1.500 (*1)
07H
1.550
08H
1.600
09H
1.650
0AH
1.700
0BH
1.750
0CH
1.800 (*1)
0DH
1.850
0EH
1.900
0FH
1.950
*1: Preset value
0 0 0 0 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.3 About DD3 Output Voltage Setting
Address 02H DD3 is allocated as resisters for the DC/DC output voltage setting.
The DC/DC output voltage setting of DD3 is controlled by writing data to address 02H.
address02H: For DD3 output voltage setting
D02 to D00: Set the output voltage
DD3 Output Voltage Setting Table
Data
Output Voltage(V)
00H
2.80 (*1)
01H
2.90
02H
3.00 (*1)
03H
3.10
04H
3.20
05H
3.30 (*1)
06H
3.40
07H
3.50 (*1)
*1: Preset value
0 0 0 0 0 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.4 About Soft Start Time
Addresses 10H to 12H are allocated as registers for the soft start time control.
The soft start time control is controlled by writing data to addresses 10H to 12H.
address10H: For DD1 soft start time setting
address11H: For DD2 soft start time setting
address12H: For DD3 soft start time setting
address13H: For DD4 soft start time setting
D03 to D00: Set the soft start time
Tss=Tslp × Vset/Vdef (ms)
Tss: soft start time
Tslp: slope coefficient of soft start: refer to follow table
Vset: output voltage setting
Vdef: DD1=1.0, DD2=1.8, DD3= 3.3, DD4=1.0
Soft Start Time Setting
Data
Tslp
Remarks
00H
1.0
DD1,DD2,DD3,DD4 (*1)
01H
2.0
02H
3.0
03H
4.0
04H
5.0
05H
6.0
06H
7.0
07H
8.0
08H
9.0
09H
10.0
0AH
11.0
0BH
12.0
0CH
13.0
0DH
14.0
0EH
15.0
0FH
16.0
*1: Preset value
0 0 0 0 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.5 DC/DC Operation Mode
Address 20H is allocated as a register for the DC/DC operation mode control.
The DC/DC operation mode is controlled by writing data to address 20H.
address20H: For DC/DC operation mode setting
D01 to D00: Set the DC/DC operation mode
Address
Bit
Description
20H
D00
0: DD1 Fixed PWM (*1)
1: DD1 PFM/PWM
20H
D01
0: DD2 Fixed PWM (*1)
1: DD2 PFM/PWM
20H
D02
0: DD3 Fixed PWM (*1)
1: DD3 PFM/PWM
20H
D03
0: DD4 Fixed PWM (*1)
1: DD4 PFM/PWM
*1: Preset value
0 0 0 0 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.6 ON/OFF for DC/DC
Address 30H is allocated as a register for the DC/DC ON/OFF.
The DC/DC ON/OFF is controlled by writing data to address 30H.
address30H: For DC/DC ON/OFF
D02 to D00: Set ON/OFF for DC/DC
Address
Bit
Description
30H
D00
0: DD1 output OFF (*1)
1: DD1 output ON
30H
D01
0: DD2 output OFF (*1)
1: DD2 output ON
30H
D02
0: DD3 output OFF (*1)
1: DD3 output ON
30H
D03
0: DD4 output OFF (*1)
1: DD4 output ON
*1: Preset value
0 0 0 0 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.7 About Error Monitor
Address 40H is allocated as error status monitor of each DC/DC output and thermal shut down.
Address 40H is read only resistor.
address40H: For error monitor of each DC/DC output and thermal shut down
D04 to D00: read only resistor. (Not allowed write resistor)
Address
Bit
Description
40H
D00
0: DD1 OCP non detection (*1)
1: DD1 OCP detection
40H
D01
0: DD2 OCP non detection (*1)
1: DD2 OCP detection
40H
D02
0: DD3 OCP non detection (*1)
1: DD3 OCP detection
40H
D03
0: DD4 OCP non detection (*1)
1: DD4 OCP detection
40H
D04
0: TSD non detection (*1)
1: TSD detection
*1: Preset value
0 0 0 D04 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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21.8 About Power Good Monitor
Address 50H is allocated as output monitor of each DC/DC output.
Address 50H is read only resistor.
address50H: For output monitor of each DC/DC output.
Detection level is over 93% of DCDC output voltage setting.
D04 to D00: read only resistor. (Not allowed write resistor)
Address
Bit
Description
50H
D00
0: DD1 non output (*1)
1: DD1 output
50H
D01
0: DD2 non output (*1)
1: DD2 output
50H
D02
0: DD3 non output (*1)
1: DD3 output
50H
D03
0: DD4 non output (*1)
1: DD4 output
*1: Preset value
0 0 0 0 D03 D02 D01 D00
MSB LSB
S
T
A
R
T
Data
A
C
K
S
T
O
P
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22. I/O Pin Equivalent Circuit Diagram
<<AVCC>>
<<VREF18>>
<<IN1,IN2,IN4,LX1,LX2,LX4,PGND1,PGND2,PGND4>>
AVCC
GND
ESD
protection
element
AVCC
VREF18
GND
IN*: IN1, IN2, IN4
LX*: LX1, LX2, IN4
PGND*: PGND1, PGND2, PGN4
IN*
AVCC
GND
LX*
PGND*
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<<PVCC1,PVCC2,PVCC4>
<<IN3,PGND3 >
<<PVCC3,LX3-1,LX3-2,VO3>>
PGND3
PVCC3
VO3
GND
AVCC
LX3-1
LX3-2
LX*
PGND*
PVCC*
AVCC
GND
PVCC*: PVCC1, PVCC2, PVCC4
LX*: LX1, LX2, LX4
PGND*: PGND1, PGND2, PGND4
IN3
GND
PGND3
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<<CTL*>> <<PG*>>
<<SCL>> <<SDA>>
GND
SCL
DVCC
GND
SDA
DVCC
GND
AVCC
CTL*
CTL*: CTLMAIN, CTL1,
CTL2, CTL3, CTL4
GND
PG*
AVCC PG*: PG1, PG2, PG3, PG4
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23. Measurement Circuit for Characteristics of General Operation
PVCC4
DD1:1.0V
Io(max):2000mA
PVCC1 LX1
PGND1
PG1
DD2:1.80V
Io(max):1200mA
LX2
PGND2
PG2
C2
4.7mF
L1
R1
100kW
C8
22mF
C5
4.7mF
C1
0.1mF
C6
1.0mF
IN1
CTL1
CTL4
AVCC
CTLMAIN
DVCC
SCL
SDA
VREF18 GND
S6AP413A
SCL
SDA
3.3V
PVCC3
C4
4.7mF
CTL3
L2
PG1
PVCC2
C3
4.7mFIN2
R2
100kW
PG2
LX3-1
LX3-2
VO3 C9
33mF
L3
PG3
R3
100kW
PG3
PGND3
C7
47mF
DD3:3.30V
Io(max):600mA
CTL2
C10
47mF
LX4 L4
PGND4
IN4
PG4
R4
100kW
PG4
DD4:1.0V
Io(max):2000mA
Input Voltage:
2.5V to 5.5V
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Table 3. Parts list
Symbol
Parts
Part Number
Specifications
Vendor
L1
Inductor
1276AS-H-1R0M
1.0µH
TOKO
L2
Inductor
1276AS-H-1R0M
1.0µH
TOKO
L3
Inductor
1276AS-H-1R0M
1.0µH
TOKO
L4
Inductor
1276AS-H-1R0M
1.0µH
TOKO
C1
Ceramic Capacitor
C1608X5R1H104K
0.1µF
TDK
C2
Ceramic Capacitor
C1608X5R1V475K
4.7µF
TDK
C3
Ceramic Capacitor
C1608X5R1V475K
4.7µF
TDK
C4
Ceramic Capacitor
C1608X5R1V475K
4.7µF
TDK
C5
Ceramic Capacitor
C1608X5R1V475K
4.7µF
TDK
C6
Ceramic Capacitor
C2012X5R1A336M
1.0µF
TDK
C7
Ceramic Capacitor
C2012X5R1A476M
47µF
TDK
C8
Ceramic Capacitor
C1608X5R1A226M
22µF
TDK
C9
Ceramic Capacitor
C2012X5R1A336M
33µF
TDK
C10
Ceramic Capacitor
C2012X5R1A476M
47µF
TDK
R1
Resistor
RR0816P-104-D
100kΩ
SSM
R2
Resistor
RR0816P-104-D
100kΩ
SSM
R3
Resistor
RR0816P-104-D
100kΩ
SSM
R4
Resistor
RR0816P-104-D
100kΩ
SSM
TOKO : TOKO, INC.
TDK : TDK Corporation
SSM : SUSUMU CO., LTD.
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24. Reference Data
DCDC Convertor Efficiency Data
DD1,DD4
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.2V setting
Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 5.5V, Vo = 1.2V setting
DD2
Input Voltage = 3.3V, Vo = 1.5V setting Input voltage = 3.3V, Vo = 1.8V setting
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
Inductor and capacitor value refer to section 26.
Document Number: 002-08448 Rev.*A Page 52 of 69
S6AP413A
DD2
Input voltage = 5.5V, Vo = 1.5V setting Input Voltage = 5.5V, Vo = 1.8V setting
DD3
Input voltage = 3.3V, Vo = 3.3V setting Input Voltage = 5.5V, Vo = 3.3V setting
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
0
10
20
30
40
50
60
70
80
90
100
0.00001 0.001 0.1 10
Efficiency[%]
Load current[A]
Fixed PWM
PFM/PWM
Document Number: 002-08448 Rev.*A Page 53 of 69
S6AP413A
DCDC Convertor Regulation Data
DD1,DD4
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.2V setting
Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 5.5V, Vo = 1.2V setting
DD2
Input Voltage = 3.3V, Vo = 1.5V setting Input voltage = 3.3V, Vo = 1.8V setting
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0.0 0.5 1.0 1.5 2.0
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0.0 0.5 1.0 1.5 2.0
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0.0 0.5 1.0 1.5 2.0
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0.0 0.5 1.0 1.5 2.0
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
0.0 0.4 0.8 1.2
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0.0 0.4 0.8 1.2
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
Document Number: 002-08448 Rev.*A Page 54 of 69
S6AP413A
DD2
Input voltage = 5.5V, Vo = 1.5V setting Input Voltage = 5.5V, Vo = 1.8V setting
DD3
Input voltage = 3.3V, Vo = 3.3V setting Input Voltage = 5.5V, Vo = 3.3V setting
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
0.0 0.4 0.8 1.2
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0.0 0.4 0.8 1.2
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0.0 0.2 0.4 0.6
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0.0 0.2 0.4 0.6
Output voltage[V]
Load current[A]
Fixed PWM
PFM/PWM
Document Number: 002-08448 Rev.*A Page 55 of 69
S6AP413A
DCDC Convertor Output Ripple Voltage
DD1, DD4
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = 0mA , Fixed PWM Load current = 2000mA, Fixed PWM
Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 5.5V, Vo = 1.0V setting
Load current = 0mA , Fixed PWM Load current = 2000mA, Fixed PWM
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = 0mA , PFM/PWM Load current = 2000mA,PFM/PWM
Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 5.5V, Vo = 1.0V setting
Load current = 0mA , PFM/PWM Load current = 2000mA,PFM/PWM
10mV/div,0.5μs/div
10mV/div, 0.5μs/div
10mV/div,0.5μs/div
10mV/div, 0.5μs/div
10mV/div, 2ms/div
10mV/div,0.5μs/div
10mV/div, 0.5μs/div
10mV/div,2ms/div
Document Number: 002-08448 Rev.*A Page 56 of 69
S6AP413A
DD2
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = 0mA , Fixed PWM Load current = 1200mA, Fixed PWM
Input voltage = 5.5V, Vo = 1.8V setting Input voltage = 5.5V, Vo = 1.8V setting
Load current = 0mA , Fixed PWM Load current =1200mA, Fixed PWM
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = 0mA , PFM/PWM Load current =1200mA,PFM/PWM
Input voltage = 5.5V, Vo = 1.8V setting Input voltage = 5.5V, Vo = 1.8V setting
Load current = 0mA , PFM/PWM Load current = 1200mA,PFM/PWM
10mV/div,0.5μs/div
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
10mV/div,0.5μs/div
10mV/div, 2ms/div
10mV/div, 0.5μs/div
10mV/div, 2ms/div
10mV/div,0.5μs/div
Document Number: 002-08448 Rev.*A Page 57 of 69
S6AP413A
DD3
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3V setting
Load current = 0mA , Fixed PWM Load current = 600mA, Fixed PWM
Input voltage = 5.5V, Vo = 3.3V setting Input voltage = 5.5V, Vo = 3.3V setting
Load current = 0mA , Fixed PWM Load current =600mA, Fixed PWM
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3V setting
Load current = 0mA , PFM/PWM Load current = 600mA,PFM/PWM
Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 3.3V, Vo =3.3V setting
Load current = 0mA , PFM/PWM Load current = 600mA,PFM/PWM
10mV/div, 2ms/div
10mV/div,0.5μs/div
10mV/div, 2ms/div
10mV/div, 0.5μs/div
10mV/div,0.5μs/div
10mV/div,0.5μs/div
10mV/div, 0.5μs/div
10mV/div, 0.5μs/div
Document Number: 002-08448 Rev.*A Page 58 of 69
S6AP413A
DCDC Convertor Enable/disable
DD1,DD4(Fixed PWM)
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = 2000mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
DD1,DD4(PFM/PWM)
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = 2000mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
DD2(Fixed PWM)
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = 1200mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
PG1(6V/div)
Vo(0.5V/div)
IIN(1.0A/div)
1.0ms
200us/div
SCL(3V/div)
PG1(6V/div)
200ms/div
Vo(0.5V/div)
IIN(40mA/div)
500ms
SCL(3V/div)
PG1(6V/div)
Vo(0.5V/div)
IIN(1.0A/div)
1.0ms
200us/div
SCL(3V/div)
PG1(6V/div)
200ms/div
Vo(0.5V/div)
IIN(40mA/div)
500ms
SCL(3V/div)
PG2(6V/div)
Vo(1V/div)
IIN(500mA/div)
1.02ms
200us/div
SCL(3V/div)
PG2(6V/div)
50ms/div
Vo(1V/div)
IIN(40mA/div)
200ms
Document Number: 002-08448 Rev.*A Page 59 of 69
S6AP413A
DD2(PFM/ PWM)
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = 1200mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting
Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
DD3 (PFM/PWM)
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting
Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
SCL(3V/div)
PG2(6V/div)
Vo(1V/div)
IIN(500mA/div)
1.03ms
200us/div
SCL(3V/div)
PG2(6V/div)
50ms/div
Vo(1V/div)
IIN(40mA/div)
204ms
SCL(3V/div)
PG3(6V/div)
Vo(2V/div)
IIN(500mA/div)
0.99ms
200us/div
SCL(3V/div)
PG3(6V/div)
100ms/div
Vo(2V/div)
IIN(40mA/div)
255ms
SCL(3V/div)
PG3(6V/div)
Vo(2V/div)
IIN(500mA/div)
1.0ms
200us/div
SCL(3V/div)
PG3(6V/div)
100ms/div
Vo(2V/div)
IIN(40mA/div)
255ms
Document Number: 002-08448 Rev.*A Page 60 of 69
S6AP413A
DCDC Convertor Load Transient
DD1(Fixed PWM)
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = from 0mA to 2000mA per 10us Load current = from 2000mA to 0mA per 10us
DD1(PFM/PWM)
Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting
Load current = from 0mA to 2000mA per 10us Load current = from 2000mA to 0mA per 10us
DD2(Fixed PWM)
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = from 0mA to 1200mA per 10us Load current = from 1200mA to 0mA per 10us
10us
Io(1.0A/div)
43.3mV
Vo1(30mV/div)
offset：1.0V
10us
40.5mV
Io(2.0A/div)
Vo1(100mV/div)
offset：1.000V
10us
Io(1.0A/div)
42.9mV
Vo1(30mV/div)
offset：1.0V
50ms
40.5mV
Io(1.0A/div)
Vo1(30mV/div)
offset：1.0V
10us
Io(1.0A/div)
54.8mV
Vo2(50mV/div)
offset：1.8V
10us
54.1mV
Io(1.0A/div)
Vo1(50mV/div)
offset：1.8V
Document Number: 002-08448 Rev.*A Page 61 of 69
S6AP413A
DD2(PFM/ PWM)
Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting
Load current = from 0mA to 1200mA per 10us Load current = from 1200mA to 0mA per 10us
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting
Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
DD3 (Fixed PWM)
Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting
Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting
10us
Io(1.0A/div)
54.0mV
Vo2(50mV/div)
offset：1.8V
10us
Io(500mA/div)
67.4mV
Vo3(50mV/div)
offset：3.3V
10us
57.1mV
Io(500mA/div)
Vo3(50mV/div)
offset：3.3V
10us
Io(500mA/div)
84.1mV
Vo3(50mV/div)
offset：3.3V
20ms
81.7mV
Io(500mA/div)
Vo3(100mV/div)
offset：3.3V
10ms
57.1mV
Io(1.0A/div)
Vo1(50mV/div)
offset：1.8V
Document Number: 002-08448 Rev.*A Page 62 of 69
S6AP413A
DCDC Convertor DVFS Function
DD1 (Fixed PWM)
Input voltage = 3.3V, Input voltage = 3.3V
Vo =from 0.7V to 1.32V setting by I2C Vo =from 1.32V to 0.7V setting by I2C
SCL
(2V/div)
PG
(5V/div)
Vo1
(200mV/div)
offset0.7V
100us
SCL
(2V/div)
PG
(5V/div)
Vo1
(200mV/div)
offset0.7V
100us
Document Number: 002-08448 Rev.*A Page 63 of 69
S6AP413A
25. Ordering Information
Table 4. Ordering Information
Part Number
Package
Remarks
S6AP413A18GN1C000
32-pin plastic QFN
(WNT032)
S6AP413A19GN1C000
S6AP413A1AGN1C000
S6AP413A1BGN1C000
S6AP413A28GN1C000
S6AP413A29GN1C000
S6AP413A2AGN1C000
S6AP413A2BGN1C000
S6AP413A38GN1C000
S6AP413A39GN1C000
S6AP413A3AGN1C000
S6AP413A3BGN1C000
S6AP413A5AGN1C000
S6AP413A5BGN1C000
S6AP413A69GN1C000
S6AP413A6AGN1C000
S6AP413A6BGN1C000
S6AP413A79GN1C000
S6AP413A7AGN1C000
S6AP413A7BGN1C000
S6AP413A9AGN1C000
S6AP413A9BGN1C000
S6AP413AAAGN1C000
S6AP413AABGN1C000
S6AP413ABAGN1C000
S6AP413ABBGN1C000
S6AP413ADBGN1C000
S6AP413AEBGN1C000
S6AP413AFBGN1C000
Document Number: 002-08448 Rev.*A Page 64 of 69
S6AP413A
26. Preset Code List
Preset Code
DD1 Output Voltage
Preset Code Value
DD2 Output Voltage
Preset Code Value
DD3 Output
Voltage
Preset Code Value
DD3 Output
Voltage
Preset Code Value
18
0.90V
1.35V
3.30V
0.90V
19
0.90V
1.35V
3.30V
1.00V
1A
0.90V
1.35V
3.30V
1.10V
1B
0.90V
1.35V
3.30V
1.20V
28
0.90V
1.50V
3.30V
0.90V
29
0.90V
1.50V
3.30V
1.00V
2A
0.90V
1.50V
3.30V
1.10V
2B
0.90V
1.50V
3.30V
1.20V
38
0.90V
1.80V
3.30V
0.90V
39
0.90V
1.80V
3.30V
1.00V
3A
0.90V
1.80V
3.30V
1.10V
3B
0.90V
1.80V
3.30V
1.20V
59
1.00V
1.35V
3.30V
1.00V
5A
1.00V
1.35V
3.30V
1.10V
5B
1.00V
1.35V
3.30V
1.20V
69
1.00V
1.50V
3.30V
1.00V
6A
1.00V
1.50V
3.30V
1.10V
6B
1.00V
1.50V
3.30V
1.20V
79
1.00V
1.80V
3.30V
1.00V
7A
1.00V
1.80V
3.30V
1.10V
7B
1.00V
1.80V
3.30V
1.20V
9A
1.10V
1.35V
3.30V
1.10V
9B
1.10V
1.35V
3.30V
1.20V
AA
1.10V
1.50V
3.30V
1.10V
AB
1.10V
1.50V
3.30V
1.20V
BA
1.10V
1.80V
3.30V
1.10V
BB
1.10V
1.80V
3.30V
1.20V
DB
1.20V
1.35V
3.30V
1.20V
EB
1.20V
1.50V
3.30V
1.20V
FB
1.20V
1.80V
3.30V
1.20V
Document Number: 002-08448 Rev.*A Page 65 of 69
S6AP413A
27. Layout
Consider the points listed below and do the layout design.
• Provide the ground plane as much as possible on the IC mounted face. GND and PGNDx provide the through hole proximal to
GND and PGNDx pins of IC, and connect it with GND of internal layer.
• Provide the power plane as much as possible to lower impedance of VCC.
• Play the most attention to the loop composed of input capacitor (CPVCCx) and SWFET. Input capacitor (CPVCCx) connected
with PVCCx should be placed close to the pin as much as possible to make the current loop as small as possible. Also
connect the GND pin of the input capacitor with PGNDx.
• Output capacitor (CVO3) connected with VO3 should be placed close to the pin as much as possible. Also connect the GND
pin of the output capacitor with PGND3.
• GND pins of the switching system parts provide the through hole at the proximal place, and connect it with GND of internal
layer.
• By-pass capacitor (CVREF, CAVCC) connected with VREF and AVCC should be placed close to the pin as much as possible.
Also connect the GND pin of the by-pass capacitor with GND of internal layer in the proximal through-hole.
• Pull the feedback line to be connected to the INx pin of the IC separately from near the output capacitor pin, whenever
possible. Consider the line connected with INx pins to keep away from a switching system parts as much as possible because
it is sensitive to the noise.
• There is leaked magnetic flux around the inductor or backside of place equipped with inductor.
Line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with
inductor).
Switching system parts: Input capacitor (CPVCCx), Inductor (L), Output capacitor(CVOx)
Note:
• x: Each channel number
Figure 7. Layout Example
(Top View)
EP(Exposed Pad)
C
AVCC
C
VREF
C
VO3
1pin
GND
Surfase
Layer
Inner
Layer
Through Hole
C
PVCC1
C
PVCC4
C
PVCC3
C
PVCC2
GND
PVCC3
PVCC2
PGND3
PGND2
PGND1
PGND4
PVCC1
PVCC4
VREF
AVCC
VO3
CPVCCx
L
CVOx
To the LXx pin
Output voltage
VOx
feedback
GND
PVCCx
PGNDx
PVCC3
L
To the LX3-2 pin
To
the LX3-1
pin
GND
C
VO3
Output voltage
VO
3 feedback
C
PVCC
3
PGND3
Layout example of switching components 1
Layout example of switching components 2
Layout example of IC
Document Number: 002-08448 Rev.*A Page 66 of 69
S6AP413A
28. Package Dimensions
Document Number: 002-08448 Rev.*A Page 67 of 69
S6AP413A
29. Major Changes
Spansion Publication Number: S6AP413A_DS405-00019
Page
Section
Descriptions
Revision 0.1
-
-
Initial release
Revision 1.0
-
-
Preliminary → Full production
52
26. Measurement Circuit for
Characteristics of General Operation
Revised the Parts number of Component list
1278AS-H-1R0M 1276AS-H-1R0M
65
28. Ordering Information
Revised the Part number of Ordering Information
NOTE: Please see “Document History” about later revised information.
Document Number: 002-08448 Rev.*A Page 68 of 69
S6AP413A
Document History
Document Title: S6AP413A 4ch DC/DC Converter with I2C Interface and Internal SW FETs
Document Number: 002-08448
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
-
TAOA
12/26/2014
Migrated to Cypress and assigned document number 002-08448.
No change to document contents or format.
*A
5146815
TAOA
02/26/2016
Updated to Cypress format.
Document Number: 002-08448 Rev.*A February 26, 2016 Page 69 of 69
S6AP413A
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2014-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then
Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form,
to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end
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