58
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
HUF76107D3, HUF76107D3S
20A, 30V, 0.052 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power
MOSFETs are manufactured using
the innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding perfor mance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications
where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay
drivers, low-voltage bus switches, and power management
in portable and battery-operated products.
Formerly developmental type TA76107.
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.052Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76107D3 TO-251AA 76107D
HUF76107D3S TO-252AA 76107D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the T O-252AA v ariant in tape and reel, e.g., HUF76107D3ST.
D
G
S
JEDEC TO-251AA JEDEC TO-252AA
DRAIN
(FLANGE) DRAIN
SOURCE
GATE DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet July 1999 File Number 4701.1
59
Absolute Maximum Ratings TC= 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 30 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±16 V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC= 100oC, VGS = 5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
20
10.5
10
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
0.30 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TA= 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 30 - - V
Zero Gate Voltage Drain Current IDSS VDS = 25V, VGS = 0V - - 1 µA
VDS = 25V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resistance rDS(ON) ID = 20A, VGS = 10V (Figure 9, 10) - 0.042 0.052 Ω
ID = 10.5A, VGS = 5V (Figure 9) - 0.058 0.080 Ω
ID = 10A, VGS = 4.5V (Figure 9) - 0.065 0.085 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 3.3 oC/W
Thermal Resistance Junction to Ambient RθJA TO-251, TO-252 - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time tON VDD = 15V, ID≅ 10A, RL = 1.50Ω,
VGS =4.5V, RGS = 33Ω
(Figure 15)
- - 120 ns
Turn-On Delay Time td(ON) -14-ns
Rise Time tr-66-ns
Turn-Off Delay Time td(OFF) -16-ns
Fall Time tf-22-ns
Turn-Off Time tOFF - - 57 ns
HUF76107D3, HUF76107D3S
60
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 15V, ID≅ 20A, RL =0.75Ω,
VGS =10V, RGS = 33Ω
(Figures 16)
- - 75 ns
Turn-On Delay Time td(ON) -18-ns
Rise Time tr-30-ns
Turn-Off Delay Time td(OFF) -62-ns
Fall Time tf-20-ns
Turn-Off Time tOFF - - 125 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 15V,ID≅ 10.5A,
RL = 1.43Ω
Ig(REF) = 1.0mA
(Figure 14)
- 8.6 10.3 nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 4.7 5.7 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 0.35 0.42 nC
Gate to Source Gate Charge Qgs - 1.00 - nC
Gate to Drain “Miller” Charge Qgd - 2.40 - nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz
(Figure 13) - 315 - pF
Output Capacitance COSS - 170 - pF
Reverse Transfer Capacitance CRSS -30-pF
Electrical Specifications TA= 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 10.5A - - 1.25 V
Reverse Recovery Time trr ISD = 10.5A, dISD/dt = 100A/µs--39ns
Reverse Recovered Charge QRR ISD = 10.5A, dISD/dt = 100A/µs--49nC
Typical Performance Curves
Unless otherwise specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
10
025 50 75 100 125
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
25
150
5
20
VGS = 4.5V
VGS = 10V
15
HUF76107D3, HUF76107D3S
61
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
Typical Performance Curves
Unless otherwise specified (Continued)
t, RECTANGULAR PULSE DURATION (s)
10-5 10-1 100
2
0.1
1
10-2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
0.01 10-4 10-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
101
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
TC = 25oC
I = I25 150 - TC
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
IDM, PEAK CURRENT (A)
500
10
10-5 10-4 10-3 10-2 10-1 100101
t, PULSE WIDTH (s)
100
VGS = 5V
TJ = MAX RATED
TC = 25oC
10ms
1ms
VDSS(MAX) = 30V
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
1001 VDS, DRAIN TO SOURCE VOLTAGE (V)
1
100
200
10
ID, DRAIN CURRENT (A)
10
100µs
1 10 100
100
0.01
200
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0.1
10
0.001
HUF76107D3, HUF76107D3S
62
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless otherwise specified (Continued)
0126
0
10
20
25
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
150oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
30
45
3
15
5VGS = 3.5V
VGS = 4V
01 3456
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 5V
VGS = 10V
VGS = 3V
VGS = 4.5V
2
0
10
20
25
30
15
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
50
60
70
90
30 4
VGS, GATE TO SOURCE VOLTAGE (V)
26108
ID = 20A
ID = 12A
ID = 5A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
40
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.50
0.75
1.00
1.25
1.75
-60 0 60 120
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
180
1.50
2.00
120
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
-60 0 60 120
0.6
0.8
0.9
1.1
1.2
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
180
1.0
0.7
0.6
1.15
1.10
1.00
0.95
0.90-60 0 60 120
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
180
1.05
HUF76107D3, HUF76107D3S
63
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless otherwise specified (Continued)
COSS
600
400
00 5 15 25
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
30
100
CISS
CRSS
10 20
500
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
10
8
6
4
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 15V
2
8100
Qg, GATE CHARGE (nC)
2
ID = 20A
ID = 12A
ID = 5A
WAVEFORMS IN
DESCENDING ORDER:
6
4
20
20 30 40 500
100
80
40
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(OFF)
td(ON)
tr
tf
VGS = 4.5V, VDD = 15V, ID = 10A, RL= 1.50Ω
60
40
20 30 40 500
100
80
60
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(OFF)
td(ON)
tf
tr
VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω
20
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF76107D3, HUF76107D3S
64
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORMS
Test Circuits and Waveforms
(Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
VDS
VGS
Ig(REF)
0
0
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76107D3, HUF76107D3S
65
PSPICE Electrical Model
SUBCKT HUF76107 2 1 3 ; REV June 1998
CA 12 8 4.2e-10
CB 15 14 4.9e-10
CIN 6 8 2.85e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 35.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 3.61e-9
LSOURCE 3 7 3.61e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-3
RGATE 9 20 3.39
RLDRAIN 2 5 10
RLGATE 1 9 36.1
RLSOURCE 3 7 36.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),7))}
.MODEL DBODYMOD D (IS = 2.8e-13 IKF = 5 RS = 1.37e-2 TRS1 = 2e-4 TRS2 = 2e-6 CJO = 4.9e-10 TT = 2.88e-8 M = 3.9e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 3.2e-10 IS = 1e-30 N = 10 M = 7.4e-1)
.MODEL MMEDMOD NMOS (VTO = 2.07 KP = 1.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.4 KP = 19.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.8 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS=.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 3.9e-2 TC2 = 5.5e-5)
.MODEL RSLCMOD RES (TC1 = 1e-4 TC2 = 3.2e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-12 TC2 = 6e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -5.96e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.4e-3 TC2 = 1e-10)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.2 VOFF= -0.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= -4.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= 0.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.0 VOFF= -0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76107D3, HUF76107D3S
66
SABER Electrical Model
nom temp=25 deg c 30v LL Ultrafet
REV Junel 1998
template huf76107 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=2.8e-13, xti=4.75, cjo=4.9e-10,tt=2.88e-8, m=3.9e-1)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=3.2e-10,is=1e-30,n=10,m=7.4e-1)
m..model mmedmod = (type=_n,vto=2.07,kp=1.25,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=19.5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.8,kp=1e-1,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.2,voff=-0.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-4.2)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.0,voff=-0.8)
c.ca n12 n8 = 4.2e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 2.85e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.61e-9
l.lsource n3 n7 = 3.61e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.94e-4,tc2=-9.84e-8
res.rdbody n71 n5 =1.37e-2, tc1=2e-4, tc2=2e-6
res.rdbreak n72 n5 =2.5e-1, tc1=9.94e-4, tc2=9.12e-7
res.rdrain n50 n16 = 3.7e-3, tc1=3.9e-2,tc2=5.5e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 36.1
res.rlsource n3 n7 = 36.1
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=3.2e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 30e-3, tc1=1e-12,tc2=6e-6
res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-10
res.rvthres n22 n8 = 1, tc1=-1.9e-3,tc2=-5.96e-6
spe.ebreak n11 n7 n17 n18 = 35.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/50))**7 ))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76107D3, HUF76107D3S
67
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SPICE Thermal Model
REV June1998
HUF76107
CTHERM1 th 6 5.0e-5
CTHERM2 6 5 9.0e-4
CTHERM3 5 4 1.3e-3
CTHERM4 4 3 1.3e-3
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 7.9e-3
RTHERM1 th 6 2.0e-4
RTHERM2 6 5 6.0e-3
RTHERM3 5 4 3.5e-2
RTHERM4 4 3 8.5e-1
RTHERM5 3 2 5.1e-1
RTHERM6 2 tl 1
SABER Thermal Model
SABER thermal model HUF76107
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-5
ctherm.ctherm2 6 5 = 9.0e-4
ctherm.ctherm3 5 4 = 1.3e-3
ctherm.ctherm4 4 3 = 1.3e-3
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 7.9e-3
rtherm.rtherm1 th 6 = 2.0e-4
rtherm.rtherm2 6 5 = 6.0e-3
rtherm.rtherm3 5 4 = 3.5e-2
rtherm.rtherm4 4 3 = 8.5e-1
rtherm.rtherm5 3 2 = 5.1e-1
rtherm.rtherm6 2 tl = 1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76107D3, HUF76107D3S
