Am50DL128CH70IS - Advanced Micro Devices

July 2003

The follo wing document specifies Spansi on memory p roducts t hat are now of fered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the re sult of normal datasheet improvement and are noted in the

document revis ion summary, where suppo rted. Future routine revisions will occur whe n appropriate,

and changes will be noted in a revision su mmary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support e xisting part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Or dering Part Number s lis ted in this docu ment.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory soluti ons.

Am50DL128CH

Data Sheet

Publication Number 30776 Revision AAmendment +3 Issue Date February 6, 2004

THIS PAGE LEFT INTENTIONALLY BLANK.

ADVANCE INFORMATION

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 30776 Rev: AAmendment/+3

Issue Date: February 6, 2004

Refer to AMD’s Website (www.amd.com) for the latest information.

Am50DL128CH

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation

Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode

DISTINCTIVE CHARACTERISTICS

MCP Features

■Power supply voltage of 2.7 to 3.3 volt

■High performance

— Access time as fast as 55 ns

■Package

— 88-Ball FBGA

■Operating Temperature

— –40°C to +85°C

Flash Memory Features

ARCHITECTURAL ADVANTAGES

■Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

— Zero latency between read and write operations

■Flexible Bank™ architecture

— Read may occur in any of the three banks not being written

or erased.

— Four banks may be grouped by customer to achieve desired

bank divisions.

■Manufactured on 0.13 µm process technology

■SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector

—

Factory locked and identifiable:

16 bytes available for

secure, random factory Electronic Serial Number; verifiable

as factory locked through autoselect function. ExpressFlash

option allows entire sector to be available for

factory-secured data

—

Customer lockable:

Sector is one-time programmable. Once

sector is locked, data cannot be changed.

■Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

■Boot sectors

— Top and bottom boot sectors in the same device

■Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■High performance

— Access time as fast as 55 ns

— Program time: 4 µs/word typical utilizing Accelerate function

■Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■Minimum 1 million write cycles guaranteed per sector

■20 year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

■Supports Common Flash Memory Interface (CFI)

■Program/Erase Suspend/Erase Resume

— Suspends program/erase operations to allow

programming/erasing in same bank

■Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■Any combination of sectors can be erased

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

the read mode

■WP#/ACC input pin

— Write protect (WP#) function protects sectors 0, 1, 140, and

141, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■Sector protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or

erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

pSRAM Features

■Power dissipation

— Operating: 50 mA maximum

— Standby: 100 µA maximum

— Deep power-down standby: 5 µA

■CE1s# and CE2s Chip Select

■Power down features using CE1s# and CE2s

■Data retention supply voltage: 2.7 to 3.3 volt

■Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

■8-word page mode access

2 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

GENERAL DESCRIPTION

Am29DL640H Features

The Am29DL640H is a 64 megabit, 3.0 volt-only flash

memory device, organized as 4,194,304 words of 16

bits each. Word mode data appears on DQ15–DQ0.

The device is designed to be programmed in-system

with the standard 3.0 volt VCC supply, and can also be

programmed in standard EPROM programmers.

The device is available with an access time of 55, 70

or 85 ns and is offered in a 88-ball FBGA package.

Standard control pins—chip enable (CE#f), write en-

able (WE#), and output enable (OE#)—control normal

read and write operations, and avoid bus contention

issues.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into four banks, two 8 Mb banks with small and

large sectors, and two 24 Mb banks of large sectors

only. Sector addresses are fixed, system software can

be used to form user-defined bank groups.

During an Erase/Program operation, any of the three

non-busy banks may be read from. Note that only two

banks can operate simultaneously. The device can im-

prove overall system performance by allowing a host

system to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system from

waiting for the completion of program or erase

operations.

The Am29DL640H can be organized as both a top and

bottom boot sector configuration.

The SecSi™ (Secured Silicon) Sector is an extra

256 byte sector capable of being permanently locked

by AMD or customers. The SecSi Indicator Bit (DQ7)

is permanently set to a 1 if the part is factory locked,

and set to a 0 if customer lockable. This way, cus-

tomer lockable parts can never be used to replace a

factory locked part.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

other flash sector, or may permanently lock their own

code there.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Bank Megabits Sector Sizes

Bank 1 8 Mb Eight 4 Kword,

Fifteen 32 Kword

Bank 2 24 Mb Forty-eight 32 Kword

Bank 3 24 Mb Forty-eight 32 Kword

Bank 4 8 Mb Eight 4 Kword,

Fifteen 32 Kword

February 6, 2004 Am50DL128CH 3

ADVANCE INFORMATION

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .5

Flash Memory Block Diagram . . . . . . . . . . . . . . . .6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations—Flash Word Mode .....................11

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Word Configuration ................................................................. 12

Requirements for Reading Array Data ................................... 12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12

Autoselect Functions ........................................................... 12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 13

Table 2. Am29DL640H Sector Architecture ....................................14

Table 3. Bank Address ....................................................................17

Table 4. SecSi

™

Sector Addresses ...............................................17

Sector/Sector Block Protection and Unprotection .................. 18

Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................18

Write Protect (WP#) ................................................................ 18

Table 6. WP#/ACC Modes ..............................................................19

Temporary Sector Unprotect .................................................. 19

Figure 1. Temporary Sector Unprotect Operation ...........................19

Figure 2. In-System Sector Protect/Unprotect Algorithms ..............20

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 21

Figure 3. SecSi Sector Protect Verify ..............................................22

Hardware Data Protection ...................................................... 22

Low VCC Write Inhibit ........................................................... 22

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 7. CFI Query Identification String ..........................................23

Table 8. System Interface String .....................................................23

Table 9. Device Geometry Definition ..............................................24

Table 10. Primary Vendor-Specific Extended Query ......................25

Flash Command Definitions . . . . . . . . . . . . . . . . 26

Reading Array Data ................................................................ 26

Reset Command ..................................................................... 26

Autoselect Command Sequence ............................................ 26

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 26

Word Program Command Sequence ..................................... 27

Unlock Bypass Command Sequence .................................. 27

Figure 4. Program Operation ..........................................................28

Chip Erase Command Sequence ........................................... 28

Sector Erase Command Sequence ........................................ 28

Figure 5. Erase Operation ...............................................................29

Erase Suspend/Erase Resume Commands ........................... 29

Table 11. Am29DL640H Command Definitions ..............................30

Flash Write Operation Status . . . . . . . . . . . . . . . 31

DQ7: Data# Polling ................................................................. 31

Figure 6. Data# Polling Algorithm .................................................. 31

RY/BY#: Ready/Busy# ............................................................ 32

DQ6: Toggle Bit I .................................................................... 32

Figure 7. Toggle Bit Algorithm ........................................................ 32

DQ2: Toggle Bit II ................................................................... 33

Reading Toggle Bits DQ6/DQ2 ............................................... 33

DQ5: Exceeded Timing Limits ................................................ 33

DQ3: Sector Erase Timer ....................................................... 33

Table 12. Write Operation Status ................................................... 34

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35

Figure 8. Maximum Negative Overshoot Waveform ...................... 35

Figure 9. Maximum Positive Overshoot Waveform ........................ 35

ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ESD Immunity ......................................................................... 36

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37

CMOS Compatible .................................................................. 37

pSRAM DC & Operating Characteristics . . . . . . 38

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 39

Figure 10. ICC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 39

Figure 11. Typical ICC1 vs. Frequency ............................................ 39

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. Test Setup .................................................................... 40

Figure 13. Input Waveforms and Measurement Levels ................. 40

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41

CE#s Timing ........................................................................... 41

Figure 14. Timing Diagram for Alternating

Between Pseudo SRAM to Flash ................................................... 41

Read-Only Operations ........................................................... 42

Figure 15. Read Operation Timings ............................................... 42

Hardware Reset (RESET#) .................................................... 43

Figure 16. Reset Timings ............................................................... 43

Erase and Program Operations .............................................. 44

Figure 17. Program Operation Timings .......................................... 45

Figure 18. Accelerated Program Timing Diagram .......................... 45

Figure 19. Chip/Sector Erase Operation Timings .......................... 46

Figure 20. Back-to-back Read/Write Cycle Timings ...................... 47

Figure 21. Data# Polling Timings (During Embedded Algorithms) . 47

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 48

Figure 23. DQ2 vs. DQ6 ................................................................. 48

Temporary Sector Unprotect .................................................. 49

Figure 24. Temporary Sector Unprotect Timing Diagram .............. 49

Figure 25. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 50

Alternate CE#f Controlled Erase and Program Operations .... 51

Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings .......................................................................... 52

Read Cycle ............................................................................. 53

Figure 27. Pseudo SRAM Read Cycle ........................................... 53

Figure 28. Page Read Timing ........................................................ 54

Write Cycle ............................................................................. 55

Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 55

Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control .............. 56

Figure 31. Pseudo SRAM Write Cycle—

UB#s and LB#s Control .................................................................. 57

4 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Flash Erase And Programming Performance . . . 58

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58

Package Pin Capacitance . . . . . . . . . . . . . . . . . . .58

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . .58

pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 59

pSRAM Power on and Deep Power Down . . . . . 59

Figure 32. Deep Power-down Timing ..............................................59

Figure 33. Power-on Timing ............................................................59

pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 60

Figure 34. Read Address Skew ..................................................... 60

Figure 35. Write Address Skew ...................................................... 60

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61

FTA088—88-Ball Fine-Pitch Grid Array 11.6 x 8 mm ............. 61

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62

February 6, 2004 Am50DL128CH 5

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

MCP BLOCK DIAGRAM

Part Number Am50DL128CH

Speed

Options

Standard Voltage

Range: VCC =

2.7–3.3 V

Flash Memory Pseudo SRAM

56 70 85 56 70 85

Max Access Time, ns 55 70 85 70 70 85

Page Access Time

(pSRAM), ns N/A N/A N/A 30 30 35

CE#f Access, ns 55 70 85 70 70 85

OE# Access, ns 25 30 40 25 25 30

VSS

VCCs

RESET#2

WE#

OE#

CE1#ps

LB#

UB#

CE#f1

WP#/ACC

CE2ps

64 MBit

Static RAM

64 MBit

Flash Memory

#2 DQ15 to DQ0

DQ15 to DQ0

RY/BY#1

VSS

VCCf

64 MBit

Flash Memory

A21 to A0

CE#f2

DQ15 to DQ0

VSSf

VCCf

RY/BY#2

RESET#1

6 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH MEMORY BLOCK DIAGRAM

VCC

VSS

Bank 1 Address

Bank 2 Address

A21–A0

RESET#

WE#

CE#

BYTE#

DQ15–DQ0

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Bank 1

X-Decoder

OE# BYTE#

DQ15–DQ0

Status

Control

A21–A0

A21–A0A0–A21

DQ15–DQ0

Mux

Bank 2

X-Decoder

Y-gate

Bank 3

X-Decoder

Bank 4

X-Decoder

Y-gate

Bank 3 Address

Bank 4 Address

February 6, 2004 Am50DL128CH 7

ADVANCE INFORMATION

CONNECTION DIAGRAM

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, PLCC, PDIP,

SSOP). The package and/or data integrity may be

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

G3 G4 G5 G6 G7 G8

F3 F4 F5 F6 F7 F8

E3 E4 E5 E6 E7 E8

D3 D4 D5 D6 D7 D8

C3 C4 C5 C6 C7 C8

B3 B4 B5 B6 B7 B8

NC NCNCCE#f2RY/BY#2V

A8 A11WE#WP#/ACCLB#A7NC

A19 A12CE2psRESET#1UB#A6A3

A9 A13A20RY/BY#1A18A5A2

A10 A14NCNCA17A4A1

DQ6 NC

A15

A21

A16NCNCDQ1V

NCNC

M10

A10

NCNCNC

H3 H4 H5 H6 H7 H8

DQ13 DQ15

fDQ4DQ3DQ9OE#CE#f1

J3 J4 J5 J6 J7 J8

DQ12 DQ7

psV

fDQ10DQ0CE#1fps

K3 K4 K5 K6 K7 K8

DQ5 DQ14

NCNCDQ11DQ2DQ8NC

L3 L4 L5 L6 L7 L8

NC NC

NCNCV

RESET#2NC

Shared

Flash 1 only

Flash 2 only

Flash 1 and 2

shared

SRAM only

88-Ball FBGA

Top View

8 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

PIN DESCRIPTION

A21–A0 = 22 Address Inputs (Common)

DQ15–DQ0 = 16 Data Inputs/Outputs (Common)

CE#f1 = Chip Enable 1 (Flash 1)

CE#f2 = Chip Enable 2 (Flash 2)

CE1#ps = Chip Enable 1 (pSRAM)

CE2ps = Chip Enable 2 (pSRAM)

OE# = Output Enable (Common)

WE# = Write Enable (Common)

RY/BY#1 = Ready/Busy Output (Flash 1)

RY/BY#2 = Ready/Busy Output (Flash 2)

UB# = Upper Byte Control (pSRAM)

LB# = Lower Byte Control (pSRAM)

RESET#1 = Hardware Reset Pin, Active Low

(Flash 1)

RESET#2 = Hardware Reset Pin, Active Low

(Flash 2)

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash)

VCCf = Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

VCCps = pSRAM Power Supply

VSS = Device Ground (Common)

NC = Pin Not Connected Internally

LOGIC SYMBOL

DQ15–DQ0

A21–A0

CE#f1

OE#

WE#

RESET#1

UB#

RY/BY#1

WP#/ACC

LB#

CE1#ps

CE2ps

CE#f2

RESET#2

RY/BY#2

February 6, 2004 Am50DL128CH 9

ADVANCE INFORMATION

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD or Fujitsu sales office to

confirm availability of specific valid combinations and to check on

newly released combinations.

Am50DL128 C H 70 I T

TAPE AND REEL

T = 7 inches

S = 13 inches

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C)

SPEED OPTION

See “Product Selector Guide” on page 5

FLASH PROCESS TECHNOLOGY

H = 0.13 µm

PSEUDO SRAM DEVICE DENSITY

C = 64 Mbits

AMD DEVICE NUMBER/DESCRIPTION

Am50DL128CH

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Two Am29DL640H 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash

Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode

88-Ball Fine Pitch Ball Grid Array, 11.6 x 8, 0.80 mm pitch package (FTA088)

Valid Combinations

Order Number Package Marking

Am50DL128CH56I

T,S

M50000004M

Am50DL128CH70I M50000004N

Am50DL128CH85I M50000004P

10 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

MCP DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Tables 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

February 6, 2004 Am50DL128CH 11
ADVANCE INFORMATION 
Table 1. Device Bus Operations—Flash Word Mode 
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5
 
V,  V HH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = 
Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are 
inhibited.
2. Do not apply CE#f1 or 2 = VIL, CE1#s = VIL and CE2s = VIH at the 
same time.
3. Active flash is device being addressed.
4. Don’t care or open LB#s or UB#s.
5. If WP#/ACC = VIL 
, the boot sectors will be protected. If WP#/ACC 
= VIH the boot sectors protection will be removed. 
If WP#/ACC = VACC (9V), the program time will be reduced by 
40%.
6. The sector protect and sector unprotect functions may also be 
implemented via programming equipment. See the “Sector/Sector 
Block Protection and Unprotection” section.
7. If WP#/ACC = VIL, the two outermost boot sectors remain 
protected. If WP#/ACC = VIH, the two outermost boot sector 
protection depends on whether they were last protected or 
unprotected using the method described in “Sector/Sector Block 
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will 
be unprotected.
8. Data will be retained in pSRAM.
9. Data will be lost in pSRAM.
10. CE# inputs on both flash devices may be held low for this operation.
Operation 
(Notes 1, 2)
CE#f
Active
CE#f
Inactive CE1#ps CE2ps OE# WE# Addr. LB#s UB#s RESET#
WP#/
ACC
(Note 5)
DQ7–
DQ0
DQ15–
DQ8
(Note 3)
Read from 
Active Flash
(Note 8) LH HH
LH AIN XX H L/H
DOUT DOUT
(Note 9) H L
Write to Active 
Flash
(Note 8) LH HH
HL AIN XX H(Note 5)
DIN DIN
(Note 9) H L
Standby VCC ± 0.3 V HHXXX XX
VCC ± 
0.3 V H High-Z High-Z
Deep Power-down 
Standby VCC ± 0.3 V HLXXXXX
VCC ± 
0.3 V H High-Z High-Z
Output Disable (Note 10) L H L H HH X X X H L/H High-Z High-Z
HH X X X
Flash Hardware 
Reset
(Note 8) XHH
X X X X X L L/H High-Z High-Z
(Note 9) H L
Sector Protect 
(Notes 6, 10)
(Note 8)
LH
HH
HL
SADD, 
A6 = L, 
A1 = H, 
A0 = L
XX VID L/H DIN X
(Note 9) H L
Sector 
Unprotect 
(Notes 6, 10)
(Note 8)
LH
HH
HL
SADD, 
A6 = H, 
A1 = H, 
A0 = L
XX VID (Note 7) DIN X
(Note 9) H L
Temporary 
Sector 
Unprotect
(Note 8)
X
HH
XX X X X VID (Note 7) DIN High-Z
(Note 9) H L
Read from pSRAM H H L H L H AIN
LL
HX
DOUT DOUT
HL High-Z
DOUT
LH DOUT High-Z
Write to pSRAM H H L H X L AIN
LL
HX
DIN DIN
HL High-Z
DIN
LH DIN High-Z

12 Am50DL128CH February 6, 2004
ADVANCE INFORMATION 
FLASH DEVICE BUS OPERATIONS
Word Configuration
The device is in word configuration, DQ15–DQ0 are
active and controlled by CE#f and OE#.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. 
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the Flash Read-Only Operations table for tim-
ing specifications and to Figure 15 for the timing dia-
gram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the device accepts program data in bytes or
words. Refer to “Flash Device Bus Operations” for
more information. 
The device features an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. 
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a sector. The “Flash Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
The device address space is divided into four banks. A
“bank address” is the address bits required to uniquely
select a bank.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The Flash
AC Characteristics section contains timing specifica-
tion tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory. 
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. 
Note that V
HH
 must not be asserted on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result
.
See “Write Protect (WP#)” on page 18 for related infor-
mation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Sector/Sector Block Protection
and Unprotection and Autoselect Command Se-
quence sections for more information.
Simultaneous Read/Write Operations with 
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 20 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6f and ICC7f in the Zero-Power Flash table
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.

February 6, 2004 Am50DL128CH 13

ADVANCE INFORMATION

(Note that this is a more restricted voltage range than

VIH.) If CE#f and RESET# are held at VIH, but not

within VCC ± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (tCE) for read ac-

cess when the device is in either of these standby

modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

ICC3f in the Zero-Power Flash table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of

the CE#f, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

ICC5f in the Zero-Power Flash table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP

, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4f). If RESET# is

held at VIL but not within VSS±0.3 V, the standby cur-

rent will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 16 for the timing dia-

gram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high

impedance state.

14 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Table 2. Am29DL640H Sector Architecture

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

Bank 1

SA0 0000000000 8/4 00000h–00FFFh

SA1 0000000001 8/4 01000h–01FFFh

SA2 0000000010 8/4 02000h–02FFFh

SA3 0000000011 8/4 03000h–03FFFh

SA4 0000000100 8/4 04000h–04FFFh

SA5 0000000101 8/4 05000h–05FFFh

SA6 0000000110 8/4 06000h–06FFFh

SA7 0000000111 8/4 07000h–07FFFh

SA8 0000001xxx 64/32 08000h–0FFFFh

SA9 0000010xxx 64/32 10000h–17FFFh

SA10 0000011xxx 64/32 18000h–1FFFFh

SA11 0000100xxx 64/32 20000h–27FFFh

SA12 0000101xxx 64/32 28000h–2FFFFh

SA13 0000110xxx 64/32 30000h–37FFFh

SA14 0000111xxx 64/32 38000h–3FFFFh

SA15 0001000xxx 64/32 40000h–47FFFh

SA16 0001001xxx 64/32 48000h–4FFFFh

SA17 0001010xxx 64/32 50000h–57FFFh

SA18 0001011xxx 64/32 58000h–5FFFFh

SA19 0001100xxx 64/32 60000h–67FFFh

SA20 0001101xxx 64/32 68000h–6FFFFh

SA21 0001101xxx 64/32 70000h–77FFFh

SA22 0001111xxx 64/32 78000h–7FFFFh

February 6, 2004 Am50DL128CH 15

ADVANCE INFORMATION

Bank 2

SA23 0010000xxx 64/32 80000h–87FFFh

SA24 0010001xxx 64/32 88000h–8FFFFh

SA25 0010010xxx 64/32 90000h–97FFFh

SA26 0010011xxx 64/32 98000h–9FFFFh

SA27 0010100xxx 64/32 A0000h–A7FFFh

SA28 0010101xxx 64/32 A8000h–AFFFFh

SA29 0010110xxx 64/32 B0000h–B7FFFh

SA30 0010111xxx 64/32 B8000h–BFFFFh

SA31 0011000xxx 64/32 C0000h–C7FFFh

SA32 0011001xxx 64/32 C8000h–CFFFFh

SA33 0011010xxx 64/32 D0000h–D7FFFh

SA34 0011011xxx 64/32 D8000h–DFFFFh

SA35 0011000xxx 64/32 E0000h–E7FFFh

SA36 0011101xxx 64/32 E8000h–EFFFFh

SA37 0011110xxx 64/32 F0000h–F7FFFh

SA38 0011111xxx 64/32 F8000h–FFFFFh

SA39 0100000xxx 64/32 F9000h–107FFFh

SA40 0100001xxx 64/32 108000h–10FFFFh

SA41 0100010xxx 64/32 110000h–117FFFh

SA42 0101011xxx 64/32 118000h–11FFFFh

SA43 0100100xxx 64/32 120000h–127FFFh

SA44 0100101xxx 64/32 128000h–12FFFFh

SA45 0100110xxx 64/32 130000h–137FFFh

SA46 0100111xxx 64/32 138000h–13FFFFh

SA47 0101000xxx 64/32 140000h–147FFFh

SA48 0101001xxx 64/32 148000h–14FFFFh

SA49 0101010xxx 64/32 150000h–157FFFh

SA50 0101011xxx 64/32 158000h–15FFFFh

SA51 0101100xxx 64/32 160000h–167FFFh

SA52 0101101xxx 64/32 168000h–16FFFFh

SA53 0101110xxx 64/32 170000h–177FFFh

SA54 0101111xxx 64/32 178000h–17FFFFh

SA55 0110000xxx 64/32 180000h–187FFFh

SA56 0110001xxx 64/32 188000h–18FFFFh

SA57 0110010xxx 64/32 190000h–197FFFh

SA58 0110011xxx 64/32 198000h–19FFFFh

SA59 0100100xxx 64/32 1A0000h–1A7FFFh

SA60 0110101xxx 64/32 1A8000h–1AFFFFh

SA61 0110110xxx 64/32 1B0000h–1B7FFFh

SA62 0110111xxx 64/32 1B8000h–1BFFFFh

SA63 0111000xxx 64/32 1C0000h–1C7FFFh

SA64 0111001xxx 64/32 1C8000h–1CFFFFh

SA65 0111010xxx 64/32 1D0000h–1D7FFFh

SA66 0111011xxx 64/32 1D8000h–1DFFFFh

SA67 0111100xxx 64/32 1E0000h–1E7FFFh

SA68 0111101xxx 64/32 1E8000h–1EFFFFh

SA69 0111110xxx 64/32 1F0000h–1F7FFFh

SA70 0111111xxx 64/32 1F8000h–1FFFFFh

Table 2. Am29DL640H Sector Architecture (Continued)

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

16 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Bank 3

SA71 1000000xxx 64/32 200000h–207FFFh

SA72 1000001xxx 64/32 208000h–20FFFFh

SA73 1000010xxx 64/32 210000h–217FFFh

SA74 1000011xxx 64/32 218000h–21FFFFh

SA75 1000100xxx 64/32 220000h–227FFFh

SA76 1000101xxx 64/32 228000h–22FFFFh

SA77 1000110xxx 64/32 230000h–237FFFh

SA78 1000111xxx 64/32 238000h–23FFFFh

SA79 1001000xxx 64/32 240000h–247FFFh

SA80 1001001xxx 64/32 248000h–24FFFFh

SA81 1001010xxx 64/32 250000h–257FFFh

SA82 1001011xxx 64/32 258000h–25FFFFh

SA83 1001100xxx 64/32 260000h–267FFFh

SA84 1001101xxx 64/32 268000h–26FFFFh

SA85 1001110xxx 64/32 270000h–277FFFh

SA86 1001111xxx 64/32 278000h–27FFFFh

SA87 1010000xxx 64/32 280000h–28FFFFh

SA88 1010001xxx 64/32 288000h–28FFFFh

SA89 1010010xxx 64/32 290000h–297FFFh

SA90 1010011xxx 64/32 298000h–29FFFFh

SA91 1010100xxx 64/32 2A0000h–2A7FFFh

SA92 1010101xxx 64/32 2A8000h–2AFFFFh

SA93 1010110xxx 64/32 2B0000h–2B7FFFh

SA94 1010111xxx 64/32 2B8000h–2BFFFFh

SA95 1011000xxx 64/32 2C0000h–2C7FFFh

SA96 1011001xxx 64/32 2C8000h–2CFFFFh

SA97 1011010xxx 64/32 2D0000h–2D7FFFh

SA98 1011011xxx 64/32 2D8000h–2DFFFFh

SA99 1011100xxx 64/32 2E0000h–2E7FFFh

SA100 1011101xxx 64/32 2E8000h–2EFFFFh

SA101 1011110xxx 64/32 2F0000h–2FFFFFh

SA102 1011111xxx 64/32 2F8000h–2FFFFFh

SA103 1100000xxx 64/32 300000h–307FFFh

SA104 1100001xxx 64/32 308000h–30FFFFh

SA105 1100010xxx 64/32 310000h–317FFFh

SA106 1100011xxx 64/32 318000h–31FFFFh

SA107 1100100xxx 64/32 320000h–327FFFh

SA108 1100101xxx 64/32 328000h–32FFFFh

SA109 1100110xxx 64/32 330000h–337FFFh

SA110 1100111xxx 64/32 338000h–33FFFFh

SA111 1101000xxx 64/32 340000h–347FFFh

SA112 1101001xxx 64/32 348000h–34FFFFh

SA113 1101010xxx 64/32 350000h–357FFFh

SA114 1101011xxx 64/32 358000h–35FFFFh

SA115 1101100xxx 64/32 360000h–367FFFh

SA116 1101101xxx 64/32 368000h–36FFFFh

SA117 1101110xxx 64/32 370000h–377FFFh

SA118 1101111xxx 64/32 378000h–37FFFFh

Table 2. Am29DL640H Sector Architecture (Continued)

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

February 6, 2004 Am50DL128CH 17

ADVANCE INFORMATION

Note: The address range is A21:A0.

Table 3. Bank Address

Table 4. SecSi™ Sector Addresses

Bank 4

SA119 1110000xxx 64/32 380000h–387FFFh

SA120 1110001xxx 64/32 388000h–38FFFFh

SA121 1110010xxx 64/32 390000h–397FFFh

SA122 1110011xxx 64/32 398000h–39FFFFh

SA123 1110100xxx 64/32 3A0000h–3A7FFFh

SA124 1110101xxx 64/32 3A8000h–3AFFFFh

SA125 1110110xxx 64/32 3B0000h–3B7FFFh

SA126 1110111xxx 64/32 3B8000h–3BFFFFh

SA127 1111000xxx 64/32 3C0000h–3C7FFFh

SA128 1111001xxx 64/32 3C8000h–3CFFFFh

SA129 1111010xxx 64/32 3D0000h–3D7FFFh

SA130 1111011xxx 64/32 3D8000h–3DFFFFh

SA131 1111100xxx 64/32 3E0000h–3E7FFFh

SA132 1111101xxx 64/32 3E8000h–3EFFFFh

SA133 1111110xxx 64/32 3F0000h–3F7FFFh

SA134 1111111000 8/4 3F8000h–3F8FFFh

SA135 1111111001 8/4 3F9000h–3F9FFFh

SA136 1111111010 8/4 3FA000h–3FAFFFh

SA137 1111111011 8/4 3FB000h–3FBFFFh

SA138 1111111100 8/4 3FC000h–3FCFFFh

SA139 1111111101 8/4 3FD000h–3FDFFFh

SA140 1111111110 8/4 3FE000h–3FEFFFh

SA141 1111111111 8/4 3FF000h–3FFFFFh

Bank A21–A19

1 000

2 001, 010, 011

3 100, 101, 110

4 111

Device Sector Size

(x8)

Address Range

(x16)

Address Range

Am29DL640H 256 bytes 000000h–0000FFh 00000h–0007Fh

Table 2. Am29DL640H Sector Architecture (Continued)

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

18 Am50DL128CH February 6, 2004
ADVANCE INFORMATION 
Sector/Sector Block Protection and 
Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
5).
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods. 
Table 5. Am29DL640H Boot Sector/Sector Block 
Addresses for Protection/Unprotection
Sector protection/ unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 25 shows the timing
diagram. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unpro-
tect write cycle. 
Note that the sector unprotect algo-
rithm unprotects all sectors in parallel. All previously
protected sectors must be individually re-protected.
 To
change data in protected sectors efficiently, the tem-
porary sector unprotect function is available. See
“Temporary Sector Unprotect”.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service.
It is possible to determine whether a sector is pro-
tected or unprotected. See the Sector/Sector Block
Protection and Unprotection section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting without using VID. This function is
one of two provided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in sectors
0, 1, 140, and 141, independently of whether those
sectors were protected or unprotected using the
method described in “Sector/Sector Block Protection
and Unprotection”.
Sector A21–A12
Sector/
Sector Block Size
SA0 0000000000 8 Kbytes
SA1 0000000001 8 Kbytes
SA2 0000000010 8 Kbytes
SA3 0000000011 8 Kbytes
SA4 0000000100 8 Kbytes
SA5 0000000101 8 Kbytes
SA6 0000000110 8 Kbytes
SA7 0000000111 8 Kbytes
SA8–SA10
0000001XXX,
0000010XXX,
0000011XXX,
192 (3x64) Kbytes
SA11–SA14 00001XXXXX 256 (4x64) Kbytes
SA15–SA18 00010XXXXX 256 (4x64) Kbytes
SA19–SA22 00011XXXXX 256 (4x64) Kbytes
SA23–SA26 00100XXXXX 256 (4x64) Kbytes
SA27-SA30 00101XXXXX 256 (4x64) Kbytes
SA31-SA34 00110XXXXX 256 (4x64) Kbytes
SA35-SA38 00111XXXXX 256 (4x64) Kbytes
SA39-SA42 01000XXXXX 256 (4x64) Kbytes
SA43-SA46 01001XXXXX 256 (4x64) Kbytes
SA47-SA50 01010XXXXX 256 (4x64) Kbytes
SA51-SA54 01011XXXXX 256 (4x64) Kbytes
SA55–SA58 01100XXXXX 256 (4x64) Kbytes
SA59–SA62 01101XXXXX 256 (4x64) Kbytes
SA63–SA66 01110XXXXX 256 (4x64) Kbytes
SA67–SA70 01111XXXXX 256 (4x64) Kbytes
SA71–SA74 10000XXXXX 256 (4x64) Kbytes
SA75–SA78 10001XXXXX 256 (4x64) Kbytes
SA79–SA82 10010XXXXX 256 (4x64) Kbytes
SA83–SA86 10011XXXXX 256 (4x64) Kbytes
SA87–SA90 10100XXXXX 256 (4x64) Kbytes
SA91–SA94 10101XXXXX 256 (4x64) Kbytes
SA95–SA98 10110XXXXX 256 (4x64) Kbytes
SA99–SA102 10111XXXXX 256 (4x64) Kbytes
SA103–SA106 11000XXXXX 256 (4x64) Kbytes
SA107–SA110 11001XXXXX 256 (4x64) Kbytes
SA111–SA114 11010XXXXX 256 (4x64) Kbytes
SA115–SA118 11011XXXXX 256 (4x64) Kbytes
SA119–SA122 11100XXXXX 256 (4x64) Kbytes
SA123–SA126 11101XXXXX 256 (4x64) Kbytes
SA127–SA130 11110XXXXX 256 (4x64) Kbytes
SA131–SA133
1111100XXX,
1111101XXX,
1111110XXX
192 (3x64) Kbytes
SA134 1111111000 8 Kbytes
SA135 1111111001 8 Kbytes
SA136 1111111010 8 Kbytes
SA137 1111111011 8 Kbytes
SA138 1111111100 8 Kbytes
SA139 1111111101 8 Kbytes
SA140 1111111110 8 Kbytes
SA141 1111111111 8 Kbytes
Sector A21–A12
Sector/
Sector Block Size

February 6, 2004 Am50DL128CH 19
ADVANCE INFORMATION 
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether sectors 0, 1, 140, and 141
were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors de-
pends on whether they were last protected or unpro-
tected using the method described in “Sector/Sector
Block Protection and Unprotection”.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result. 
Table 6. WP#/ACC Modes
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
5).
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 24 shows the timing diagrams, for this feature.
If the WP#/ACC pin is at VIL, sectors 0, 1, 140, and
141 will remain protected during the Temporary sector
Unprotect mode.
Figure 1. Temporary Sector Unprotect Operation
WP# Input 
Voltage
Device 
Mode
VIL
Disables programming and erasing in 
SA0, SA1, SA140, and SA141
VIH
Enables programming and erasing in 
SA0, SA1, SA140, and SA141
VHH
Enables accelerated programming 
(ACC). See “Accelerated Program 
Operation” on page 12.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected (If WP#/ACC = V
IL
, 
sectors 0, 1, 140, and 141 will remain protected).
2. All previously protected sectors are protected once 
again.

20 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Figure 2. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

February 6, 2004 Am50DL128CH 21

ADVANCE INFORMATION

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize the that

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicator Bit permanently set to a “0.” Thus, the SecSi

Sector Indicator Bit prevents customer-lockable de-

vices from being used to replace devices that are fac-

tory locked.

The system accesses the SecSi Sector Secure

through a command sequence (see “Enter SecSi™

Sector/Exit SecSi Sector Command Sequence”). After

the system has written the Enter SecSi Sector com-

mand sequence, it may read the SecSi Sector by

using the addresses normally occupied by the boot

sectors. This mode of operation continues until the

system issues the Exit SecSi Sector command se-

quence, or until power is removed from the device. On

power-up, or following a hardware reset, the device re-

verts to sending commands to the first 256 bytes of

Sector 0.

Note that the ACC function and unlock by-

pass modes are not available when the SecSi Sector

is enabled.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a secure ESN. The 8-word random number will at

addresses 000000h–000007h in word mode. The se-

cure ESN will be programmed in the next 8 words at

addresses 000008h–00000Fh. The device is available

preprogrammed with one of the following:

■A random, secure ESN only

■Customer code through the ExpressFlash service

■Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space.

The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

The SecSi Sector area can be protected using one of

the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that

RESET# may be at either V

or V

. This

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

■To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

22 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 11 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during VCC power-up

and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until VCC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#f

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,

CE#f and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE#f = VIL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 7–10. To terminate reading CFI data,

the system must write the reset command.The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 7–10. The

system must write the reset command to return the

device to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1 µs

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

February 6, 2004 Am50DL128CH 23

ADVANCE INFORMATION

Table 7. CFI Query Identification String

Table 8. System Interface String

Addresses

(Word Mode) Data Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h Primary OEM Command Set

15h

16h

0040h

0000h Address for Primary Extended Table

17h

18h

0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Addresses

(Word Mode) Data Description

1Bh 0027h VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 0036h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 0003h Typical timeout per single byte/word write 2N µs

20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 0009h Typical timeout per individual block erase 2N ms

22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 0005h Max. timeout for byte/word write 2N times typical

24h 0000h Max. timeout for buffer write 2N times typical

25h 0004h Max. timeout per individual block erase 2N times typical

26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

24 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Table 9. Device Geometry Definition

Addresses

(Word Mode) Data Description

27h 0017h Device Size = 2N byte

28h

29h

0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 0003h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

007Dh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

February 6, 2004 Am50DL128CH 25

ADVANCE INFORMATION

Table 10. Primary Vendor-Specific Extended Query

Addresses

(Word Mode) Data Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h 0031h Major version number, ASCII (reflects modifications to the silicon)

44h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h 0004h

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 0004h Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode

4Ah 0077h Simultaneous Operation

00 = Not Supported, X = Number of Sectors (excluding Bank 1)

4Bh 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 0000h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 0085h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 0095h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 0001h

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write

Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and

Bottom

50h 0001h Program Suspend

0 = Not supported, 1 = Supported

57h 0004h Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

58h 0017h Bank 1 Region Information

X = Number of Sectors in Bank 1

59h 0030h Bank 2 Region Information

X = Number of Sectors in Bank 2

5Ah 0030h Bank 3 Region Information

X = Number of Sectors in Bank 3

5Bh 0017h Bank 4 Region Information

X = Number of Sectors in Bank 4

26 Am50DL128CH February 6, 2004
ADVANCE INFORMATION 
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 11 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence may
place the device in an unknown state. A reset com-
mand is then required to return the device to reading
array data. 
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the pSRAM AC Characteristics
section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. The system can read array data using the
standard read timing, except that if it reads at an ad-
dress within erase-suspended sectors, the device out-
puts status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with the same excep-
tion. See the Erase Suspend/Erase Resume Com-
mands section for more information.
The system 
must
 issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
section for more information. The Flash Read-Only
Operations table provides the read parameters, and
Figure 15 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to the read mode. If the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, however,
the device ignores reset commands until the operation
is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Sus-
pend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the autose-
lect mode. The system may read any number of
autoselect codes without reinitiating the command se-
quence.
Table 11 shows the address and data requirements.
To determine sector protection information, the system
must write to the appropriate bank address (BA) and
sector address (SADD). Table 2 shows the address
range and bank number associated with each sector. 
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi

February 6, 2004 Am50DL128CH 27
ADVANCE INFORMATION 
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. The SecSi
Sector is not accessible when the device is executing
an Embedded Program or embedded Erase algorithm.
Table 11 shows the address and data requirements for
both command sequences. See also “SecSi™ (Se-
cured Silicon) Sector Flash Memory Region” for further
information. 
Note that the ACC function and unlock by-
pass modes are not available when the SecSi Sector
is enabled.
Word Program Command Sequence
The system may program the device by word. Pro-
gramming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is 
not
 required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 11 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper-
ation Status section for information on these status
bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. 
Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when a program opera-
tion is in progress. 
The program command sequence
should be reinitiated once that bank has returned to
the read mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 11 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. (See Table 11).
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. 
Note that
the WP#/ACC pin must not be at V
HH
 any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.

28 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 11

shows the address and data requirements for the chip

erase command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Flash Write Operation Status

section for information on these status bits.

Any commands written during the chip erase operation

are ignored.

Note that the SecSi Sector, autoselect,

and CFI functions are unavailable when a program op-

eration is in progress.

However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the chip erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 11 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

The device does

not

require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 80 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to the read mode.

Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

The system

must rewrite the command sequence and any addi-

tional addresses and commands.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 11 for program command sequence.

February 6, 2004 Am50DL128CH 29
ADVANCE INFORMATION 
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer
to the Flash Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Figure 5. Erase Operation
Erase Suspend/Erase Resume 
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm. 
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when
writing the Erase suspend command.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Flash Write Operation Status section for
information on these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Flash Write Operation Status section for
more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored
in the memory array. When the device exits the au-
toselect mode, the device reverts to the Erase Sus-
pend mode, and is ready for another valid operation.
Refer to the Sector/Sector Block Protection and Un-
protection and Autoselect Command Sequence sec-
tions for details. 
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pended bank is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the chip has resumed erasing. 
START
Write Erase 
Command Sequence
(Notes 1, 2)
Data Poll to Erasing 
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
Notes:
1. See Table 11 for erase command sequence.
2. See the section on DQ3 for information on the sector 
erase timer.

30 Am50DL128CH February 6, 2004
ADVANCE INFORMATION 
Table 11. Am29DL640H Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses 
latch on the falling edge of the WE# or CE#f pulse, whichever happens 
later.
PD = Data to be programmed at location PA. Data latches on the rising 
edge of WE# or CE#f pulse, whichever happens first.
SADD = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A21–A12 uniquely select any sector. Refer to 
Table 2 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is 
in bypass mode, or is being erased. Address bits A21–A19 select a 
bank. Refer to Table 3 for information on sector addresses.
Notes:
1. See Tables 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, 
except for RD and PD.
5. Unless otherwise noted, address bits A21–A12 are don’t cares for 
unlock and command cycles, unless SADD or PA is required.
6. No unlock or command cycles required when bank is reading 
array data.
7. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when a bank is in the autoselect mode, or if DQ5 goes high (while 
the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read 
cycle. The system must provide the bank address to obtain the 
manufacturer ID, device ID, or SecSi Sector factory protect 
information. Data bits DQ15–DQ8 are don’t care. See the 
Autoselect Command Sequence section for more information.
9. The device ID must be read across the fourth, fifth, and sixth 
cycles.
10. The data is 80h for factory locked, 40h for customer locked and 
00h for not factory/customer locked.
11. The data is 00h for an unprotected sector/sector block and 01h for 
a protected sector/sector block. 
12. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the 
read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase 
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or when 
device is in autoselect mode. 
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth  Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4 555 AA 2AA 55 (BA)555 90 (BA)X00 01
Device ID (Note 9) Word 6 555 AA 2AA 55 (BA)555 90 (BA)X01 7E (BA)X0E 02 (BA)X0F 01
SecSi Sector Factory 
Protect (Note 10) Word 4 555 AA 2AA 55 (BA)555 90 (BA)X03 80/00
Sector/Sector Block 
Protect Verify 
(Note 11)
Word 4 555 AA 2AA 55 (BA)555 90 (SADD)
X02 00/01
Enter SecSi Sector Region Word 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region Word 4 555 AA 2AA 55 555 90 XXX 00
Program Word 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass Word 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 12) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00
Chip Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SADD 30
Erase Suspend (Note 14) 1 BA B0
Erase Resume (Note 15) 1 BA 30
CFI Query (Note 16) Word 1 55 98

February 6, 2004 Am50DL128CH 31

ADVANCE INFORMATION

FLASH WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 12 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the

fol-

lowing

read cycles. Just prior to the completion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ15–DQ8 (DQ7–DQ0

in byte mode) while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ15–DQ0 may be still

invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for

byte mode) will appear on successive read cycles.

Table 12 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 21

in the pSRAM AC Characteristics section shows the

Data# Polling timing diagram.

Figure 6. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

32 Am50DL128CH February 6, 2004
ADVANCE INFORMATION 
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 12 shows the outputs for RY/BY#. 
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 12 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 22 in
the “Flash AC Characteristics” section shows the tog-
gle bit timing diagrams. Figure 23 shows the differ-
ences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
Figure 7. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
 = Toggle?
No
Program/Erase
Operation Not 
Complete, Write 
Reset Command
Program/Erase
Operation Complete
Toggle Bit
 = Toggle?
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA 
Read Byte
(DQ7–DQ0)
Address =VA 
Note: The system should recheck the toggle bit even if DQ5 
= “1” because the toggle bit may stop toggling as DQ5 
changes to “1.” See the subsections on DQ6 and DQ2 for 
more information.

February 6, 2004 Am50DL128CH 33
ADVANCE INFORMATION 
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 12 to compare out-
puts for DQ2 and DQ6. 
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 22 shows the toggle bit timing diagram. Figure
23 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ15–DQ0 (or DQ7–DQ0 for byte
mode) at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note
and store the value of the toggle bit after the first read.
After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle bit
is not toggling, the device has completed the program
or erase operation. The system can read array data on
DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data. 
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 12 shows the status of DQ3 relative to the other
status bits.

34 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

Table 12. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Standard

Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

February 6, 2004 Am50DL128CH 35

ADVANCE INFORMATION

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . –40°C to +85°C

Voltage with Respect to Ground

VCCf, VCCs (Note 1) . . . . . . . . . . . .–0.5 V to +4.0 V

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V

All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V

to –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V

+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V

+2.0 V for periods up to 20 ns. See

Figure 9.

2. Minimum DC input voltage on pins RESET#, and

WP#/ACC is –0.5 V. During voltage transitions,

WP#/ACC, and RESET# may overshoot V

to –2.0 V for

periods of up to 20 ns. See Figure 8. Maximum DC input

voltage on pin RESET# is +12.5 V which may overshoot

to +14.0 V for periods up to 20 ns. Maximum DC input

voltage on WP#/ACC is +9.5 V which may overshoot to

+12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 8. Maximum Negative

Overshoot Waveform

Figure 9. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

VCCf/VCCs Supply Voltages

VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

ESD IMMUNITY

Spansion Flash memory Multi-Chip Products (MCPs)

may contain component devices that are developed by

FASL LLC (“Spansion components”) and component

devices that are developed by a third party (‘third-party

components”).

Spansion components are tested and guaranteed to

the ESD immunity levels listed in the corresponding

Spansion Flash memory Qualification Database.

Third-party components are neither tested nor guaran-

teed by FASL LLC for ESD immunity. However, ESD

test results for third-party components may be avail-

able from the component manufacturer. Component

manufacturer contact information is listed in the Span-

sion MCP Qualification Report, when available.

The Spansion Flash memory Qualification Database

and Spansion MCP Qualification Report are available

from AMD and Fujitsu sales offices.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

36 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

ESD Immunity

Spansion Flash memory Multi-Chip Products (MCPs)

may contain component devices that are developed by

FASL LLC ("Spansion components") and component

devices that are developed by a third party

("third-party components")

Spansion components are tested and guaranteed to

the ESD immunity levels listed in the corresponding

Spansion Flash memory Qualification Database.

Third-party components are neither tested nor guaran-

teed by FASL LLC for ESD immunity. However, ESD

test results for third-party components may be avail-

able from the component manufacturer. Component

manufacturer contact information is listed in the Span-

sion MCP Qualification Report, when available.

The Spansion Flash memory Qualification Database

and Spansion MCP Qualification Report are available

from AMD and Fujitsu sales offices.

February 6, 2004 Am50DL128CH 37

ADVANCE INFORMATION

FLASH DC CHARACTERISTICS

CMOS Compatible

Notes:

1. The I

CC current listed is typically less than 2 mA/MHz, with OE# at

VIH.

2. Maximum ICC specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in

progress.

4. Automatic sleep mode enables the low power mode when

addresses remain stable for tACC + 30 ns. Typical sleep mode

current is 200 nA.

5. Not 100% tested.

6. CE#f refers to chip enable input of active flash (device being

addressed).

7. Typical and maximum current specifications shown are for each

flash device.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC,

VCC = VCC max

±1.0 µA

ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V 35 µA

ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC,

VCC = VCC max

±1.0 µA

ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC

= VACC max

35 µA

ICC1fFlash VCC Active Read Current

(Notes 1, 2)

CE#f = VIL, OE# = VIH,

Byte Mode

5 MHz 10 16

1 MHz 2 4

CE#f = VIL, OE# = VIH,

Word Mode

5 MHz 10 16

1 MHz 2 4

ICC2fFlash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA

ICC3fFlash VCC Standby Current (Notes 2, 7) VCCf = VCC max, CE#f, RESET#,

WP#/ACC = VCCf ± 0.3 V 0.2 5 µA

ICC4fFlash VCC Reset Current (Notes 2, 7) VCCf = VCC max, RESET# = VSS ± 0.3 V,

WP#/ACC = VCCf ± 0.3 V 0.2 5 µA

ICC5fFlash VCC Current Automatic Sleep Mode

(Notes 2, 4, 7)

VCCf = VCC max, VIH = VCC ± 0.3 V;

VIL = VSS ± 0.3 V 0.2 5 µA

ICC6fFlash VCC Active Read-While-Program

Current (Notes 1, 2) CE#f = VIL, OE# = VIH

Byte 21 45 mA

Word 21 45

ICC7fFlash VCC Active Read-While-Erase

Current (Notes 1, 2) CE#f = VIL, OE# = VIH

Byte 21 45 mA

Word 21 45

ICC8f

Flash VCC Active

Program-While-Erase-Suspended Current

(Notes 2, 5)

CE#f = VIL, OE#f = VIH 17 35 mA

VIL Input Low Voltage –0.2 0.8 V

VIH Input High Voltage 2.4 VCC + 0.2 V

VHH

Voltage for WP#/ACC Program

Acceleration and Sector

Protection/Unprotection

8.5 9.5 V

VID

Voltage for Sector Protection, Autoselect

and Temporary Sector Unprotect 11.5 12.5 V

VOL Output Low Voltage IOL = 2.0 mA, VCCf = VCCs = VCC min 0.45 V

VOH1 Output High Voltage

IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x

VCC V

VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4

VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.0 2.5 V

38 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

pSRAM DC & OPERATING CHARACTERISTICS

Notes:

1. V

– 1.0 V for a 10 ns pulse width.

2. V

+ 1.0 V for a 10 ns pulse width.

Parameter

Symbol Parameter Description Test Conditions Min. Typ Max Unit

ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA

ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or

WE# = VIL, VIO= VSS to VCC

–1.0 1.0 µA

ICC1s Operating Current

Cycle time = Min., IIO = 0 mA, 100% duty,

CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH,

tRC = Min.

40 mA

ICC2sPage Access Operating

Current

Cycle time = Min., IIO = 0 mA, 100% duty,

CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH,

tPC = Min.

25 mA

VOL Output Low Voltage IOL = 1.0 mA 0.4 V

VOH Output High Voltage IOH = –0.5 mA 2 V

ISB Standby Current (CMOS) CE#1 = VCCS – 0.2 V, CE2 = VCCS – 0.2 V 70 µA

IDSB Deep Power-down Standby CE2 = 0.2 V 5 µA

VIL Input Low Voltage –0.3

(Note 1) 0.4 V

VIH Input High Voltage 2.4

VCC +

0.3

(Note 2)

February 6, 2004 Am50DL128CH 39

ADVANCE INFORMATION

FLASH DC CHARACTERISTICS

Zero-Power Flash

Note: Addresses are switching at 1 MHz

Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

0 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

Figure 11. Typical ICC1 vs. Frequency

2.7 V

3.3 V

40 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

TEST CONDITIONS

Table 13. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Te s t

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

Test Condition 56, 70, 85 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V 1.5 V OutputMeasurement LevelInput

Figure 13. Input Waveforms and Measurement Levels

February 6, 2004 Am50DL128CH 41

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

CE#s Timing

Figure 14. Timing Diagram for Alternating

Between Pseudo SRAM to Flash

Parameter

Description

Test Setup All Speeds Unit

JEDEC Std

—t

CCR CE#s Recover Time — Min 0 ns

CE#f

tCCR tCCR

CE1#s

CE2s

tCCR tCCR

42 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 13 for test specifications

3. Measurements performed by placing a 50

Ω

termination on the data pin with a bias of V

/2. The time from OE# high to the

data bus driven to V

/2 is taken as t

Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation.

Figure 15. Read Operation Timings

Parameter

Description Test Setup

Speed

JEDEC Std. 56 70 85 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 85 ns

tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max557085ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max557085ns

tGLQV tOE Output Enable to Output Delay Max 55 30 40 ns

tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 25 30 35 ns

tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns

tAXQX tOH

Output Hold Time From Addresses, CE#f or

OE#, Whichever Occurs First Min 16 ns

tOEH

Output Enable Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 5 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#f

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

February 6, 2004 Am50DL128CH 43

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Note: CE#f refers to the flash device being reset (either CE#f1 or CE#f2).

Figure 16. Reset Timings

Parameter

Description All Speed Options UnitJEDEC Std

tReady

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#1,

RESET#2

RY/BY#1,

RY/BY#2

RY/BY#1,

RY/BY#2

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#f, OE#

tRH

CE#f, OE#

Reset Timings during Embedded Algorithms

RESET#1,

RESET#2 tRP

tRB

44 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

3. CE#f refers to chip enable input of active flash (device being addressed).

Parameter Speed

JEDEC Std Description 56 70 85 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 85 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO

Address Setup Time to OE# low during toggle bit

polling Min 15 ns

tWLAX tAH Address Hold Time Min 30 40 45 ns

tAHT

Address Hold Time From CE#f or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 30 40 45 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 ns

tGHWL tGHWL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns

tELWL tCS CE#f Setup Time Min 0 ns

tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns

tWHEH tCH CE#f Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 25 30 35 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 7 µs

tWHWH1 tWHWH1

Accelerated Programming Operation,

Word or Byte (Note 2) Ty p 4 µ s

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Write Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

February 6, 2004 Am50DL128CH 45

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

OE#

WE#

CE#f

VCCf

Data

Addresses

tDS

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

GHWL

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

otes:

. PA = program address, PD = program data, D

OUT

is the true data at the program address.

. Illustration shows device in word mode.

. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device

must be held high during this operation.

Figure 17. Program Operation Timings

WP#/ACC

tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 18. Accelerated Program Timing Diagram

46 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

OE#

CE#f

Addresses

VCCf

WE#

Data

2AAh SADD

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.

. These waveforms are for the word mode.

. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must

be held high during this operation.

Figure 19. Chip/Sector Erase Operation Timings

February 6, 2004 Am50DL128CH 47

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

OE#

WE#

Addresses

tOH

Data Valid

Valid

Valid PA Valid RA

tWC

tWPH

tAH

tWP

tDS

tDH

tRC

tCE

Valid

Out

tOE

tACC

tOEH tGHWL

tDF

Valid

CE#f Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

tCP

tCPH

tWC tWC

Read Cycle

tSR/W

CE#f

Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation.

Figure 20. Back-to-back Read/Write Cycle Timings

WE#

CE#f

OE#

High Z

tOE

High Z

DQ7

DQ6–DQ0

RY/BY#

tBUSY

Complement Tr u e

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data Tr u e

Valid Data

tACC

tRC

Notes:

1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read

cycle.

2. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device

must be held high during this operation.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

48 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

OE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status

Valid

Status

Valid

Status

RY/BY#

CE#f

Note:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

2. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device

must be held high during this operation.

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to

toggle DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

February 6, 2004 Am50DL128CH 49

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

tRRB

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect Min 4 µs

RESET#

VIDR

, V

or V

, V

or V

CE#f

WE#

RY/BY#

VIDR

RSP

Program or Erase Command Sequence

RRB

Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation.

Figure 24. Temporary Sector Unprotect Timing Diagram

50 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

RESET#

SADD,

A6, A1, A0

Data

CE#f

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector/Sector Block Protect or Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.

Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation.

Figure 25. Sector/Sector Block Protect and

Unprotect Timing Diagram

February 6, 2004 Am50DL128CH 51

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

Alternate CE#f Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2).

Parameter Speed

JEDEC Std Description 56 70 85 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 85 ns

tAVWL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 30 40 45 ns

tDVEH tDS Data Setup Time Min 30 40 45 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE#f Pulse Width Min 25 40 45 ns

tEHEL tCPH CE#f Pulse Width High Min 25 30 ns

tWHWH1 tWHWH1

Programming Operation

(Note 2) Word Typ 7 µs

tWHWH1 tWHWH1

Accelerated Programming Operation,

Word or Byte (Note 2) Ty p 4 µ s

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

52 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#f

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PA for program

SADD for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SADD = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

OUT

is the data written to the device.

4. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must

be held high during this operation.

5. Waveforms are for the word mode.

Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

February 6, 2004 Am50DL128CH 53

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Read Cycle

Notes:

1. t

OD,

ODo

, t

, and t

ODW

are defined as the time at which

the outputs achieve the open circuit condition and are not

referenced to output voltage levels.

2. If CE#, LB#, or UB# goes low at the same time or before

WE# goes high, the outputs will remain at high impedance.

3. If CE#, LB#, or UB# goes low at the same time or after WE#

goes low, the outputs will remain at high impedance.

Figure 27. Pseudo SRAM Read Cycle

Parameter

Symbol Description Speed Unit

56, 70 85

tRC Read Cycle Time Min 70 85 ns

tACC Address Access Time Max 70 85 ns

tCO Chip Enable Access Time Max 70 85 ns

tOE Output Enable Access Time Max 25 ns

tBA Data Byte Control Access Time Max 25 ns

tCOE Chip Enable Low to Output Active Min 10 ns

tOEE Output Enable Low to Output Active Min 0 ns

tBE Data Byte Control Low to Output Active Min 0 ns

tOD Chip Enable High to Output High-Z Max 20 ns

tODO Output Enable High to Output High-Z Max 20 ns

tBD Data Byte Control High to Output High-Z Max 20 ns

tOH Output Data Hold from Address Change Min 10 ns

tPM Page Mode Time Min 70 ns

tPC Page Mode Cycle Time Min 30 ns

tAA Page Mode Address Access Time Max 30 ns

tAOH Page Output Data Hold Time Min 10 ns

tRC

tACC

Addresses

A20 to A0

CE#1

CE2

OE#

WE#

LB#, UB#

OUT

DQ15 to DQ0

tCO

tOH

Fixed High

High-Z

tOE

tBA

tOD

tODO

tBD

Valid Data Out

Indeterminate

tBE

tOEE

tCOE

54 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Notes:

1. t

OD,

ODo

, t

, and t

ODW

are defined as the time at which the outputs achieve the open circuit condition and are not referenced

to output voltage levels.

2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance.

3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.

Figure 28. Page Read Timing

Addresses

A2 to A0

Addresses

A20 to A3

CE#1

CE2

OE#

WE#

LB#, UB#

OUT

DQ15 to DQ0

COE

ACC

OEE

OUT

ODO

AOH

Fixed High

Maximum 8 words

February 6, 2004 Am50DL128CH 55

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Write Cycle

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.

4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.

Figure 29. Pseudo SRAM Write Cycle—WE# Control

Parameter

Symbol Description Speed Unit

56, 70 85

tWC Write Cycle Time Min 70 85 ns

tWP Write Pulse Time Min 50 60 ns

tCW Chip Enable to End of Write Min 60 70 ns

tBW Data Byte Control to End of Write Min 60 70 ns

tAW Address Valid to End of Write Min 60 70 ns

tAS Address Setup Time Min 0 ns

tWR Write Recovery Time Min 0 ns

tODW WE# Low to Write to Output High-Z Max 20 ns

tOEW WE# High to Write to Output Active Min 0 ns

tDS Data Set-up Time Min 30

tDH Data Hold from Write Time Min 0 ns

tCH CE2 Hold Time Min 300 µs

Valid Data In

OEW

Addresses

A20 to A0

WE#

CE#1

CE2

LB#, UB#

DIN

DQ15 to DQ0

DOUT

DQ15 to DQO

ODW

High-Z

(Note 1)

(Note 3) (Note 4)

56 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control

Valid Data In

Addresses

A20 to A0

CE#1

CE2

WE#

LB#, UB#

DQ15 to DQ0

OUT

DQ15 to DQ0

ODW

COE

High-ZHigh-Z

(Note 1) (Note 1)

February 6, 2004 Am50DL128CH 57

ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Notes:

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.

2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 31. Pseudo SRAM Write Cycle—

UB#s and LB#s Control

Valid Data In

Addresses

A20 to A0

WE#

CE#1

CE2

UB#, LB#

DQ15 to DQ0

OUT

DQ15 to DQ0

High-Z High-Z

COE

ODW

58 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

FLASH ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90

C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

11 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except V

. Test conditions: V

= 3.0 V, one pin at a time.

PACKAGE PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

FLASH DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.4 5 sec Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 56 sec

Byte Program Time 5 150 µs

Excludes system level

overhead (Note 5)

Accelerated Byte/Word Program Time 4 120 µs

Word Program Time 7 210 µs

Chip Program Time

(Note 3) Word Mode 28 84 sec

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 11 14 pF

COUT Output Capacitance VOUT = 0 12 16 pF

CIN2 Control Pin Capacitance VIN = 0 14 16 pF

CIN3 WP#/ACC Pin Capacitance VIN = 0 17 20 pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years

125°C20Years

February 6, 2004 Am50DL128CH 59

ADVANCE INFORMATION

pSRAM DATA RETENTION

Notes:

1. CE1#s

≥

– 0.2 V, CE2s

≥

– 0.2 V (CE1#s controlled) or CE2s

≤

0.2 V (CE2s controlled).

2. Typical values are not 100% tested.

pSRAM POWER ON AND DEEP POWER DOWN

Figure 32. Deep Power-down Timing

Figure 33. Power-on Timing

Parameter

Symbol Parameter Description Test Setup Min Typ Max Unit

VDR VCC for Data Retention CS1#s ≥ VCC – 0.2 V (Note 1) 2.7 3.3 V

IDR Data Retention Current VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V

(Note 1)

1.0

(Note 2) 100 µA

tCS CE2 Setup Time 0 ns

tCH CE2 Hold Time 300 µs

tDPD CE2 Pulse Width 10 ms

tCHC CE2 Hold from CE#1 0 ns

tCHP CE2 Hold from Power On 30 µs

CE#1

CE#2

tDPD

tCH

tCS

CE#1

VDD

CE#2

tCHC

tCHP tCH

VDD min

60 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

pSRAM ADDRESS SKEW

Figure 34. Read Address Skew

Note: If multiple invalid address cycles shorter than t

min occur for a period greater than 10 µs, at least one valid address

cycle over t

RC min

is required during that period.

Figure 35. Write Address Skew

Note: If multiple invalid address cycles shorter than t

min occur for a period greater than 10 µs, at least one valid address

cycle over t

WC min

, in addition to t

WP min

, is required during that period.

CE#1

WE#

Address

tRC min

over 10 µs

CE#1

WE#

Address

tWP min

tWC min

over 10 µs

February 6, 2004 Am50DL128CH 61

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

FTA088—88-Ball Fine-Pitch Grid Array 11.6 x 8 mm

3237 \ 16-038.14b

PACKAGE FTA 088

JEDEC N/A

11.60 mm x 8.00 mm

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.40 PROFILE

A1 0.25 --- --- BALL HEIGHT

A2 1.00 --- 1.11 BODY THICKNESS

D 11.60 BSC. BODY SIZE

E 8.00 BSC. BODY SIZE

D1 8.80 BSC. MATRIX FOOTPRINT

E1 7.20 BSC. MATRIX FOOTPRINT

MD 12 MATRIX SIZE D DIRECTION

ME 10 MATRIX SIZE E DIRECTION

n 88 BALL COUNT

φb 0.30 0.35 0.40 BALL DIAMETER

eE 0.80 BSC. BALL PITCH

eD 0.80 BSC BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

A3,A4,A5,A6,A7,A8,B1,B10,C1,C10,D1,D10

DEPOPULATED SOLDER BALLS

E1,E10,F1,F10,G1,G10,H1,H10

J1,J10,K1,K10,L1,L10,M3,M4,M5,M6,M7,M8

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

INDEX MARK

88X

CORNER

0.15

(2X)

0.15

AD1

ABDCEFHG

BOTTOM VIEW

0.20 C

0.15

0.08

PIN A1

TOP VIEW

SIDE VIEW

CORNER

0.08

62 Am50DL128CH February 6, 2004

ADVANCE INFORMATION

REVISION SUMMARY

Revision A (October 6, 2003)

Initial release.

Revision A+1 (November 7, 2003)

Write Cycle Table

Removed tCEH and tWEH from table.

Revision A+2 (November 25, 2003)

Flash DC Characteristics - CMOS Compatible

Changed IOL test conditions for VOL from 4.0 mA to 2.0

mA.

Revision A+3 (February 6, 2004)

ESD Immunity

Added section.

February 6, 2004 Am50DL128CH 63

ADVANCE INFORMATION

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

64 Am50DL128CH February 6, 2004

ADVANCE INFORMATION