PIC18(L)F24/25/45K50 PIC18(L)F24/25/45K50 Family Silicon Errata and Data Sheet Clarification The PIC18(L)F24/25/45K50 family devices that you have received conform functionally to the current Device Data Sheet (DS30684A), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC18(L)F24/25/45K50 silicon. 4. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A2). Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: 5. Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18(L)F24/25/ 45K50 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Device ID(1) (11-bit) Revision ID for Silicon Revision(2) (5-bit) A1 A2 PIC18F24K50 5C6h 0 0001 0 0010 PIC18LF24K50 5CEh 0 0001 0 0010 PIC18F25K50 5C2h 0 0001 0 0010 PIC18LF25K50 5CAh 0 0001 0 0010 PIC18F45K50 5C0h 0 0001 0 0010 PIC18LF45K50 5C8h 0 0001 0 0010 Note 1: 2: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format "DEVID:DEVREV". Refer to the "PIC18(L)F2X/4XK50 Flash Memory Programming Specification" (DS41630) for detailed information on Device and Revision IDs for your specific device. 2012-2014 Microchip Technology Inc. DS80000547C-page 1 PIC18(L)F24/25/45K50 TABLE 2: SILICON ISSUE SUMMARY Module Oscillator Feature Item Number Issue Summary Affected Revisions(1) A1 A2 Fail-Safe Clock Monitor 1. HS oscillator remains biased if the crystal fails and the clock has switched to Fail-Safe Clock, causing high Sleep currents. X X Timer1/3 Asynchronous Counter Module with Mode Gate Control 2. When using the Timer1 or Timer3 module as an Asynchronous Counter either separately or simultaneously, a false overflow interrupt can occur after reloading the TMRxL and TMRxH registers. X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80000547C-page 2 2012-2014 Microchip Technology Inc. PIC18(L)F24/25/45K50 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 1. Module: Oscillator Higher Sleep currents will be observed if the HS oscillator fails and the PIC(R) MCU switches to the Fail-Safe Clock. Issue occurs if: - The device is running off of the HS clock - The device experiences a failure on the HS clock and the Fail-Safe Clock activates - The device then goes to Sleep without the HS clock returning - The Sleep current observed will differ from base IPD by an amount equal to the HS bias current. Work around None. Affected Silicon Revisions A1 A2 X X 2012-2014 Microchip Technology Inc. DS80000547C-page 3 PIC18(L)F24/25/45K50 2. Module: Timer1/3 Module with Gate Control the interrupt service handler will again branch to the interrupt vector on the next instruction clock, after leaving the ISR. If interrupts are not enabled, the TMRx Overflow Interrupt Flag bit will be set, however, the firmware will not branch to the interrupt vector. When using the Timer1 or Timer3 module, either separately or simultaneously, a false overflow event may occur after reloading the timer. The event only occurs when the timer is configured for Asynchronous Counter mode operation, and is only problematic if the timer's interrupt is enabled. Work around While inside the Interrupt Service Routine (ISR), create a loop routine that tests the timer for a minimum increment of one count. Once the timer has incremented by a minimum of one count, test the Overflow Interrupt Flag bit (TMRxIF) and clear it if set before leaving the ISR. During the Interrupt Service Routine (ISR), after reloading the timer register (TMR1 and/or TMR3) with a new value, the false overflow event can occur upon the very next increment of the timer. This sets the TMRx Overflow Interrupt Flag bit (TMRxIF) and if the timer's interrupts are enabled, EXAMPLE 1: TMR1/3 FALSE INTERRUPT WORK AROUND Load TMRx movlw 0xAA ;W = 0xAA movlwf TMR3H ;Load TMRxH with W movlw 0x55 ;W = 0x55 movwf TMR3L ;Load TMRxL with W movf TMRxL, W ;Move TMRxL to W cpfsgt TMRxL, 0 ;Compare f with W, skip if f>W goto CheckTMR ;Goto CheckTMR if TMRx has not incremented yet btfsc PIRx, TMRxIF ;Test for false TMRxIF bcf PIRx, TMRxIF ;Clear TMRx Overflow Interrupt Flag bit btfss INTCON, ;Test if disabled bsf INTCON, CheckTMR GIE GIE all interrupts including ;Enable all interrupts disabled retfie including peripherals peripherals were if Affected Silicon Revisions A1 A2 X X DS80000547C-page 4 2012-2014 Microchip Technology Inc. PIC18(L)F24/25/45K50 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS30684A): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: CPU Divider Figure 3-1 from Section 3.1 "Overview", as well as Table 3-6 and Table 3-7 from Section 3.14.1 "Low-Speed Operation" have incorrect data on the CPUDIV Configuration bits. The corrected versions are below: 2012-2014 Microchip Technology Inc. DS80000547C-page 5 PIC18(L)F24/25/45K50 FIGURE 3-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO Secondary Oscillator (SOSC) SOSCI Low-Power Mode Event Switch (SCS<1:0>) SOSCOUT 2 Primary Clock Module Secondary Oscillator PCLKEN PRISD EN FOSC<3:0>(4) OSC1 Primary Oscillator INTOSC 3x or 4xPLL 0 0 1 1 IDLE CPU 6 PLL Postscaler Primary Oscillator(2) ( OSC) 01 3 2 1 11 Primary Clock 10 00 01 00 Clock Switch MUX OSC2 CPUDIV PLL_Select(3) Peripherals RA6 4 CLKO Enabled Modes INTOSC 1x Internal Oscillator IRCF<2:0> INTSRC FSEN 3 3 1 HFINTOSC INTOSC Divide Circuit INTRC 8 Internal Oscillator MUX(3) (16 MHz) HF-16 MHZ HF-8 MHZ HF-4 MHZ HF-2 MHZ HF-1 MHZ HF-500 kHZ HF-250 kHZ HF-31.25 kHZ 1 0 4 INTOSC USB Module Clock Needs 48 MHz for FS Needs 6 MHz for LS 0 LS48MHZ LF-31.25 kHz (31.25 kHz) Note 1: Details in Figure 3-3. 2: Details in Figure 3-2. 3: Details in Table 3-1. 4: The Primary Oscillator MUX uses the INTOSC branch when FOSC<3:0> = 100x. DS80000547C-page 6 2012-2014 Microchip Technology Inc. PIC18(L)F24/25/45K50 TABLE 3-6: CLOCK FOR LOW-SPEED USB System Clock CPUDIV<1:0> Microcontroller Clock LS48MHZ USB Clock 48 11 48/6 = 8 MHz 1 48/8 = 6 MHz 48 10 48/3 = 16 MHz 1 48/8 = 6 MHz 48 01 48/2 = 24 MHz 1 48/8 = 6 MHz 48 00 48 MHz 1 48/8 = 6 MHz 24 11 24/6 = 4 MHz 0 24/4 = 6 MHz 24 10 24/3 = 8 MHz 0 24/4 = 6 MHz 24 01 24/2 = 12 MHz 0 24/4 = 6 MHz 24 00 24 MHz 0 24/4 = 6 MHz TABLE 3-7: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator Frequency Clock Mode (FOSC<3:0>) EC 48 MHz 16 MHz 12 MHz EC, HS or INTOSC with 3xPLL EC or HS with 4xPLL 24 MHz Note 1: EC or HS(1) MCU Clock Division (CPUDIV<1:0>) Microcontroller Clock Frequency 6 (11) 6 MHz 3 (10) 12 MHz 2 (01) 24 MHz None (00) 48 MHz (11) 6 MHz 3 (10) 12 MHz 2 (01) 24 MHz None (00) 48 MHz (11) 6 MHz 3 (10) 12 MHz 2 (01) 24 MHz None (00) 48 MHz (11) 4 MHz 3 (10) 8 MHz 2 (01) 12 MHz None (00) 24 MHz The 24 MHz mode (without PLL) is only compatible with low-speed USB. Full-speed USB requires a 48 MHz system clock. 2012-2014 Microchip Technology Inc. DS80000547C-page 7 PIC18(L)F24/25/45K50 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (08/2012) Initial release of this document. Rev B Document (11/2013) Added Silicon Revision A2; Other minor corrections; Data Sheet Clarifications: Added Module 1 (CPU Divider). Rev C Document (01/2014) Added Module 2 (Timer1/3 Module with Gate Control); Other minor corrections. DS80000547C-page 8 2012-2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620778296 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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