DM9374N - Fairchild Semiconductor

March 1989

Revised March 2000

DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

DM9374

7-Segment Decoder/Driver/Latch

with Constant Current Sink Outputs

General Descript ion

The DM74 is a 7-segment decoder driver incorporating

input latches and output circuits to directly drive common

anode LED displays.

Ordering Code:

Connection Diagram Logic Symbol

VCC = Pin 16

GND = Pin 8

Pin Descriptions

Order Number Package Number Package Description

DM9374N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Description

Names

A0–A3 Address (Data Inputs)

LE Latch Enable Input (Active LOW )

RBI Ripple Blanking Input (Active LOW)

RBO Ripple Blanking as Output (Active LOW)

as Input (Active LOW)

a –g Constant Current Outputs (Active LOW)

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DM9374

Truth Table

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Immaterial

Note 1: The RBI will blank th e dis play only if a binary zero is stored in the latches.

Note 2: RBO used as an input overrides all other input conditions.

Numerical Desi gn ati on s

Binary Inputs Outputs Display

State LE RBI A3 A2 A1 A0 a b c d e f g RBO

— H (Note 1) X X X X STABLE H Stable

0 L L L L L L HHHHHHH L Blank

0 L H L L L L LLLLLLH H 0

1 L X LLLHHLLHHHH H 1

2L X LLHLLLHLLHL H 2

3 L X L L H HLLLLHHL H 3

4 L X L H L L HLLHHLL H 4

5L X LHLHLHLLHLL H 5

6 L X L H H L LHLLLLL H 6

7 L X LHHHLLLHHHH H 7

8 L X H L L L LLLLLLL H 8

9 L X H L L H LLLLHLL H 9

10 L X H L H L HHHHHHL H —

11 L X H L H H LHHLLLL H E

12 L X H H L L HLLHLLL H H

13 L X H H L H HHHLLLH H L

14 L X H H H L LLHHLLL H P

15 L X H H H H HHHHHHH H BLANK

X X X X X X X HHHHHH HL (Note 2) BLANK

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DM9374

Functional Description

The DM9374 is a 7-segment decoder/driver with latches on

the address inputs and active LOW constant current out-

puts to drive LEDs directly. This device accepts a 4-bit

binary code and produces output drive to the appropriate

segments of the 7-segment display. It has a decode format

which produces numeric codes “0” through “9” and other

codes.

Latches on the four data in puts a re cont rolle d by a n active

LOW Latch Enable, LE. When LE is LOW, the state of t he

outputs is determined by the input data. When LE goes

HIGH, the last data present at the inputs is stored in the

latches and the ou tputs remain sta ble. The LE pulse width

necessary to accept and store data is typically 50 ns, which

allows data to be stro bed into the DM9374 at normal TTL

speeds. This feature means that data can be routed

directly from high speed counters and frequency dividers

into the display without slowing down the system clock or

providing intermediate data storage.

The latch/decoder combination is a simple system which

drives LED displays with multiplexed data inputs from MOS

time clocks, DVMs, calculator chips, etc. Data inputs are

multiplexed while the displays are in st atic mod e. This low-

ers component and insertion costs, since several circuits—

seven resi stors per display, strobe d rivers, a separate dis-

play voltage source, and clock failure detect circuits—tradi-

tionally found in multiplexed display systems are

eliminated. It also allows low strobing rates to be used with-

out display flicker.

Another DM9374 feature is the reduced loading on the

data inputs when the Latch Enable is HIGH (only 10 µA

typ). This al lows many DM 9374s to be drive n from a MOS

device in multiplex mode without the need for drivers on

the data lines. The DM9374 also provides automatic blank-

ing of t he leading a nd /or tra ilin g- edg e zeroes i n a mu lt idig i t

decimal number, resulting in an easily readable decimal

display co nforming to no rmal writing p ractice. In an 8 -digit

mixed integer fraction decimal representation, using the

automatic blanking capability 0060.0300 would be dis-

played as 60.03. Leading-edge zero suppression is

obtain ed by connecting the Ripple Blan king Output (RBO)

of a decode r to the Ripp le Bla nking Input (RBI) of th e next

lower stage device. The most significant decoder stage

should have the RIB input grounded; and since suppres-

sion of t he least signif icant integ er zero in a n umber is no t

usually de sired, th e RBI i nput of th is decode r stage sh ould

be le ft ope n. A si m ilar proce dur e for th e fra c tion al p ar t o f a

display will provide automatic suppression of trailing-edge

zeroes. The RBO terminal of the decoder can be OR-tied

with a modulating signal via an isolating buffer to achieve

duration intensity modulation. A suitable signal can be gen-

erated for this purpose by forming a variable frequency

multivibrator with a cross coupled pair of TTL or DTL gates.

Logic Diagram

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DM9374

Applications

It is p ossibl e with com mo n ano de 7- seg me nt LE D di sp lays

and constant current sink decoder drivers to save substan-

tial amounts of power by carefully choosing operating

poin ts on display supply vo ltage. First , examin e the powe r

used in the normal display driving method where the dis-

play and decoder driver are both operated from a +5.0V

regulated supply (VCC = VS).

The po wer di ssipate d by th e LE D and the dr iver output s is

(VCC x Iseg x n Segments). The total power dissipated with

a 15 mA LED displaying an eight (8) would be:

PTOT = 5.0V x 15 mA x 7

= 525 mW

Of this 525 mW, the power actually required to drive the

LED is dependent on the VF drop of each segment. Most

GaAsP LEDs exhibit either a 1.7V or a 3.4V forward volt-

age drop. Therefore, the required total power for seven

segments would be:

P(1.7) = 1.7V x 15 mA x 7

= 178.5 mW

P(3.4)= 3.4V x 15 mA x 7

= 357 mW

The remaining power is dissipated by the driver outputs

which are maintaining the 15 mA constant current required

by the LEDs. Most of this power is wasted, since the driver

can maintain approximately 15 mA with as little as 0.5V

across the output device. By using a separate power

source (VS, Figure 1) for the LEDs, which is set to the LED

VF plus t h e offset v ol t ag e of t h e d r i ver, as mu ch a s 2 80 mW

can be saved per digit. i.e.,

VS = VF (Max) + Voffset

= 2.0V + 0.5V

= 2.5V

PT= 2.5V x 14 mA (from Figure 6) x 7

= 245 mW

These figures show that using a separate supply to drive

the LEDs can offer significant display power savings. In

battery powered equipment, two rechargeable nickel-cad-

mium cells in series would be sufficient to drive the display,

while four su ch cells would be ne eded to oper ate the logic

units.

Another method to save power is to apply intensity modula-

tion to the displays (Figure 2). It is well known that LED dis-

plays are more efficient when operated in pulse mode.

There are two re asons: one, the quantu m efficiency of the

LED material is better; secondly the eye tends to peak

detect. Typically a 20% off duty cy cle to displays (GaAsP)

will produce the same brightness as operating under dc

conditions.

FIGURE 1. Separate Supply for LED Displays

All Inverters are DTL 99 36 or Open Collec to r T T L 7405

FIGURE 2. Intensity Control by RBO Pulse Duty Cycle

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DM9374

Low Power, Low Cost Display Power Sources—In small

line operated systems using TTL/MSI and LED or incan-

descent displays, a signi ficant port ion of the total dc power

is consumed to drive the displays. Since it is irrelevant

whether disp lays a re dri ve n f rom un fil ter ed dc o r p ulsed dc

(at fast rates), a dual power system can be used that

makes better utilization of transformer rms ratings. The

system utilizes a full wave rectified but unsmoothed dc volt-

age to provide the displays with 120 Hz pulsed power while

the reset of the system is driven by a conventional dc

power circuit. The frequency of 120 Hz is high enough to

avoid display flicker problems. The main advantages of this

system are:

• Reduced transformer rating

• Much smaller smoothing capacitor

• Increased LED light output due to pulsed operation

With the standard capacitor filter circuit, the rms current

(full wave) loading of the transformer is approximately

twice the dc output. Most commercial transformer manu-

facturers rate transformers with capacitive input filters as

follows:

Full Wa ve Bridge Rectifier Circuit

Transformer rms current = 1.8 x dc current required

Full Wave Center Tapped Rectifier Circuit

Transformer rms current = 1.2 x dc current required

Therefo re, the re moval of a large por tion of t he filtered dc

current requirement (display power) substantially reduces

the transformer loading.

There are two basic approaches. First (Figure 3) is the

direct full wave rectified unregulated supply to power the

displays. The '74 decoder driver constant current feature

maintains the specified segment current after the LED

diode drop and 0.5V saturation voltage has been reac hed

(≅2.2V). Care must be exercised not to exceed the '74

power ratings and the maximum voltage that the decoder

driver sees in both the “on” and “off” modes.

The seco nd ap proach (Fig ure 4 ) uses a 3-t ermi nal volt age

regulator such as the 7805 to pro vide dc pulsed power to

the display with the peak dc v oltage limited to +5.0V. This

approach allows easier system thermal management by

heat sinking the regulator rather than the display or display

drivers. When this power source is used with an intensity

modulation scheme or with a multiplexed display system,

the frequencies must be chose n such that they do not be at

with the 120 Hz full wave rectified power frequency.

FIGURE 3. Direct Unregulated Display Supply

FIGURE 4. Pulsed Regulated Display Supply

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DM9374

Absolute Maximum Ratings(No te 3) Note 3: The “A bsolute Maxim um Ratings ” are those valu es beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum ratin gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 4: All typic als are at VCC = 5V, TA = 25°C.

Note 5: Not more than one output should be shorted at a time.

Supply Voltage 7V

Input Voltag e 5.5 V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VOUT Output Voltage Applied OFF 10 V

ON (Figure 5)

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current, a–g, VOUT = 5.5V 250 µA

IOL LOW Level Output Current, a–g, VOL = 3.0V 12 18 mA

TAFree Air Operating Temperature 0 70 °C

tS (H) Setup Time HIGH or LOW 75 ns

tS (L) An to LE 30

tH (H) Hold Time HIGH or LOW 0 ns

tH (L) An to LE 0

tW (L) LE Pulse Width LOW 85 ns

Symbol Parameter Conditions Min Typ Max Units

(Note 4)

VIInput Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max 2.4 3.4 V

VOL LOW Level Output Voltage VCC = Min, IOL = Max, VIH = Min 0.2 0.4 V

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IIH HIGH Level Input Curre nt VCC = Max, VI = 2.4V 40 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA

IOS Short Circuit Output Current VCC = Max (Note 5) −18 −57 mA

ICCH Supply Current VCC = Max, VIN = 0V, 50 mA

VOUT = 3.0V

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DM9374

Switching Characteristics

VCC = +5.0V, TA = +25°C

Typical Performance Characteristics

FIGURE 5. Output Voltage Safe Operating Area FIGURE 6. Typical Constant Segment Current

Versus Output Voltage

CL = 15 pF

Symbol Parameter RL = 1 kΩUnits

Min Max

tPLH Propagation Delay 140 ns

tPHL An to a–g 140

tPLH Propagation Delay 140 ns

tPHL LE to a–g 140

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DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of any circuitr y described, no circuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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