©1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC 4833/6
1
CNTRSTR
Counter/
Address
Reg.
A
14R
A
0R
Counter/
Address
Reg.
CNTENR
ADSR
CNTENL
ADSL
CNTRSTL
Dout0-8_L
Dout9-17_L Dout0-8_R
Dout9-17_R
B
W
0
L
B
W
1
L
B
W
1
R
B
W
0
R
I/O0L-I/O
17L I/O0R -I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OEROEL
4833 tbl 01
UBL
LBL
R/WL
CE0L
UBR
LBR
R/WR
CE0R
CE1R
CE1L
64K x 18
MEMORY
ARRAY
CLKR
CLKL
.
,
A
14L
A
0L
Functional Block Diagram
Features:
◆True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆High-speed clock to data access
Commercial: 4.2/5/6ns (max.)
◆Pipelined output mode
◆Counter enable and reset features
◆Dual chip enables allow for depth expansion without
additional logic
◆Full synchronous operation on both ports
7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
Fast 4.2ns clock to data out
1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
◆Separate byte controls for multiplexed bus and bus
matching compatibility
◆LVTTL- compatible, single 3.3V (±150mV) power supply for
core
◆LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os
◆Industrial temperature range (-40°C to +85°C) is
available for selected speeds
◆Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array
PRELIMINARY
IDT70V3379S
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V I/O
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70V3379 is a high-speed32K x 18 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3379 has been optimized for applications having unidirectional or
bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3379 can support an I/O operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS and VSSQ pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
1716
15
1412 13
10
9876543
21 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O9L NC VSS NC
A2L
A4L
CLKL
A8L
A12L
NC
NC OPTL
NC VSSQR NC VSS A1L
A5L
A9L
A13L
NC
VDDQL I/O9R VDDQR VDD
A3L
A6L
NC
A10L
A14L
NC NC
NC VSSQL I/O10L NC
NC
I/O11L NC VDDQR I/O10R
NC
I/O11R NC VSSQR
VDD
NC I/O12L
VDD VSS VSSQR
NC
VSSQL
I/O12R
CNTRST
R
NC I/O14L VDDQR
VDDQL I/O15R
NC VSSQR
NCNC
NC A11L A7L
A0L
NC
I/O7L
NC
I/O6L
I/O8R
UBL
NC
I/O8L
VDDQL
CE0L
CE1L
LBL
CNTRST
L
OEL
I/O0L
I/O2L
I/O1R
ADSR
R/WR
NC
I/O16R
I/O15L
NC
A13R
A12R NC VDD CLKR
I/O0R
NC
NC
NC
NC NC
NC
VSS
A5R
A9R CE0R
CE1R
VDD
VSS
NC
NC
NC
NC
NC
NC A14R A10R UBR
VSSQR
VDDQL
I/O1L
I/O2R
NC
NC NC NC A11R A7R LBROER
VSS
NC
VDDQL
OPTRNC
70V3379BF
BF-208(5)
208-Pin fpBGA
Top View(6)
4833 tbl 02
I/O14R
VDDQL
VSSQL
VDDQR
NC
NC
NC
NC I/O7R
NC
R/WL
NC
ADSL
VDDQL
I/O13R
CNTEN
L
VSS
I/O13L
VSSQL
I/O16L VDDQR
VSSQR I/O17R
I/O17L VDDQL
VSSQL VDD
A8R
CNTEN
R
A6R
A3R
A1R
A2R
A0R
I/O3L I/O4L
A4R
VDD
VSS
VSS VSSQL
VDDQR
VDDQL
VSSQL VDDQR
VSSQR
I/O3R I/O4R VSS
VDDQR
VSS
VDD
VSSQL
VDD VSSQR I/O5R
I/O5L
VDDQR
I/O6R
VSSQL
VSSQR
VDDQL
VDD VSSQL
VDDQR
VSS
VSSQR
VDD
VDD
VSS
VDD
VSS
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
A14L
NC
VSS
NC
IO9L
IO9R
VDDQL
VSSQL
IO10L
IO10R
VDDQR
VSSQR
IO11L
IO11R
IO12L
IO12R
VDD
VDD
VSS
VSS
IO13R
IO13L
IO14R
IO14L
IO15R
IO15L
VDDQL
VSSQL
IO16R
IO16L
VDDQR
VSSQR
IO17R
IO17L
NC
NC
NC
A14R A1R
A0R
OPTR
IO0L
IO0R
VDDQR
VSSQR
IO1L
IO1R
VDDQL
VSSQL
IO2L
IO2R
IO3L
IO3R
IO4L
IO4R
VSS
VSS
VDD
VDD
IO5L
IO5R
VDDQR
VSSQR
IO7R
IO7L
VDDQL
VSSQL
NC
IO8R
IO8L
NC
OPTL
A0L
A1L
IO6R
IO6L
70V3379PRF
PK-128(5)
128-Pin TQFP
Top View(6)
4833 drw 02a
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
CNTRST
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
CNTRST
R
A
6R
A
5R
A
4R
A
3R
A
2R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
.
Pin Configuration(1,2,3,4) (con't.)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS and VSSQ pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = VIH.
3. OE is an asynchronous input signal.
Truth Table IRead/Write and Enable Control(1,2,3)
Pin Names
Left Port Right Port Names
CE0L
, CE1L CE0R, CE1R Chip Enables
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0L
- A14 L A0R - A14R Address
I/O0L
- I/O17 L I/O0R - I/O17R Data Input/Output
CLKLCLKRClock
ADSLADSRAddress Strobe Enable
CNTENLCNTENRCounter Enable
CNTRSTLCNTRSTRCounter Reset
UBL - LBLUBR - LBRByte Enables (9-bit bytes)
VDD Q L VDDQR Power (I/O Bus) (3.3V or 2.5V)(1 )
VSS Q L VSSQR Ground (I/O Bus)(0V)
OPTLOPTROption fo r selecting VDDQX(1,2)
VDD Power (3.3V)(1 )
VSS Ground (0V)
4833 tbl 01
OE CLK CE0CE1UB LB R/W
Upper Byte
I/O9-18
Lower Byte
I/O0-8 MODE
X↑L H H H X High-Z High-Z All Bytes Deselected
X↑LHHL LHigh-Z D
IN Write to Lower Byte Only
X↑LHLHL D
IN High-Z Write to Upper Byte Only
X↑LHLLL D
IN DIN Write to Bo th By te s
L↑LHHLHHigh-Z D
OUT Read Lower Byte Only
L↑LHLHH D
OUT High-Z Read Upper Byte Only
L↑LHLLH D
OUT DOUT Read Both Bytes
H↑L H L L X High-Z High-Z Outputs Disabled
4833 tbl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
2. OPTX selects the operating voltage levels for the I/Os on that port. If OPTX
is set to VIH (3.3V), then that port's I/Os will operate at 3.3V levels and VDDQX
must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os will operate
at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are indepen-
dent of one anotherboth ports can operate at 3.3V levels, both can operate at
2.5V levels, or either can operate at 3.3V with the other at 2.5V.
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage(1)
Absolute Maximum Ratings(1)
Truth Table IIAddress Counter Control(1,2)
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Address
Previous
Address
Addr
Used CLK(6 ) ADS CNTEN CNTRST I/O(3 ) MODE
XX0
↑XX L
(4 ) DI/O (0) Counter Reset to Address 0
An X An ↑ L(4 ) HHD
I/O (n) External Address Loaded into Counter
An Ap Ap ↑HH H D
I/O (p) External Address BlockedCounter disabled (Ap reused)
XApAp + 1
↑H L
(5 ) HD
I/O (p+1) Counter EnabledInternal Address generation
4833 tbl 03
Grade
Ambient
Temperature GND VDD
Commercial 0OC to +70OC0V3.3V
+ 150mV
Industrial -40OC to +85OC0V3.3V
+ 150mV
4833 tbl 04
Symbol Parameter Min. Typ. Max. Unit
VDD Core Supply Voltage 3.15 3.3 3.45 V
VDDQ I/O Supply Voltage(3) 2.375 2.5 2.625 V
VSS Ground 0 0 0 V
VIH Input High Voltage
(Address & Control Inputs)
2.0 ____ VDDQ + 125mV(2 ) V
VIH Input High Voltage - I/O(3) 1.7 ____ VDDQ + 125mV(2) V
VIL Input Low Voltage -0.3(1) ____ 0.7 V
4833 tbl 05a
Symbol Rating Commercial
& Industrial
Unit
VTE RM(2 ) Terminal Voltage
with Resp ect to
GND
-0.5 to +4.6 V
TBIAS Temperature
Under Bias
-55 to +125 oC
TSTG Storage
Temperature
-55 to +125 oC
IOUT DC Output Current 50 mA
4833 tbl 06
Recommended DC Operating
Conditions with VDDQ at 2.5V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os of a given port, the OPT pin for
that port must be set to VIL (0V), and VDDQX for that port must be supplied as
indicated above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os of a given port, the OPT pin for
that port must be set to VIH (3.3V), and VDDQX for that port must be supplied as
indicated above.
Symbol Parameter Min. Typ. Max. Unit
VDD Core Supply Voltage 3.15 3.3 3.45 V
VDDQ I/O Supply Voltage(3) 3.15 3.3 3.45 V
VSS Ground 0 0 0 V
VIH Input High Voltage
(Address & Control Inputs)(3)
2.0 ____ VDDQ + 150mV(2 ) V
VIH Input High Voltage - I/O(3) 2.0 ____ VDDQ + 150mV(2 ) V
VIL Input Low Voltage -0.3(1) ____ 0.8 V
4833 tbl 05b
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
NOTE:
1. At VDD <  2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
Symbol Parameter Test Conditions
70V3379S
UnitMin. Max.
|ILI| Input Leakage Current(1) VDDQ = Max., VIN = 0V to VDDQ ___ 10 µA
|ILO| Output Leakage Current CE
0 = VIH or CE1 = VIL
, VOUT
= 0V to VDDQ ___ 10 µA
VOL (3.3V) Output Low Voltage (2 ) IOL = +4mA, VDDQ = Min. ___ 0.4 V
VOH (3.3V) Output High Voltage (2 ) IOH = -4mA, VDDQ = Min. 2.4 ___ V
VOL (2.5V) Output Low Voltage (2 ) IOL = +2mA, VDDQ = Min. ___ 0.4 V
VOH (2.5V) Output High Voltage (2 ) IOH = -2mA, VDDQ = Min. 2.0 ___ V
4833 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter Conditions(2 ) Max. Unit
CIN Input Capacitance VIN = 3dV 8 pF
COUT
(3 ) Output Capacitance VOUT
= 3dV 10.5 pF
4833 tbl 07
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3,6) (VDD = 3.3V ± 150mV)
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X  0.2V
"X" represents "L" for left port or "R" for right port.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7. The maximum value indicated for IDD is a combination of the current for the memory core and the current for the I/O bus of each port. Worst case power dissipation in
the core occurs while both ports are writing continuously at maximum frequency to the memory array, while worst case for the I/O bus occurs when both ports are
reading continuously at maximum frequency from the array. In either writing or reading, worst case power dissipation occurs when every I/O changes its logic state at the
maximum possible frequency. Thus the IDD maximum value indicated is a calculated value, and is very unlikely to occur in normal operations, which typically involve a
mixture of writes and reads with only 50% of the I/Os (on average) changing state with each cycle.
70V3379S4
Com'l Only
70V3379S5
Com'l Only
70V3379S6
Com'l Only
Symbol Parameter Test Condition Version Typ.(4 ) Max. Typ.(4 ) Max. Typ.(4 ) Max. Unit
IDD Dynamic Ope rating
Current (Both
Ports Active)
CEL and CER= VIL ,
Outputs Open,
f = fMAX(1)
COM'L S 375 460(7 ) 285 360(7 ) 245 310(7) mA
IND S ____ ____ ____ ____ ____ ____
ISB1 Standby Current
(Both Ports - TTL
Le ve l Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L S 145 190 105 145 95 125 mA
IND S ____ ____ ____ ____ ____ ____
ISB2 Standby Current
(One Port - TTL
Le ve l Inputs)
CE"A" = VIL and CE"B" = VIH (5)
Active Port Outputs Open,
f=fMAX(1)
COM'L S 265 325 190 260 175 225 mA
IND S ____ ____ ____ ____ ____ ____
ISB3 Full Standby Current
(Both Ports - CMOS
Le ve l Inputs)
Both Ports CEL and
CER > VDD - 0.2V, VIN > VDD - 0.2V
or VIN < 0.2V, f = 0(2 )
COM'LS615615615
mA
IND S ____ ____ ____ ____ ____ ____
ISB4 Full Standby Current
(One Port - CMOS
Le ve l Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or VIN < 0.2V
Active Port, Outputs Open, f = fMAX(1)
COM'L S 265 325 180 260 170 225 mA
IND S ____ ____ ____ ____ ____ ____
4833 tbl 09
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
8
AC Test Conditions
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
Input Pulse Levels (Add ress & Co ntro ls )
Input Pulse Levels (I/Os)
Input Rise/Fall Times
Input Timing Refe rence Levels
Output Reference Levels
Output Load
GND to 3.0V
GND to 3.0V/GND to 2.35V
3ns
1.5V/1.25V
1.5V/1.25V
Figures 1, 2, and 3
4833 tbl 10
1.5V/1.25
50Ω
50Ω
4833 drw 03
10pF
(Tester)
DATAOUT
,
4833 drw 04
317Ω
5pF*
351Ω
3.3V
DATAOUT
,
833Ω
5pF*
770Ω
2.5V
DATAOUT
,
-1
1
2
3
4
5
6
7
20.5 30 50 80 100 200
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
Capacitance (pF)
∆tCD
(Typical, ns)
4833 drw 05
•
•
••
·
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2,3)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
70V3379S4
Com'l Only
70V3379S5
Com'l Only
70V3379S6
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
tCYC2 Clock Cycle Time (Pipelined ) 7.5 ____ 10 ____ 12 ____ ns
tCH2 Clock High Time (Pipelined) 3 ____ 4____ 5____ ns
tCL 2 Clock Low Time (Pipelined) 3 ____ 4____ 5____ ns
tRClock Rise Time ____ 3____ 3____ 3ns
tFClock Fall Time ____ 3____ 3____ 3ns
tSA Address Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHA Address Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSC Chip Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHC Chip Enable Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSB Byte Enable Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHB Byte Enable Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSW R/ W Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHW R/ W Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSD Input Data Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHD Input Data Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSAD ADS Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHA D ADS Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSCN CNTEN Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHCN CNTEN Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tSRST CNTRST Setup Time 1.8 ____ 2.0 ____ 2.0 ____ ns
tHRST CNTRST Hold Time 0.7 ____ 0.7 ____ 1.0 ____ ns
tOE (1) Output Enable to Data Valid ____ 4____ 5____ 6ns
tOLZ Output Enable to Output Low-Z 0 ____ 0____ 0____ ns
tOHZ Output Enable to Output High-Z 1 4 1 4.5 1 5 ns
tCD2 Clock to Data Valid (Pipelined) ____ 4.2 ____ 5____ 6ns
tDC Data Output Hold After Clock High 1 ____ 1____ 1____ ns
tCKHZ Clock High to Output High-Z 1 3 1 4.5 1.5 6 ns
tCKLZ Clo ck High to Outp ut Low-Z 1 ____ 1____ 1____ ns
Port-to-Port Delay
tCO Clock-to-Clock Offset 6 ____ 8____ 10 ____ ns
4833 tbl 11
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
tSC tHC
CE0(B1)
ADDRESS(B1) A0A1A2A3A4A5
tSA tHA
CLK
4833 drw 07
Q0Q1Q3
DATAOUT(B1)
tCH2 tCL2
tCYC2
ADDRESS(B2) A0A1A2A3A4A5
tSA tHA
CE0(B2)
DATAOUT(B2) Q2Q4
tCD2 tCD2 tCKHZ tCD2
tCKLZ
tDC tCKHZ
tCD2
tCKLZ
tSC tHC
tCKHZ
tCKLZ
tCD2
A6
A6
tDC
tSC tHC
tSC tHC
An An + 1 An + 2 An + 3
tCYC2
tCH2 tCL2
R/W
ADDRESS
CE0
CLK
CE1
UB,LB(0-3)
(3)
DATAOUT
OE
tCD2
tCKLZ
Qn Qn + 1 Qn + 2
tOHZ tOLZ
tOE
4833 drw 06
(1)
(1)
tSC tHC
tSB tHB
tSW tHW
tSA tHA
tDC
tSC tHC
tSB tHB
(4)
(1 Latency)
(5)
(5)
Timing Waveform of a Multi-Device Pipelined Read(1,2)
Timing Waveform of Read Cycle for Pipelined Operation(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V3379 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
CLKL
R/WL
ADDRESSL
DATAINL
CLKR
R/WR
ADDRESSR
DATAOUTR
tSW tHW
tSA tHA
tSD tHD
tSW tHW
tSA tHA
tCO(3)
tCD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
4833 drw 08
tDC
R/W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATAIN Dn + 2
CE0
CLK
4833 drw 09
Qn Qn + 3
DATAOUT
CE1
UB,LB
tCD2 tCKHZ tCKLZ tCD2
tSC tHC
tSB tHB
tSW tHW
tSA tHA
tCH2 tCL2
tCYC2
READ NOP READ
tSD tHD
(3)
(1)
tSW tHW
WRITE
(4)
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
ADDRESS An
CLK
DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3
ADS
CNTEN
tCYC2
tCH2 tCL2
4833 drw 11
tSA tHA
tSAD tHAD
tCD2
tDC
READ
EXTERNAL
ADDRESS READ WITH COUNTER COUNTER
HOLD
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
Qn + 1
R/W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
DATAIN Dn + 3Dn + 2
CE0
CLK
4833 drw 10
DATAOUT Qn Qn + 4
CE1
UB,LB
OE
tCH2 tCL2
tCYC2
tCKLZ tCD2
tOHZ
tCD2
tSD tHD
READ WRITE READ
tSC tHC
tSB tHB
tSW tHW
tSA tHA
(3)
(1)
tSW tHW
(4)
Timing Waveform of Pipelined Read with Address Counter Advance(1)
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
ADDRESS An
D0
tCH2 tCL2
tCYC2
Q0Q1
0
CLK
DATAIN
R/W
CNTRST
4833 drw 13
INTERNAL(3)
ADDRESS
ADS
CNTEN
tSRST tHRST
tSD tHD
tSW tHW
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRESS 1 READ
ADDRESS n
Qn
An + 1 An + 2
READ
ADDRESS n+1
DATAOUT
tSA tHA
1An An + 1
(4)
(5)
(6)
Ax
tSAD tHAD
tSCN tHCN
Timing Waveform of Write with Address Counter Advance(1)
Timing Waveform of Counter Reset(2)
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from An to An +1. The transition shown indicates the time required for the counter to advance. The An +1Address is
written to during this cycle.
ADDRESS An
CLK
DATAIN Dn Dn + 1 Dn + 1 Dn + 2
ADS
CNTEN
tCH2 tCL2
tCYC2
4833 drw 12
INTERNAL(3)
ADDRESS An(7) An + 1 An + 2 An + 3 An + 4
Dn + 3 Dn + 4
tSA tHA
tSAD tHAD
WRITE
COUNTER HOLD WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
tSCN tHCN
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
Functional Description
The IDT70V3379 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to
stall the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT70V3379s for
depth expansion configurations. Two cycles are required with CE0 LOW
and CE1 HIGH to re-activate the outputs.
4833 drw 14
IDT70V3379 CE0
CE1
CE1
CE0
CE0
CE1
A15
CE1
CE0
VDD VDD
IDT70V3379
IDT70V3379
IDT70V3379
Control Inputs
Control Inputs
Control Inputs
Control Inputs UB,LB
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
.
Depth and Width Expansion
The IDT70V3379 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3379 can also be used in applications requiring expanded
width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3379
6.42
IDT70V3379S Preliminary
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Ordering Information
A
Power 99
Speed A
Package A
Process/
Temperature
Range
Blank
I(1) Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
PRF 208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
4
5
6
XXXXX
Device
Type
IDT
Speed in nanoseconds
4833 drw 15
S Standard Power
70V3379 576K (32K x 18-Bit) Synchronous Dual-Port RAM
Commercial Only
Commercial Only
Commercial Only
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Preliminary Datasheet: Definition
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
1/18/98: Initial Public Release
3/15/99: Page 10 Additional Notes
4/28/99: Added fpBGA package
6/8/99: Page 2 Changed package body height from 1.5mm to 1.4mm
6/11/99: Page 5 Deleted note 6 for Table II
7/14/99: Page 2 Corrected pin to T3 to VDDQL
8/4/99: Page 6 Improved power numbers
10/4/99: Upgraded speed to 133MHz, added 2.5V I/O capability
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com