intel. 82586 IEEE 802.3 ETHERNET LAN COPROCESSOR m Performs Complete CSMA/CD Medium a Access Control Functions Independently of CPU High-Level Command Interface mw Supports Established and Emerging LAN Standards a IEEE 802.3/Ethernet (10BASE5) IEEE 802.3/Cheapernet (10BASE2) IEEE 802.3/StarLAN (1BASE5) Proposed 10BASE-T Proposed 10BASE-F Proprietary CSMA/CD Networks up to 10 Mb/s m On-Chip Memory Management Automatic Buffer Chaining Buffer Reclaim After Receipt of Bad Frames Save Bad Frames, Optionally wm Interfaces to 8-Bit and 16-Bit Microprocessors m 48-Pin DIP and 68-Pin PLCC (see Intel Packaging Document, Order Number: 231369) Supports Minimum Component Systems Shared Bus Configuration Interface to 80186 and 80188 Microprocessors Without Glue Supports High-Performance Systems Bus Master, with On-Chip DMA 5-MB/s Bus Bandwidth Compatible with Dual-Port Memory Back-to-Back Frame Reception at 10 Mb/s Network Management CRC Error Tally Alignment Error Tally Location of Cable Faults Self-Test Diagnostics Internal Loopback External Loopback Internal Register Dump Backoff Timer Check SYSTEM INTERFACE oS > COMMAND UNIT MICROINSTRUCTION ROM pus system ciock| 'NTERFACE = ANO CONTROL SIGNALS e/) f RECEIVE . OMA UNIT CONTROL (4 CHANNELS) MOST SIGNIFICANT ADDRESS (Azy - Aig) cy MULTIPLEKED ADDRESS AND DATA OATA INTERFACE UNIT SERIAL INTERFACE. RECEIVE 8 cor a FIFO CZ RECEIVER cRS (16 BYTES) ro Axo TRANSMIT a > 1x0 I TRANSMITTER (18 BYTES) wa ae 231246-1 Figure 1. 82586 Functional Block Diagram *IBM is a trademark of International Business Machines Corporation. 1-1 November 1991 Order Number: 231246-007intel. 82586 azo 1 Vec arose (12 a2i awe U3 a22 (RD) a7de az. (WA) awe 5 ane aois (16 HOLD ani 7 HLDA aon 8 3 woh abt (1s $5 (DER) aot | READY (ALE) ante : wT Vsg. ( AADY/SROY aos G Voc ave cA aor (J RESET ave C man AX aos G CLK apa crs aos cbt ap2 J ors ani qj ars apo (1 TKO aye TRE Vss q Axo 231246-2 NOTE: The symbols in parentheses correspond to minimum mode. Plastic Leaded Chip Carrier ma = on aoa i 1 g22G28b Pee sk SkEBE onoo noo ooo oooon neq] NC aps NC aos clk ap7 MN/MX ADs RESET 09 CA Vss Voc Vss N82586 Vec Vs 681 PLCC Voc Vss (TOP viEW) Vee p10 ARDY/SRDY INT READY(ALE) ADI S0(DEN) aD12 J 51(DT/R) ani3 Cy Nc neq I NC cos se w a wa w a on ~ & a20gs cos co OE nn cohen an ow az NS a a a ~~ LOA CAS non @ ny iw a seernreRaage x e | a PIN NO. 1 MARK: 755 %<=4 > SIRE 3S << o x O A ol ~~ Nn < <q 231246-41 Figure 2. 82586 Pinout Diagramsintel. 82586 The 82586 is an intelligent, high-performance Local Area Network coprocessor, implementing the CSMA/CD access method (Carrier Sense Multiple Access with Collision Detection). It performs all time- critical functions independently of the host proces- sor, which maximizes performance and network efficiency. The 82586 performs the full set of IEEE 802.3 CSMA/CD Medium Access Control and channel in- terface functions including: framing, preamble gen- eration and stripping, source address generation, destination address checking, CRC generation and checking, short frame detection. Any data rate up to 10 Mb/s can be used. The 82586 features a powerful host system inter- face. It automatically manages memory structures with command chaining and bidirectional data chain- ing. An on-chip DMA controller manages four chan- nels transparently to the user. Buffers containing er- rored or collided frames can be automatically recov- ered. The 82586 can be configured for 8-bit or 16-bit data path, with maximum burst transfer rate of 2 or 4 MB/s respectively. Memory address space is 16 megabytes maximum. The 82586 provides two independent 16-byte FI- FOs, one for receiving and one for transmitting. The threshold for block transfer to/from memory is pro- grammable, enabling the user to optimize bus over- head for a given worst case bus latency. The 82586 provides a rich set of diagnostic and net- work management functions including: internal and external loopbacks, exception condition tallies, channel activity indicators, optional capture of all frames regardless of destination address, optional capture of errored or collided frames, and time do- main reflectometry for locating faults in the cable. The 82586 can be used in either baseband or broad- band networks. It can be configured for maximum network efficiency (minimum contention overhead) for any length network operating at any data rate up to 10 Mb/s. The controller supports address field lengths of 1, 2, 3, 4, 5, or 6 bytes. It can be config- ured for either the IEEE 802.3/Ethernet or HDLC method of frame delineation. Both 16-bit and 32-bit CRCs are supported. The 82586 is fabricated in Intels reliable HMOS |! 5-V technology and is available in a 48-pin DIP or 68-pin PLCC package. Table 1. 82586 Pin Description 48 Pin DIP | 68 PinPLCC | Type Symbol Pin No. Pin No. Level Name and Function Voc. Voc | 48, 36 8, 9, 10, 11, System Power: + 5V Power Supply. 61, 62 Vss, Vss 12, 24 26, 27, 41, System Ground. 42, 43, 44 RESET 34 13 I RESET is an active HIGH internaily synchronized signal, TTL | causing the 82586 to terminate present activity immediately. The signal must be HIGH for at least four clock cycles. The 82586 will execute RESET within ten system clock cycles starting from RESET HIGH. When RESET returns LOW, the 82586 waits for the first CA to begin the initialization sequence. TxD 27 22 0 Transmitted Serial Data output signal. This signal is HIGH TTL | when not transmitting. TxC 26 23 | Transmit Data Clock. This signal provides timing * information to the internal serial logic, depending upon the mode of data transfer. For NRZ mode of operation, data is transferred to the TxD pin on the HIGH to LOW clock transition. RxD 25 24 | Received Data Input Signal. TTL RxC 23 28 i Received Data Clock. This signal provides timing * information to the internal shifting logic depending upon the mode of data transfer. For NRZ data, the state of the RxD pin is Sampled on the HIGH to LOW clock transition. *See D.C. Characteristics. 1-382586 Table 1. 82586 Pin Description (Continued) Symbol 48 Pin DIP Pin No. 68 Pin PLCC Pin No. Type Level Name and Function a or n 28 2t 0 TTL Request To Send signal. When LOW, notifies an externa! interface that the 82586 has data to transmit. It is forced HIGH after a Reset and while the Transmit Serial Unit is not sending data. 29 20 Active LOW Clear To Send input enables the 82586 transmitter to actually send data. It is normally used as an interface handshake to RTS. This signal going inactive stops transmission. It is internally synchronized. If CTS goes inactive, meeting the setup time to TxC negative edge, transmission is stopped and RTS goes inactive within, at most, two TxC cycles. 31 18 Active LOW Carrier Sense input used to notify the 82586 that there is traffic on the serial link. It is used only if the 82586 is configured for external Carrier Sense. When so configured, external circuitry is required for detecting serial link traffic. it is internally synchronized. To be accepted, the signal must stay active for at least two serial clock cycles. 30 19 Active LOW Collision Detect input is used to notify the 82586 that a collision has occurred. It is used only if the 82586 is configured for externa! Collision Detect. External circuitry is required for detecting the collision. It is internally synchronized. To be accepted, the signal must stay active for at least two serial clock cycles. During transmission, the 82586 is able to recognize a collision one bit time after preamble transmission has begun. INT 38 TTL Active HIGH Interrupt request signal. CLK 32 15 MOS The system clock input from the 80186 or another symmetrical clock generator. MN/MX 33 14 When HIGH, MN/Mx selects RD, WR, ALE DEN, DT/R (Minimum Mode). When LOW, MN/M<X selects A22, A23, READY, SO, ST (Maximum Mode). Note: This pin should be static during 82586 operation. ADO-AD15 6-11, 13-22 29-33, 36- 40, 45, 48, 49, 50, 53, 54 1/0 TTL These lines form the time multiplexed memory address (t1) and data (t2, t3, tW, t4) bus. When operating with an 8-bit bus, the high byte will output the address only during T1. ADO-AD15 are floated after a RESET or when the bus is not acquired. A16-A18 A20-A23 1,3-5 45-47 55-57, 59, 63-65 These lines constitute 7 out of 8 most significant address bits for memory operation. They switch during t1 and stay valid during the entire memory cycle. The lines are floated after RESET or when the bus is not acquired. Address lines A22 and A23 are not available for use in minimum mode. A19/S6 58 During t1 it forms line 19 of the memory address. During t2 through t4 it is used as a status indicating that this is a Master peripheral cycle, and is HIGH. Its timing is identical to that of ADO-AD15 during write operation. 1-482586 Table 1. 82586 Pin Description (Continued) Symbol 48 Pin DIP Pin No. 68 Pin PLCC Pin No. Type Level Name and Function HOLD 43 67 0 TTL HOLD is an active HIGH signal used by the 82586 to request local bus mastership at the end of the current CPU bus transfer cycle, or at the end of the current DMA burst transfer cycle. in normal operation, HOLD goes inactive before HLDA. The 82586 can be forced off the bus by HLDA going inactive. In this case, HOLD goes inactive within four clock cycles in word mode and eight clock cycles in byte mode. HLDA 42 68 HLDA is an active HIGH Hold Acknowledge signal indicating that the CPU has received the HOLD request and that bus control has been relinquished to the 82586. It is internally synchronized. After HOLD is detected as LOW, the processor drives HLDA LOW. Note, CONNECTING Vcc TO HLDA IS NOT ALLOWED because it will cause a deadlock. Users wanting to give permanent bus access to the 82586 should connect HLDA with HOLD. 35 12 The CA pin is a Channel Attention input used by the CPU to initiate the 82586 execution of memory resident Command Blocks. The CA signal is synchronized. internally. The signal must be HIGH for at least one system clock period. It is latched internally on HIGH to LOW edge and then detected by the 82586. oD mi 44 66 The Bus High Enable signal (BHE) is used to enable data onto the most significant half of the data bus. Its timing is identical to that of A16-A23. With a 16-bit bus it is LOW and with an 8-bit bus it is HIGH. Note: after RESET, the 82586 is configured to 8-bit bus. READY 39 This active HIGH signal is the acknowledgement from the addressed memory that the transfer cycle can be completed. While LOW, it causes wait states to be inserted. This signal must be externally synchronized with the system clock. The Ready signal internal to the 82586 is a logical OR between READY and SRDY/ARDY. ARDY/SRDY 37 This active HIGH signal performs the same function as READY. If it is programmed at configure time to SRDY, it is identical to READY. If it is programmed to ARDY, the positive edge of the Ready signal is internally synchronized. Note, the negative edge must still meet setup and hold time specifications, when in ARDY mode. The ARDY signal must be active for at least one system clock HIGH period for proper strobing. The Ready signal internal to the 82586 is a logical OR between READY (in Maximum Mode only) and SRDY/ARDY. Note that following RESET, this pin assumes ARDY mode. 1-582586 Table 1. 82586 Pin Description (Continued) Symbol 48 Pin DIP Pin No. 68 Pin PLCC Pin No. Type Level Name and Function | a QI 40,41 4,3 0 TTL Maximum mode only. These status pins define the type of DMA transfer during the current memory cycle. They are encoded as follows: Read Memory Write Memory 1 1 Passive Status is active from the middle of t4 to the end of t2. They return to the passive state during t3 or during tW when READY or ARDY is HIGH. These signals can be used by the 8288 Bus Controller to generate all memory control and timing signals.* Any change from the passive state, signals the 8288 to start the next t1 to t4 bus cycle. These pins are pulled HIGH and floated after a system RESET and when the bus is not acquired. ST 50 0 0 Not Used 0 1 1 0 46 64 Used in minimum mode only. The read strobe indicates that the 82586 is performing a memory read cycle. RD is active LOW during t2, t8 and tW of any read cycle. This signal is pulled HIGH and floated after a RESET and when the bus is not acquired. 45 65 Used in minimum mode only. The write strobe indicates that the 82586 is performing a write memory cycle. WR is active LOW during t2, t3 and tW of any write cycle. It is pulled HIGH and floats after RESET and when the bus is not acquired. ALE 39 Used in minimum mode only. Address Latch Enable is provided by the 82586 to latch the address into the 8282/8283 address latch. It is a HIGH pulse, during t1 (clock low) of any bus cycle. Note that ALE is never floated. | Oo m 2 40 Used in minimum mode only. Data ENable is provided as output enable for the 8286/8287 transceivers in a stand- alone (no 8288) system. DEN is active LOW during each memory access. For a read cycle, it is active from the middle of t2 until the beginning of t4. For a write cycle, it is active from the beginning of t2 until the middle of t4. Itis pulled HIGH and floats after a system RESET or when the bus is not acquired. DT/R 41 Used in minimum mode only. DT/R is used in non-8288 systems using an 8286/8287 data bus transceiver. It controls the direction of data flow through the Transceiver. Logically, DT/R is equivalent to 57. It becomes valid in the t4 preceding a bus cycle and remains valid until the final t4 of the cycle. This signal is pulled HIGH and floated after a RESET or when the bus is not acquired. NOTE: *8288 does not support 10 MHz operation.intel. 82586 82586/HOST CPU INTERACTION Communication between the 82586 and the host is carried out via shared memory. The 82586s on-chip DMA capability allows autonomous transfer of data blocks (buffers, frames) and relieves the CPU of byte transfer overhead. The 82586 is optimized to interface the iAPX 186, but due to the small number of hardware signals between the 82586 and the CPU, the 82586 can operate easily with other proc- essors. The 82586/host interaction is explained separately in terms of the logical interface and the hardware bus interface. The 82586 consists of two independent units: Com- mand Unit (CU) and Receive Unit (RU). The CU exe- cutes commands from shared memory. The RU handles all activities related to frame reception. The CU and RU enable the 82586 to engage in the two types of activities simultaneously: the CU may be fetching and executing commands out of memory, and the RU may be storing received frames in mem- ory. CPU intervention is only required after the CU executes a sequence of commands or the RU stores a sequence of frames. The only hardware signals that connect the CPU and the 82586 are INTERRUPT and CHANNEL ATTEN- TION (see Figure 3). Interrupt is used by the 62586 to draw the CPUs attention to a change in the con- tents of the SCB. Channel Attention is used by the CPU to draw the 82586s attention. 82586 SYSTEM MEMORY STRUCTURE The Shared Memory structure consists of four parts: Initialization Root, System Contro! Block (SCB), Command List, and Receive Frame Area (RFA) (see Figure 4). The Initialization Root is at a predetermined location in the memory space, (OFFFFF6H), known to both the host CPU and the 82586. The root is accessed at initialization and points to the System Control Block. The System Control Block (SCB) functions as a bidi- rectional mail drop between the host CPU, CU and RU. It is the central element through which the CPU and the 82586 exchange control and status informa- tion. The SCB consists of two parts, the first of which entails instructions from the CPU to the 82586. These include: control of the CU and RU (START, ABORT, SUSPEND, RESUME), a pointer to the list of commands for the CU, a pointer to the receive frame area, and a set of Interrupt acknowl- edge bits. The second entails status information keyed by the 82586 to the CPU, including: state of the CU and RU (e.g. IDLE, ACTIVE READY, SUS- PENDED, NO RECEIVE RESOURCES), interrupts bits (command completed, frame received, CU not ready, RU not ready), and statistics (see Figure 4). The Command List serves as a program for the CU. Individual commands are placed in memory units called a Command Block, or CB. CB's contain com- mand specific parameters and command specific statuses. Specifically, these high level commands are called Action Commands (e.g. Transmit, Config- ure). A specific command, Transmit, causes transmission of a frame by the 82586. The Transmit command block includes Destination Address, Length Field, and a pointer to a list of linked buffers that holds the frame to be constructed from several buffers scat- tered in memory. The Command Unit performs with- CHANNEL ATTENTION CPU INTERRUPT cA SHARED MEMORY INITIALIZATION ROOT BLOCK (SCB): MAILBOX COMMAND LIST 231246-3 Figure 3. 82586/Host CPU Interaction 1-7 L82586 INITIALIZATION ROOT peer SYSTEM conaot | BLOCK (SCB) STATUS COMMAND COMMAND LIST POINTER r RECEIVE FRAME fF- STATISTICS t RECEIVE BUFFER DESCRIPTOR (RBD) COMMAND LIST (CBL) COMMAND TRANSMIT see eta) or a} (1) (2) RECEIVE FFER a a Te TRANSMIT BUFFER DESCRIPTOR (780) RECEIVE BUFFER RECEIVE BUFFER | cs) | 231246-4 Figure 4. 82586 Shared Memory Structure out the CPU intervention, the DMA of each buffer and the prefetching of references to new buffers in parallel. The CPU is notified only after successful transmission or retransmission. The Receive Frame Area is a list of Free Frame De- scriptors (Descriptors not yet used) and a list of buff- ers prepared by the user. It is conceptually distinct from the Command List. Frames arrive without being solicited by the 82586. The 82586 must be prepared to receive them even if it is engaged in other activi- ties and to store them in the Free Frame Area. The Receive Unit fills the buffers upon frame reception and reformats the Free Buffer List into received frame structures. The frame structure is virtually identical to the format of the frame to be transmitted. The first frame descriptor is referenced by SCB. A Frame Descriptor and the associated Buffer De- scriptor wasted upon receiving a Bad Frame (CRC or Alignment errored, Receive DMA overrun errored, or Collision fragmented frame) are automatically re- claimed and returned to the Free Buffer List, unless the chip is configured to Save Bad Frames. 1-8 Receive buffer chaining (i.e. storing incoming frames in a linked list of buffers) improves memory utiliza- tion significantly. Without buffer chaining, the user must allocate consecutive blocks of the maximum frame size (1518 bytes in Ethernet) for each frame. Taking into account that a typical frame size may be about 100 bytes, this practice is very inefficient. With buffer chaining, the user can allocate small buffers and the 82586 uses only as many as needed. In the past, the drawback of buffer chaining was the CPU processing overhead and the time involved in the buffer switching (especially at 10 Mb/s). The 82586 overcomes this drawback by performing buff- er management on its own for both transmission and reception (completely transparent to the user). The 82586 has a 22-bit memory address range in minimum mode and 24-bit memory address range in maximum mode. All memory structures, the System Contro! Block, Command List, Receive Descriptor List, and al! buffer descriptors must reside within one 64K-byte memory segment. The Data Buffers can be located anywhere in the memory space.intel. 82586 TRANSMITTING FRAMES The 82586 executes high level action commands from the Command List in external memory. Action commands are fetched and executed in parallel with the host CPUs operation, thereby significantly im- proving system performance. The general action commands format is shown in Figure 5. COMMAND STATUS CONTROL FIELDS COMMAND LINK FIELD A NEXT (POINTER TO NEXT COMMAND) [" COMMAND PARAMETER FIELD (COMMANO-SPECIFIC PARAMETERS) 231246-5 Figure 5. Action Command Format Message transmission is accomplished by using the Transmit command. A single Transmit command contains, as part of the command-specific parame- ters, the destination address and length field for the transmitted frame along with a pointer to a buffer area in memory containing the data portion of the frame. (See Figure 15.) The data field is contained in a memory data structure consisting of a Buffer De- scriptor (BD) and Data Buffer (or a linked list of buff- er descriptors and buffers) as shown in Figure 6. The BD contains a Link Field which points to the next BD on the list and a 24-bit address pointing to the Data Buffer itself. The length of the Data Buffer is speci- fied by the Actual Count field of the BD. Using the BDs and Data Buffers, multiple Data Buff- ers can be chained together. Thus, a frame with a jong Data Field can be transmitted using multiple (shorter) Data buffers chained together. This chain- ing technique allows the system designer to develop efficient buffer management policies. The 82586 automatically generates the preamble (alternating 1s and 0s) and start frame delimiter, fetches the destination address and length field from the Transmit command, inserts its unique address as the source address, fetches the data field from TRANSMIT (BD) ACTUAL COUNT r NEXT BUFFER DESCRIPTOR LINK FIELD. * OB ADORESS (24 BITS) of DATA BUFFER (08) 231246-6 Figure 6. Data Buffer Descriptor and Data Buffer Structure buffers pointed to by the Transmit command, and computes and appends the CRC at the end of the frame. See Figure 7. The 82586 can be configured to generate either the Ethernet or HDLC start and end frame delimiters. In the Ethernet mode, the start frame delimiter is 10101011 and the end frame delimiter indicated by the lack of a signal after transmitting the last bit of the frame check sequence field. When in the HDLC mode, the 82586 will generate the 01111110 flag for the start and end frame delimiters and perform the standard bit stuffing/stripping. in addition, the 82586 will optionally pad frames that are shorter than the specified minimum frame length by append- ing the appropriate number of flags to the end of the frame. in the event of a collision (or collisions), the 82586 manages the entire jam, random wait and retry pro- cess, reinitializing DMA pointers without CPU inter- vention. Multiple frames can be sent by linking the appropriate number of Transmit commands togeth- er. This is particularly useful when transmitting a message that is larger than the maximum frame size (1518 bytes for Ethernet). RECEIVING FRAMES In order to minimize CPU overhead, the 82586 is designed to receive frames without CPU supervi- sion. The host CPU first sets aside an adequate START PREAMBLE] FRAME ADDR oRR DELIMITER LENGTH | DATA FRAME END FIELD FIELD CHECK | FRAME SEQUENCE| DELIMITER Figure 7. Frame Format 1-9intel. 82586 SYSTEM CONTROL 4 BLOCK | Se i | FRAME | |__| DESCRIPTOR (RFD) FO oe FO | | | | FREE BUFFER LIST (FBL) \ i RECEIVE | BUFFER RBO ABO | DESCRIPTOR (RBD) | ! I | | DATA | | BUFFER (DB) 0B 068 | | | | _ eee RECEIVER FRAME AREA(RFA) | 231246-7 Figure 8. Receive Frame Area Diagram amount of receive buffer space and then enabies the 82586s Receive Unit. Once enabled, the RU watches for any of its frames which it automatically RECEIVE FRAME STATUS stores in the Receive Frame Area (RFA). The RFA consists of a Receive Descriptor List (RDL) and a list NEXT RECEIVE of free buffers called the Free Buffer List (FBL) as LINK FIELD | _ FRAME DESCRIPTOR shown in Figure 8. The individual Receive Frame Descriptors that make up the ADL are used by the BUFFER DESCRIPTOR - BUFFER DESCRIPTOR 82586 to store the destination and source address, LINK FIELD length field and status of each frame that is re- ceived. (Figure 9.) DESTINATION ADDRESS The 82586, once enabled, checks each passing frame for an address match. The 82586 will recog- SOURCE ADDRESS nize its own unique address, one or more multicast addresses or the broadcast address. {f a match oc- LENGTH FIELD curs, it stores the destination and source address and length field in the next available RFD. It then begins filling the next free Data Buffer on the FBL 231246-8 (which is pointed to by the current RFD) with the data portion of the incoming frame. As one DB is filled, the 82586 automatically fetches the next DB on the FBL until the entire frame is received. This buffer chaining technique is particularly memory effi- cient because it allows the system designer to set aside buffers that fit a frame size that may be much shorter than the maximum allowable frame. Figure 9. Receive Frame Descriptor Once the entire frame is received without error, the 82586 performs the following housekeeping tasks: Updates the Actual Count field of the last Buffer Descriptor used to hold the frame just received with the number of bytes stored in its associated Data Buffer.ntel. 82586 Fetches the address of the next free Receive Frame Descriptor. Writes the address of the next free Buffer De- scriptor into the next free Receive Frame De- scriptor. Posts a Frame Received interrupt status bit in the SCB. @ Interrupts the CPU. In the event of a frame error, such as a CRC error, the 82586 automatically reinitializes its DMA point- ers and reclaims any data buffers containing the bad frame. As long as Receive Frame Descriptors and data buffers are available, the 82586 will continue to receive frames without further CPU help. 82586 NETWORK MANAGEMENT AND DIAGNOSTIC FUNCTIONS The behavior of data communication networks is typically very complex due to their distributed and asynchronous nature. it is particularly difficult to pin- point a failure when it occurs. The 82586 was de- signed in anticipation of these problems and includes a set of features for improving reliability and testability. The 82586 reports on the following events after each frame transmitted: Transmission successful. Transmission unsuccessful; lost Carrier Sense. e Transmission unsuccessful; lost Clear-to-Send. Transmission unsuccessful; DMA underrun be- cause the system bus did not keep up with the transmission. Transmission unsuccessful; number of collisions exceeded the maximum allowed. The 82586 checks each incoming frame and reports on the following errors, (if configured to Save Bad Frame): CRC error: incorrect CRC in a well aligned frame. Alignment error: incorrect CRC in a misaligned frame. Frame too short: the frame is shorter than the configured value for minimum frame length. Overrun: the frame was not completely placed in memory because the system bus did not keep up with incoming data. Out of buffers: no memory resources to store the frame, so part of the frame was discarded. NETWORK PLANNING AND MAINTENANCE To perform proper planning, operation, and mainte- nance of a communication network, the network management entity must accumulate information on network behavior. The 82586 provides a rich set of network-wide diagnostics that can serve as the ba- sis for a network management entity. Network Activity information is provided in the status of each frame transmitted. The activity indicators are: Number of collisions: number of collisions the 82586 experienced in attempting to transmit this frame. Deferred transmission: indicates if the 82586 had to defer to traffic on the link during the first trans- mission attempt. Statistics registers are updated after each received frame that passes the address filtering, and is longer than the Minimum Frame Length configuration pa- rameter. CRC errors: number of frames that experienced a CRC error and were property aligned. Alignment errors: number of frames that experi- enced a CRC error and were misaligned. No-resources: number of correct frames lost due to lack of memory resources. Overrun errors: number of frame sequences lost due to DMA overrun. The 82586 can be configured to Promiscuous Mode. In this mode it captures all frames transmitted on the Network without checking the Destination Address. This is useful in implementing a monitoring station to capture all frames for analysis. The 82586 is capable of determining if there is a short or open circuit anywhere in the Network using the built in Time Domain Refiectometer (TDR) mech- anism. STATION DIAGNOSTICS The chip can be configured to External Loopback. The transmitter to receiver interconnection can be placed anywhere between the 82586 and the fink to locate faults, for example: the 82586 output pins, the Serial Interface Unit, the Transceiver cable, or in the Transceiver.intel. 82586 The 82586 has a mechanism recognizing the trans- ceiver heart beat signal for verifying the correct op- eration of the Transceivers collision detection cir- Cuitry. 82586 SELF TESTING The 82586 can be configured to Internal Loopback. {t disconnects itself from the Serial interface Unit, and any frame transmitted is received immediately. The 82586 connects the Transmit Data to the Re- ceive Data signa! and the Transmit Clock to the Re- ceive Clock. The Dump Command causes the chip to write over 100 bytes of its internal registers to memory. The Diagnose command checks the exponential Backoff random number generator internal to the 82586. CONTROLLING THE 82586 The CPU controls operation of the 82586s Com- mand Unit (CU) and Receive Unit (RU) of the 82586 via the System Control Block. THE COMMAND UNIT (CU) The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to a CPU program. A Command Block (CB) is associated with each Action Command. The CU can be modeled as a logical machine that takes, at any given time, one of the following states: e iDLECU is not executing a command and is not associated with a CB on the list. This is the initial state. SUSPENDEDCU is not executing a command but (different from IDLE) is associated with a CB on the list. ACTIVECU is currently executing an Action Command, and points to its CB. The CPU may affect the CU operation in two ways: issuing a CU control Command or setting bits in the COMMAND word of the Action Command. THE RECEIVE UNIT (RU) The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a logical machine that takes, at any given time, one of the following states: e 1DLERU has no memory resources and is dis- carding incoming frames. This is the initia! RU state. NO-RESOURCESRU has no memory resourc- es and is discarding incoming frames. This state differs from the IDLE state in that RU accumu- lates statistics on the number of frames it had to discard. SUSPENDEDRU has free memory resources to store incoming frames but discard them any- way. 15 ODDBYTE EVENBYTE 0 T T T T T qt SCB STAT 0 cus 0 RUS o | o | o | | &tarus) 4 i L 1 4 4 Ls T v t vv R 7 T ACK \\ cuc E RUC \\ \\ \\\\\ iCOMMAND) i L i L 1 s - L L : CBLOFFSET SCB+ 4 RFA OFFSET SCB+6 CRCERRS SCB+8 ALNERRS SCB+ 10 RSCERRS SCB+ 12 OVANERRS ScB+ 14 231246-9 Figure 10. System Control Block (SCB) Format 1-12intel. 82586 e READYRU has free memory resources and stores incoming frames. The CPU may affect RU operation in three ways: issuing an RU Control Command, setting bits in Frame Descriptor, FD, COMMAND word of the frame currently being received, or setting EL bit of Buffer Descriptor, BD, of the buffer currently being filled. SYSTEM CONTROL BLOCK (SCB) The System Control Block is the communication mail-box between the 82586 and the host CPU. The SCB format is shown in Figure 10. The host CPU issues Control Commands to the 82586 via the SCB. These commands may appear at any time during routine operation, as determined by the host CPU. After the required Control Com- mand is setup, the CPU sends a CA signal to the 82586. SCB is also used by the 82586 to return status infor- mation to the host CPU. After inserting the required status bits into SCB, the 82586 issues an Interrupt to the CPU. The format is as follows: STATUS word: Indicates the status of the 82586. This word is modified only by the 82586. Defined bits are: CX Acommand in the CBL having its I (interrupt) bit set has been executed. A frame has been received. The Command Unit left the Active state. The Receive Unit left the Ready state. (3 bits) this field contains the status of the Command Unit. Valid values are: 0 Idle 1 Suspended 2 Active 3-7 Not Used (3 bits) this field contains the status of the Receive Unit. Valid values are: 0 Idle Suspended No Resources Not Used Ready (Bit 15) FR CNR (Bit 14) (Bit 13) RNR | (Bit 12) CUS | (Bits 8-10) RUS | (Bits 46) 1 2 3 4 5- 7 Not Used COMMAND word: Specifies the action to be per- formed as a result of the CA. This word is set by the CPU and cleared by the 82586. Defined bits are: ACK-CX | (Bit 15) Acknowledges the command executed event. Acknowledges the frame received event. Acknowledes that the Command Unit became not ready. Acknowledges that the Receive Unit became not ready. (3 bits) this field contains the command to the Command Unit. NOP (doesnt affect current State of the unit). Start execution of the first command on the CBL. Ifa command is in execution, then complete it before starting the new CBL. The beginning of the CBL is in CBL OFFSET. Resume the operation of the command unit by executing the next command. This operation assumes that the command unit has been previously suspended. Suspend execution of commands on CBL after current command is complete. Abort execution of commands immediately. Reserved, illegal for use. (3 bits) This field contains the command to the receive unit. Valid values are: NCP (does not alter current state of unit). Start reception of frames. If a frame is being received, then complete reception before starting. The beginning of the RFA is contained in the RFA OFFSET. Resume frame receiving (only when in suspended state.) Suspend frame receiving. If a frame is being received, then complete its reception before suspending. Abort receiver operation immediately. Reserved, illegal for use. Reset chip (logically the same as hardware ACK-FR_ | (Bit 14) ACK-CNA | (Bit 13) ACK-RNR | (Bit 12) CcuCc (Bits 8-10) 5-7 (Bits 4-6) RUC 5-7 (Bit 7) RESET RESET).intel. 82586 CBL-OFFSET: Gives the 16-bit offset address of the first command (Action Command) in the command list to be execut- ed following CU-START. Thus, the 82586 reads this word only if the CUC field contained a CU-START Control Command. RFA-OFFSET: Points to the first Receive Frame Descriptor in the Receive Frame Area. CRCERRS: CRC Errors - contains the number of properly aligned frames received with a CRC error. ALNERRS: Alignment Errors - contains the number of misa- ligned frames received with a CRC error. RSCERRS: Resource Errors - records the number of correct in- coming frames discarded due to lack of memory resources (buffer space or received frame descrip- tors). OVRNERRS: Overrun Errors - counts the number of received frame sequences lost because the memory bus was not available in time to transfer them. ACTION COMMANDS The 82586 executes a program that is made up of action commands in the Command List. As shown in Figure 5, each command contains the command field, status and control fields, link to the next action command in the CL, and any command-specific pa- rameters. This command format is called the Com- mand Block. The 82586 has a repertoire of 8 commands: NOP Setup Individual Address Configure Setup Multicast Address Transmit TDR Diagnose Dump NOP This command results in no action by the 82586, except as performed in normal command process- ing. It is present to aid in Command List manipula- tion. NOP command includes the following fields: STATUS word (written by 82586): c (Bit 15) Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Compietion COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion | (Bit 13) Interrupt After Completion CMD | (Bits0-2) | NOP = 0 LINK OFFSET: Address of next Command Block 15 ODD BYTE EVENBYTE 0 0 cloelela ZEROS (STATUS) T T eajfs |i sz LEE CMD =0 2 LEE <7) 4 (COMMAND) LINK OFFSET 231246~10 Figure 11. The NOP Command Block 1-14intel. 82586 1A-SETUP This command loads the 82586 with the Individual Address. This address is used by the 82586 for rec- ognition of Destination Address during reception and insertion of Source Address during transmission. The IA-SETUP command includes the following fields: 15 ODD BYTE EVEN BYTE 0 0 c | se fox] a ZEROS (STATUS) T t _ 2 ey sit CMD = 1 (COMMAND) i 1 LINK OFFSET 4 2ND BYTE ' 1ST BYTE . ' Law oe 1 INDIVIDUAL ADDRESS 8 eo = t - 1 ' 10 NTH BYTE 1 231246-11 Figure 12. The IA-SETUP Command Block STATUS word (written by 82586). Cc (Bit 15) * Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Compietion A (Bit 12) Command Aborted COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion | (Bit 13) Interrupt After Completion CMD ; (Bits 0-2) | IA-SETUP = 1 LINK OFFSET: Address of next Command Block INDIVIDUAL ADDRESS: Individual Address param- eter The least significant bit of the Individual Address pa- rameter must be zero for IEEE 802.3/Ethernet. However, no enforcement of 0 is provided by the 82586. Thus, an Individual Address with least signifi- cant bit 1, is possible. CONFIGURE The CONFIGURE command is used to update the 82586 operating parameters. The CONFIGURE command includes the following fields: STATUS word (written by 82586): Cc (Bit 15) Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Completion A (Bit 12) Gommand Aborted COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion I (Bit 13) * Interrupt After Completion CMD | (Bits 0-2) | Configure = 2 LINK OFFSET: Address of next Command Block Byte 6-7: BYTE CNT | (Bits 0-3)| Byte Count, Number of bytes including this one, holding the parameters to be configured. A number smaller than 4 is interpreted as 4.A number greater than 12 is interpreted as 12.intel. 82586 18 ODOBYTE EVEN BYTE oO c B OK A ZEROS 00 el $s 1 cup = > 02 iL aL LINK OFFSET 04 : Fro LIM : evte CNT : 06 XT | INT + + / * , * silat] "TEM | de | toomeen | Be [atoy INTERFRAME SPACING : Bor ACR : uN palo 0A I. 7a 1. 4 i 1 RETRY NUM SLT TM (H)} SLOT TIME (L) oc cot tn crs +t pap a [nsa ero a | ac [ens 0c sACc 1 , src 1 L STF 16 INS | CRS] QRZ | DIS MIN FRM LEN 10 231246-13 Figure 13. The CONFIGURE Command Block FIFO-LIM (Bits 8B-11)} Value of FIFO 1 e Address and Length Threshold. Fields are part of the Transmit/Receive data Byte 8-9: buffers, including SRDY/ARDY | (Bit 6) Source Address (which 0 e SRDY/ARDY pin is not inserted by the operates as ARDY 82566). (internal PREAN- (Bits e Preamble Length synchronization). LEN 12-13) including Beginning of 1 SRDY/ARDY pin Frame indicator: operates as SRDY 00 - 2 bytes (external 01 - 4 bytes synchronization). 10 - 8 bytes SAV-BF (Bit 7) 11 - 16 bytes 0 Received bad INT-LPBCK | (Bit 14) Internal Loopback fr ames are not saved EXT-LPBCK | (Bit 15) External Loopback. in memory. NOTE: Bits 14 and 15 1 Received bad configured to 1, cause frames are saved in Internal Loopback. memory. ADD-LEN _ | (Bits 8-10)| Number of address Byte 10-11: byes. NOTE: 7 is LIN-PRIO | (Bits O-2)| Linear Priority interpreted as 0. ACR (Bits 4-6)| Accelerated Contention AL-LOC (Bit 11) Resolution (Exponential 0 Address and Length Priority) Fields separated BOF-MET _ | (Bit 7) Exponential Backoff from data and Method associated with 0 - IEEE 802.3/Ethernet Transmit Command Block or Receive Frame Descriptor. For transmitted Frame, Source Address is inserted by the 82586. 1 - Alternate Methodintel. 82586 INTER (Bits 8-15) | Number indicating CDOTF (Bits Collision Detect FRAME the Interframe 12-14 Filter in Bit Times SPACING Spacing in TxC CDT-SRC | (Bit 15) * Collision Detect period units. Source Byte 12-13: 9 * Externat 1 Internal SLOT- (Bits 0-7) | Slot Time Number, TIME (L) Low Byte Byte 16: SLT-TM (H) | (Bits 8-10) | Slot Time Number, MIN-FRM- | (Bits 0-7) | Minimum Number of High Bits Bytes in a Frame RETRY- (Bits Maximum Number of NUM 12-15) Transmission Retries on Collisions CONFIGURATION DEFAULTS Byte 14-15: . : The default values of the configuration parameters PRM (Bit 0) Promiscuous Mode are compatible with the IEEE 802.3/Ethernet Stan- BC-DIS (Bit 1) Broadcast Disable dards. RESET configures the 82586 according to MANCH/ (Bit 2) e Manchester or NRZ the defaults shown in Table 2. NRZ Encoding/Decoding 0 eNRZ Table 2. 82586 Default Values 1 * Manchester Preamble Length (Bytes) = 8 TONO-CRS | (Bit 3) Transmit on No Address Length (Bytes) = 6 0 camer Sense . Broadcast Disable = 0) * Cease Iransmission CRC-16/CRC-32 = 0 nore Foes Inactive No CRC insertion = 0 Transmission Bitstuffing/ EOC = 0 1 Continue Padding * 0 Transmission Even if Min-Frame-Length (Bytes) = 64 no Carrier Sense Interframe Spacing (Bits) = 96 NCRC-INS | (Bit 4) * No CRC insertion Slot Time (Bits) = 512 CRC-16 (Bit 5) CRC Type: Number of Retries = 15 0 32 bit Autodin Ii CRC Linear Priority = 0 Polynomial Accelerated Contention Resolution = 0 1 16 bit CCITT CRC Exponential Backoff Method = 0 Polynomial Manchester/NRZ = 0 BT-STF (Bit 6) Bitstuffing: Internal CRS = 0 0 End of Carrier Mode CRS Filter = 0 (Ethernet) Internal CDT = 0 1 HDLC like Bitstuffing CDT Filter = 0 Mode Transmit On No CRS = 0 PAD (Bit 7) Padding FIFO THRESHOLD = 8 0 * No Padding SRDY/ARDY = i) 1 * Perform Padding by Save Bad Frame = 0 Transmitting Flags Address/Length Location = 0 S Remainder of INT Loopback = 0 or EXT Loopback = 0 CRSF (Bits 8-9) { carer Sense Filter Promiscuous Mode _ 0 CRS-SRC | (Bit 11) Carrier Sense Source 0 @ External 1 e Internal. intel. 82586 15 ODD BYTE EVENBYTE 0 0 c | B]oK] a ZEROS (STATUS) i nun 4 : 2 a L 1. LINK OFFSET 4 rg FF MC-CNT 6 1 MC LIST 2ND BYTE \ 1ST BYTE ' McD ' NTH BYTE ADDITIONAL MC-IDS 231246-14 Figure 14. The MC-SETUP Command Block MC-SETUP This command sets up the 82586 with a set of Multi- cast Addresses. Subsequently, incoming frames with Destination Addresses from this set are accept- ed. - The MC-SETUP command includes the following fields: STATUS word (written by 82586): Cc (Bit 15) # Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) e Error Free Completion A (Bit 12) Command Aborted COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion I (Bit 13) interrupt After Completion CMD | (Bits0-2) | MC-SETUP = 3 LINK OFFSET: Address of next Command Block MC-CNT: A 14-bit field indicating the number of bytes in the MC-LIST field. MC-CNT is truncated to the nearest multiple of Address Length (in bytes). Issuing a MC-SETUP command with MC-CNT=0 disables reception of any incoming frame with a Mul- ticast Address. MC-LIST: A list of Multicast Addresses to be accept- ed by the 82586. Note that the most significant byte of an address is followed immediately by the least significant byte of the next address. Note also that the least significant bit of each Multicast Address in the set must be a one. The Transmit-Byte-Machine maintains a 64-bit HASH table used for checking Multicast Addresses during reception. An incoming frame is accepted if it has a Destination Address whose least significant bit is a one, and af- ter hashing points to a bit in the HASH table whose value is one. The hash function is selecting bits 2 to 7 of the CRC register. RESET causes the HASH ta- ble to become all zeros. After the Transmit-Byte-Machine reads a MC-SET- UP command from TX-FIFO, it clears the HASH ta- ble and reads the bytes in groups whose length is determined by the ADDRESS fength. Each group is hashed using CRC logic and the bit in the HASH table to which bits 2-7 of the CRC register point is set to one. A group that is not complete has no ef- fect on the HASH table. Transmit-Byte-Machine noti- fies CU after completion.intel. 82586 15 OOD BYTE EVENBYTE 0 T T T c | 8] oxt a o | sw | so | ss } s7 | ss] ss] o MAX COLL A. 4. 9 t t (STATUS) eafls |i EEE LEE SEZ CMD = 4 2 < A 1 (COMMAND) LINK OFFSET NEXT BD OFFSET : 2ND BYTE 1 1ST BYTE mc |e l DESTINATION ADDRESS A 4 NTH BYTE ' c LENGTH FIELD E 291246-15 Figure 15. The Transmit Command Block TRANSMIT s | (Bit) * Heart Beat, indicates that or during tnterframe we, aresmi command causes qransmission Spacing period after the (and if necessary retransmission) of a frame. previous transmission, a : on . pulse was detected on TRANSMIT CB includes the following fields: the Collision Detect pin. $5 (Bit 5) Transmission attempt STATUS word (written by 82586): stopped due to number of ; collisions exceeding the Cc (Bit 15) Command Completed maximum number of B (Bit 14) Busy Executing retries. Command MAX- | (Bits 3-0) | Number of Collisions OK (Bit 13) Error Free Completion COLL experienced by this A (Bit 12) Command Aborted frame. S5 = 1 and MAX- $10 (Bit 10) No Carrier Sense signal COLL = 0 indicates that during transmission there were 16 collisions. (between beginning of . Destination Address and COMMAND word: end of Frame Check EL (Bit 15) End of Command List Sequence). Ss (Bit 14) Suspend After S$9 (Bit 9) Transmission Completion unsuccessful (stopped) | (Bit 13) Interrupt After due to loss of Clear-to- Completion Send signal. CMD | (Bits0-2) | TRANSMIT = 4 $8 (Bit 8) Transmission successful (stopped due to DM ene ) LINK OFFSET: Address of next Command Block i.e. data not lied (e. cata cyte for TBD OFFSET: Address of list of buffers holding the transmission). information field. TBD-OFFSET = OFFFFH indi- $7 (Bit 7) Transmission had to cates that there is no Information field. Defer to traffic on the link. DESTINATION ADDRESS: Destination Address of the frame. LENGTH FIELD: Length field of the frame.intel. 82586 STATUS word: EOF @ Indicates that this is the Buffer Descriptor of the last buffer of this frames Information Field. Actual number of data bytes in buffer (can be ACT- | (Bits 0-13) COUNT even or odd). NEXT BD OFFSET: points to next Buffer Descriptor in list. If EOF is set, this field is meaningless. BUFFER ADDRESS: 24-bit absolute address of buffer. TIME DOMAIN REFLECTOMETER - TDR This command performs a Time Domain Reflectom- eter test on the serial link. By performing the com- mand, the user is able to identify shorts or opens and their location. Along with transmission of All Ones, the 82586 triggers an internal timer. The tim- er measures the time elapsed from transmission start until echo is obtained. Echo is indicated by Collision Detect going active or Carrier Sense signal drop. TDR command includes the following fields: STATUS word (written by 82586): c (Bit 15) * Command Completed B (Bit 14) * Busy Executing Command OK (Bit 13) Error Free Completion COMMAND word: EL (Bit 15) End of Command List $s (Bit 14) e Suspend After Completion lL (Bit 13) Interrupt After Completion CMD | (Bits0-2) | e TDR = 5 1 ODO BYTE EVEN BYTE 0 T T T T T T T T T T v EOF G ) ACT COUNT 0 L i i i. 1 i aL. 1 i i i i (STATUS) NEXT BO OFFSET 2 BUFFER ADDRESS a4 LALLA . 231246-16 Figure 16. The Transmit Buffer Description 18 ODD BYTE EVEN BYTE 0 c 8 OK A ZEROS 0 (STATUS) ' qv $s cCMD-=5 2 WLLL" come LINK OFFSET 4 wt [sar || SY re 231246-17 Figure 17. The TOR Command Blockintel. 82586 LINK OFFSET: Address of next Command Block RESULT word: LNK-OK _ |(Bit 15) @ No Link Problem Identified e Transceiver Cable Problem identified (valid only in the case of a Transceiver that does not return Carrier Sense during transmission). Open on the link identified (valid only in the case of a Transceiver that returns Carrier Sense during transmission). Short on the link identified (valid only in the case of a Transceiver that returns Carrier Sense during transmission). (Bits 0-10)| Specifying the distance to a problem on the link (if one exists) in transmit clock cycles. XCVR-PRB|(Bit 14) ET-OPN = |(Bit 13) ET-SRT (Bit 12) TIME DUMP This command causes the contents of over a hun- dred bytes of internal registers to be placed in mem- ory. It is supplied as a self diagnostic tool, as well as to supply registers of interest to the user. DUMP command includes the following fields: STATUS word (written by 82586): Cc (Bit 15) Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Completion COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion I (Bit 13) Interrupt After Completion CMD | (Bits 0-2) | e DUMP = 6 LINK OFFSET: Address of next Command Block BUFFER OFFSET: This word specifies the offset portion of the memory address which points to the top of the buffer allocated for the dumped registers contents. The length of the buffer is 170 bytes. DUMP AREA FORMAT Figure 18 shows the format of the DUMP area. The fields are as follows: Bytes 00H to OAH: These bytes correspond to the 82586 CONFIGURE command field. Bytes OCH to 11H: The Individual Address Register content. ARO is the Individual Address least signifi- cant byte. . Bytes 12H to 13H: Status word of last command block (only bits 0-13). 15 0 c B | OKI A ZEROS 0 (STATUS) EZ so <4 EL 8 1 EE woes , 7] 1 l (COMMAND) LINK OFFSET 4 BUFFER OFFSET 6 231246-18 Figure 18. The DUMP Command Block 1-21intel. 82586 Bytes 14H to 17H: Content of the Transmit CRC generator. TXCRCRO is the least significant byte. The contents are dependent on the activity before the DUMP command: After RESET - All Ones. After successful transmission - All Zeros. After MC-SETUP command - Generated CRC value of the last MC address, on MC-LIST. After unsuccessful transmission, depends on where it stopped. NOTE: For 16-bit CRC only TXCRCRO and TXCRCR1 are valid. $$ 14013:12:1710 9 6 7 6 $$ 4 3921 O ol o}olo] oo v tistrdofos INTERFRAME SPACING 1] IN oe 1 ferry T SLOT TIME (LOW) 08 in| S47} 00 MIN FRM LEN oA Ian oc 2 0E AR 4 10 olgjolo 6] COLL NUM 12 TXCACR 1 TXCACRO 4 TXCACA 3 TXCRCA2 16 AXCACR 1 RAXCACRO 18 AXCRCA 3 RXCRCR 2 1A TEMPR 1 TEMPRO 1c TEMPR 3 TEMPR 2 1E TEMPR 5S TEMPR 4 20 oy - se 22 HASHA 1 HASHR 3 MASHR 0 24 HASHR 2 26 HASHR 4G 28 HASHR 5 HASHR 7 tar 2c ryt ze HASHR 6 2a a 3x oyoyo 3E NXT AB SIZE 40 231246-19 1S 401312 11 10 8 8 7 6 5 4 3 2 1 6 NXT RB ADA (HIGH) NXT RB ADR (LOW) CUR RB SIZE LA ABO ADR NXT ABD ADR CUR ROO ADA CUR AB EBC NXT FO ADR CUR FO ADR TEMPORARY NXT TA CNT BUF ADR NXT TB ADA NXT TBO ADR LATBO ADR Dum cw CODE 9101 NXT CB ADR cB SCB AOR o ojo ojo o}o ololo BUF ADA PTR (HIGH) BUF ADA PRT (LOW) ACV OMA BC + BUF aDRA+H o,oj}o ACV OMA ADR H RCV DMA AORL Gea] oajo 9 a a 0 0 o o o o 0 58 Sa sc SE 60 $2 66 68 6A 6c 6E 70 72 4 16 7a TA 7 80 82 84 86 88 oA 3c 9 ao a2 aa as aes 231246-20 Figure 19. The DUMP Area 1-22intel. 82586 Bytes 18H to 1BH: Contents of Receive CRC Checker. RXCRCRO is the feast significant byte. The contents are dependent on the activity per- formed before the DUMP command: After RESET - All Ones. After good frame reception 1. For CRC-CCITT - OIDOFH 2. For CRC-Autodin-ll - C704DD7BH After Bad Frame reception - corresponds to the re- ceived information. After reception attempt, i.e. unsuccessful check for address match, corresponds to the CRC performed on the frame address. NOTE: Any frame on the serial link modifies this register contents. Bytes 1CH to 21H: Temporary Registers. Bytes 22H to 23H: Receive Status Register. Bits 6, 7, 8, 10, 11 and 13 assume the same meaning as corresponding bits in the Receive Frame Descriptor Status field. Bytes 24H to 2BH: HASH TABLE. Bytes 2CH to 2DH: Status bits of the last tine TDR command that was performed. NXT-RB-SIZE: Let N be the last buffer of the last received frame, then NXT-RB-SIZE is the number of bytes of available in the N + 1 buffer. EL - The EL bit of the Receive Buffer Descriptor. NXT-RB-ADR: Let N be the last Receive Buffer used, then NXT-RB-ADR is the BUFFER-ADDRESS field in the N + 1 Receive-Buffer Descriptor, i.e. the pointer to the N + 1 Receive Buffer. CUR-RB-SIZE: The number of bytes in the jast buft- er of the last received frame. EL - The EL bit of the last buffer in the last received frame. LA-RBD-ADR: Look Ahead Buffer Descriptor, i.e. the pointer to N + 2 Receiver Buffer Descriptor. NXT-RBD-ADR: Next Receive Buffer Descriptor Ad- dress. Similar to LA-RBD-ADR but points to N + 1 Receive Buffer Descriptor. CUR-RBD-ADR: Current Receive Buffer Descriptor Address. Similar to LA-RBD-ADR, but point to Nth Receive Buffer Descriptor. 1-23 CUR-RB-EBC: Current Receive Buffer Empty Byte Count Let N be the currently used Receive Buffer. Then CUR-RB-EBC indicates the Empty part of the buffer, i.e. the ACT-COUNT of buffer N is given by the difference between its SIZE and the CUR-RB- EBC. NXT-FD-ADR: Next Frame Descriptor Address. De- fine N as the last Receive Frame Descriptor with bits C = 1 andB = 0, then NXT-FD-ADR is the address of N + 2 Receive Frame Descriptor (with B = C = 0) and is equal to the LINK-ADDRESS field in N + 1 Receive Frame Descriptor. CUR-FD-ADR: Current Frame Descriptor Address. Similar to next NXT-FD-ADR but refers to N + 1 Receive Frame Descriptor (with B = 1, C = 0). Bytes 54H to 55H: Temporary register. NXT-TB-CNT: Next Transmit Buffer Count. Let N be the last transmitted buffer of the TRANSMIT com- mand executed recently, the NXT-TB-CNT is the ACT-COUNT field in the Nth Transmit Buffer De- scriptor. EOF - Corresponds to the EOF bit of the Nth Transmit Buffer Descriptor. EOF = 1 indicates that the last buffer accessed by the 82586 during Transmit was the last Transmit Buffer in the data buffer chain associated with the Transmit Com- mand. BUF-ADR: Buffer Address. The BUF-PTR field in the DUMP-STATUS Command Block. NXT-TB-AD-L: Next Transmit Buffer Address Low. Let N be the last Transmit Buffer in the transmit buff- er chain of the TRANSMIT Command performed recently, then NXT-TB-AD-L are the two least signifi- cant bytes of the Nth buffer address. LA-TB-ADR: Look Ahead Transmit Buffer Descrip- tor Address. Let N be the last Transmit Buffer in the transmit buffer chain of the TRANSMIT Command performed recently, then LA-TBD-ADR is the NEXT- BD-ADDRESS field of the Nth Buffer Descriptor. NXT-TBD-ADR: Next Transmit Buffer Descriptor Address. Similar in function to LA-TBD-ADR but re- lated to Transmit Buffer Descriptor N-1. Actually, it is the address of Transmit Buffer Descriptor N. Bytes 60H, 61H: This is a copy of the 2nd word in the DUMP-STATUS command presently executing. NXT-CB-ADR: Next Command Block Address. The LINK-ADDRESS field in the DUMP Command Block presently executing. Points to the next command. CUR-CB-ADR: Current Command Block Address. The address of the DUMP Command Block currently executing.intel. 82586 SCB-ADR: Offset of the System Control Block (SCB). Bytes 7EH, 7FH: RU-SUS-RQ (Bit 4) - Receive Unit Suspend Re- quest. Bytes 80H, 81H: CU-SUS-RQ (Bit 4) - Command Unit Suspend Re- quest. END-OF-CBL (Bit 5) - End of Command Block List. If 1"" indicates that DUMP-STATUS is the last com- mand in the command chain. ABRT-IN-PROG (Bit 6) - Command Unit Abort Re- quest. RU-SUS-FD (Bit 12) - Receive Unit Suspend Frame Descriptor Bit. Assume N is the Receive Frame De- scriptor used recently, then RU-SUS-FD is equiva- lent to the S bit of N + 1 Receive Frame Descriptor. Bytes 82H, 83H: RU-SUS (Bit 4) - Receive Unit in SUSPENDED state. RU-NRSRC (Bit 5) - Receive Unit in NO RESOURC- ES state. . RU-RDY (Bit 6) - Receive Unit in READY state. RU-IDL (Bit 7) - Receive Unit in IDLE state. RNR (Bit 12) - RNR Interrupt in Service bit. CNA (Bit 13) - CNA Interrupt in Service bit. FR (Bit 14) - FR Interrupt in Service bit. CX (Bit 15) - CX Interrupt in Service bit. Bytes 90H to 93H: BUF-ADR-PTR - Buffer pointer is the absolute ad- dress of the bytes following the DUMP Command block. Bytes 94H to 95H: RCV-DMA-BC - Receive DMA Byte Count. This field contains number of bytes to be transferred during the next Receive DMA operation. The value de- pends on AL-LOCation configuration bit. 1-24 1. lf AL-LOCation = 0 then RCV-DMA-BC = (2 times ADDR-LEN plus 2) if the next Receive Frame Descriptor has already been fetched. . If AL-LOCation 1 then it contains the size of the next Receive Buffer. BR+ BUFPTR+ 96H - Sum of Base Address plus BUF PTR field and 96H. RCV-DMA-ADR - Receive DMA absolute Address. This is the next RCV-DMA start address. The value depends on AL-LOCation configuration bit. 1. If AL-LOCation = 0, then RCV-DMA-ADR is the Destination Address field located in the next Re- ceive Frame Descriptor. . If AL-LOCation = 1, then RCV-DMA-ADR is the next Receive Data Buffer Address. The following nomenclature has been used in the DUMP table: 0 * The 82586 writes zero in this location. 1 The 82586 writes one in this location. x * The 82586 writes zero or one in this location. 41 The 82586 copies this location from the corresponding position in the memory structure. DIAGNOSE The DIAGNOSE Command triggers an internal self test procedure of backoff related registers and coun- ters. The DIAGNOSE command includes the following: STATUS word (written by 82586): Cc (Bit 15) Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Completion FAIL | (Bit 11) Indicates that the Self Test Procedured Failed COMMAND word: Et (Bit 15) End of Command List $s (Bit 14) Suspend After Completion | (Bit 13) Interrupt After Completion CMD | (Bits0-2) | * DIAGNOSE = 7 LINK OFFSET: Address of next Command Block.intel. 82586 18 0 c B | ox] a ] FAL ZEROS 0 : ' (STATUS) els |i LEED LEE. CMD =7 2 < 1 1 (COMMAND) LINK OFFSET 4 231246-21 Figure 20. The DIAGNOSE Command Block Lie | RFA POINTE! STATISTICS To COMMAND BLOCK LIST b<$ RECEIVE FRAME AREA RFD 1 ' 1 STATUS [OT] STATUS STATUS status po ' ' 4 4! J RECEIVE 1 1 FRAME ' ' DESCRIPTORS ' ' ' EMPTY EMPTY EMPTY ! : RBD2 \ RBO 3 RBD4 ABD S ' 1] act-nt [1 o | AcT-ent 0 | ACT-cnt 0 | ACT-cnt | = 4 wee ft Et DESCRIPTORS = j 1 i t ' t f] 1 ' iy ' RECEIVE ' VALID VALID | | BUFFERS \ DATA DATA| | BUFFER 1 BUFFER 2 BUFFER 3 BUFFER 4 BUFFER 5 RECEIVE FRAME LIST el<~_ FREEFRAMELIST }39 -> i 231246-22 Figure 21. The Receive Frame Area RECEIVE FRAME AREA (RFA) FRAME DESCRIPTOR (FD) FORMAT The Receive Frame Area, RFA, is prepared by the The FD includes the following fields: host CPU, data is placed into the RFA by the 82586 as frames are received. RFA consists of a list of Receive Frame Descriptors (FD), each of which is STATUS word (set by the 82586): associated with a frame. RFA-OFFSET field of SCB Cc (Bit 15) * Completed Storing points to the first FD of the chain; the last FD is Frame. identified by the End-of-Listing flag (EL). See Figure B (Bit 14) FD was Consumed by 21. RU. 1-25intel. 82586 1% ODO BYTE EVEN BYTE @ c 8 | ox] o | si} sw] so | se | s7 ] s ZEROS 0 (STATUS) a. _ LiNK OFFSET 4 ABD-OFFSET 6 2N0 BYTE 1ST BYTE wc Is DESTINATION ADDRESS 10 NTH BYTE 2 2N0 BYTE 1ST BYTE SOURCE ADDRESS 6 NTH BYTE 8 2N0 BYTE LENGTH FIELD 1ST BYTE 20 231246-23 Figure 22. The Frame Descriptor (FD) Format OK (Bit 13) Frame received LINK OFFSET: Address of next FD in list. successfully. If this bit is - fini ; st hen al oer wilde | ee eee coy a t; if itis reset, then y pda y . : s the: th: bit ili dicat RBD that represents the information Field. RBD- e other bits wil Indicate OFFSET = OFFFFH means there is no Information the nature of the error. Field S11 (Bit 11) Received Frame , Experienced CRC Error. DESTINATION ADDRESS (written by 82586): S10 | (Bit10) | Received Frame Contains Destination Address of received frame. Experienced an The length in bytes, it is determined by the Address Alignment Error. Length configuration parameter. sg (Bit 9) e RU ran out of resources during reception of this SOURCE ADDRESS (written by 82586): Contains frame. Source Address of received frame. Its length is the $8 (Bit 8) @ RCV-DMA Overrun. same as DESTINATION ADDRESS. S7 (Bit 7) Received frame had fewer bits than LENGTH FIELD (written by 82586): Contains the 2 configured Minimum byte Length or Type Field of received frame. Frame Length. s (Bit 6) No EOF flag detected (only when configured to RECEIVE BUFFER DESCRIPTOR Bitstuffing). FORMAT The Receive Buffer Descriptor (RBD) holds informa- COMMAND word: tion about a buffer; size and location, and the means for forming a chain of RBDs, (forward pointer and EL (Bit 15) Last FD in the List. end-of-frame indication). iS) (Bit 14) RU should be suspended after receiving this frame. The Buffer Descriptor contains the following fields. 1-2682586 EOF F T T T v ACT COUNT ah. L a= =a 4 4 0 1 1 (STATUS) NEXT BD OFFSET 2 BUFFER ADDRESS A23 a 4 ll SIZE 231246-24 Figure 23. The Receive Buffer Descriptor (RBD) Format STATUS word (written by the 82586). EOF (Bit 15) F (Bit 14) ACT (Bits 0-13) COUNT Last buffer in received frame. ACT COUNT field is valid. Number of bytes in the buffer that are actuaily occupied. NEXT RBD OFFSET: Address of next BD in list of BDs. 1-27 BUFFER ADDRESS: 24-bit absolute address of buffer. EL/SIZE: EL (BIT 15) Last BD in list. SIZE | (Bits 0-13) | Number of bytes the buffer is capable of holding.intel. 82586 ABSOLUTE MAXIMUM RATINGS* eee 0C to 70C 68C to 150C Ambient Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground 1.0V to +7V Power Dissipation....................05 3.0 Watts D.C. CHARACTERISTICS NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Siressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Ta = OC to 70C, Te = 0C to 105C, Vog = 5V +10%, CLK has MOS levels (See Vii, Vain: VMoL: Vow). TxC and RxC have 82C501 compatible levels (Vit, VriH, VRIH)- All other signals have TTL levels (see Vic Vins VoL, OH): Symbol Parameter Min Max Units Test Conditions ViL Input Low Voltage (TTL) -0.5 +0.8 Vv Vin Input High Voltage (TTL) 2.0 Voc + 0.5 Vv VoL Output Low Voltage (TTL) 0.45 Vv lol = 2.5mA Von Output High Voltage (TTL) 2.4 Vv lon 400 pA VMIL Input Low Voltage (MOS) -0.5 0.6 Vv VMIH Input High Voltage (MOS) 3.9 Voc + 0.5 Vv VrIH Input High Voltage (TxC) 3.3 Veco + 0.5 V Vain Input High Voltage (RxC) 3.0 Voc + 0.5 Vv VMOL Output Low Voltage (MOS) 0.45 Vv lo, 2.5 mA VMOH Output High Voltage (MOS) Voc 0.5 Vv lon 400 pA tu input Leakage Current +10 pA 0<Vin< Voc ILo Output Leakage Current +10 pA 0.45 < Vout s Vcc Cin Capacitance of Input Buffer 10 pF FC = 1 MHz Cout Capacitance of Output Buffer 20 pF FC = 1 MHz loc Power Supply Current 550 mA Ta = 0C 450 Ta = 70C 1-28intel. 82586 SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS Ta = 0C to 70C, Tc = 0C to 105C, Voc = SV + 10%. Figures 24 and 25 define how the measurements should be done. INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS 2.4 15 TEST POINTS ts 0.45: 231246-25 AC Testing Inputs are Driven at 2.4V for a Logic 1 and 0.45 for a Logic 0. Timing measurements are made at 1.5V for both a Logic 1 and 0 Figure 24. TTL tnput/Output Voltage Levels for Timing Measurements 7? HIGH LEVEL MAY VARY WITH VCC 231246-26 MOS I/O measurements are taken at 0.1 and 0.9 of the voitage swing Figure 25. System Clock CMOS Input Voltage Leveis for Timing Measurements 1-29intel. 82586 INPUT TIMING REQUIREMENTS* 82586-6 82586 82586-10 Symbol Parameter (6 MHz) (8 MHz) (10 MHz) Comments Min | Max | Min | Max ; Min Max T1 CLK Cycle Period 166 | 2000 | 125 | 2000] 100 200 T2 CLK Low Time at 1.5V 73 | 1000 | 55 | 1000] 44 1000 T3 CLK Low Time at 0.9V 42.5 | 1000 | 42.5 | 1000 T4 CLK High Time at 1.5V 73 55 44 T5 CLK High Time at 3.6V 42.5 42.5 T CLK Rise Time 15 16 12 Note 1 17 CLK Fall Time 15 15 12 Note 2 T8 Data in Setup Time 20 20 15 T9 Data in Hold Time 10 10 10 T10 Async RDY Active Setup Time 20 20 15 Note 3 Ti Async RDY Inactive Setup Time 35 ' 35 25 Note 3 T12 Asynec RDY Hold Time 15 15 15 Note 3 T13 Synchronous Ready/Active Setup | 35 35 20 T14 Synchronous Ready Hold Time 0 0 0 T15 HLDA Setup Time 20 20 20 Note 3 T16 HLDA Hold Time 10 10 5 Note 3 T17 Reset Setup Time 20 20 20 Note 3 T18 Reset Hold Time 10 10 10 Note 3 T19 CA Pulse Width 171 171 171 T20 CA Setup Time 20 20 20 Note 3 T21 CA Hold Time 10 10 10 Note 3 OUTPUT TIMINGS** Symbol Parameter Min | Max | Min | Max | Min | Max | Comments T22 DT/R Valid Delay 0 60 0 60 0 44 T23 WR, DEN Active Delay 0 70 0 70 0 56 T24 WR, DEN Inactive Delay 10 65 10 65 10 45 T25 Int. Active Delay 0 85 0 85 0 70 Note 4 T26 Int. Inactive Delay 0 85 0 85 0 70 Note 4 T27 Hold Active Delay 0 85 0 85 0 70 Note 4 T28 Hold inactive Delay 0 85 0 85 0 70 Note 4 T29 Address Valid Delay 0 55 0 55 0 50 T30 Address Float Delay 0 50 0 50 12 50 T31 Data Valid Delay 0 55 0 55 50 Note 7 T32 Data Hold Time 0 0 T33 Status Active Deiay 10 60 10 60 10 45 1-30intel. 82586 OUTPUT TIMINGS** (Continued) 82582-6 82586 82586-10 Symbol Parameter (6 MHz) (8 MHz) (10 MHz) Comments Min Max Min Max Min Max T34 Status Inactive Delay 10 70 10 70 10 50 Note 8 T35 ALE Active Delay 0 46 0 45 0 35 Note 5 T36 ALE Inactive Delay 0 45 0 45 0 37 Note 5 T37 ALE Width T2-10 T2-10 T2-10 Note 5 T38 Address Valid to ALE Low T2-40 T2-30 T2~-25 T39 Address Hold to ALE Inactive | T4-10 T4-10 T4-10 T40 RD Active Delay 10 95 10 95 10 95 T41 RD Inactive Delay 10 70 10 70 10 70 T42 RD Width 2T1-50 2T1-50 271-46 T43 Address Fioat to RD Active 10 10 0 T44 RD Inactive to Address Active | 71-40 T1-40 T1-34 T45 WR Width 271-40 271-40 271-34 T46 Data Hold After WR T2-25 T2-25 T2-25 T47 Control Inactive After Reset 0 60 0 60 0 60 Note 6 *All units are in ns. **CL on all outputs is 20-200 pF unless otherwise specified. NOTES: 1. 1.0V to 3.5V 6. Affects: oe _ 2. 3.5V to 1.0V MIN MODE: RD, WR, DT/R, DEN 3. To guarantee recognition at next clock MAX MODE: SO, S1 4. CL = 50 pF 7. High address lines (A16-A24, BHE) become valid one 5. CL = 100 pF clock before T1 only on first memory cycle after the 82586 acquired the bus. 8. S1, SO go inactive just prior to T4. 231246-27 _ N 231246-28 Figure 26. INT Output Timing Figure 27. CA Input Timing CLK j T7 RESET | fi6. WR. DEN. OVA. 1 TN 231246-29 Figure 28. RESET Timing 1-3182586 READY SIGNAL TH LA, SROY OR. VALID READY 82586 INPUTS - 231246-30 Figure 29. ARDY and SRDY Timings Relative to CLK LK RMN oud te te te hen l 27 728 HLDA Q ; Ue te wiirty 2 ~ Ts Tie} OT, ea wneren $a eR} 231246-31 Figure 30. HOLD/HLDA Timing Relative to CLK 1-3282586 "1 T2 3 v4 BHE a16-a18 A19/S6 ADO-ADIS DATA IN RD Ta 231246-32 Figure 31. Read Cycle Timing v1 Ts Tw BHE a16-a18 A19/S6 ADO-AD15 DATA OUT T45 231246-33 Figure 32. Write Cycle Timing 1-33intel. 82586 SERIAL INTERFACE A.C. TIMING CHARACTERISTICS for Manchester: f min = 500 kHz + 100 ppm f max = 10 MHz + 100 ppm CLOCK SPECIFICATION Applies for TxC, RxC for NRZ: f min = 100 kHz + 100 ppm f max = 10 MHz + 100 ppm A.C. CHARACTERISTICS 1 , 152 = +5% 751, T 2 5% TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION* for Manchester, symmetry is needed: Symbol | Parameter Min | Max Comments TRANSMIT CLOCK PARAMETERS T48 TxC Cycle 100 1000 Notes 14, 2 T48 TxC Cycle 100 Notes 14,3 T49 TxC Rise Time 5 Note 14 T50 TxC Fall Time 5 Note 14 T51 TxC High Time @ 3.0V 40 1000 Note 14 T52 TxC Low Time @0.9V 40 Notes 14, 4 TRANSMIT DATA PARAMETERS T53 TxD Rise Time 10 Notes 5, 13 754 TxD Fall Time 10 Notes 5, 13 T55 TxD Transition-Transition Min (T51, Notes 2,5 T52) 7 T56 TxC Low to TxD Valid 40 Notes 3, 5 T57 TxC Low to TxD Transition 30 Notes 2, 5 T58 TxC High to TxD Transition 30 Notes 2, 5 T9 TxC Low to TxD High at the Transmission End 40 Note 5 REQUEST TO SEND/CLEAR TO SEND PARAMETERS T0 TxC Low to RTS Low. Time to Activate RTS 40 Note 6 T61 CTS Valid to TxC Low. CTS Setup Time 45 T2 TxC Low to CTS Invalid. CTS Hold Time 20 Note 7 T63 TxC Low to RTS High, time to Deactivate ATS 40 Note 6 RECEIVE CLOCK PARAMETERS T64 RxC Clock Cycle 100 Notes 15, 3 T65 RXxC Rise Time 5 Note 15 T66 RxC Fail Time 5 Note 15 T67 RxC High Time @ 2.7V 36 1000 Note 15 T68 RxC Low Time @0.9V 40 Note 15 *Alt units are in ns. 1-34intel. 82586 A.C. CHARACTERISTICS (Continued) TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION* (Continued) Symbol | Parameter | Min | Max Comments RECE!IVE DATA PARAMETERS , T69 RxD Setup Time 30 Note 1 T70 RxD Hold Time 30 Note 1 T71 RxD Rise Time 10 Note 1 T72 RxD Fail Time 10 Note 1 CARRIER SENSE/COLLISION DETECT PARAMETERS 1 T73 CDT Valid to TxC High Ext. Collision 30 Note 12 Detect Setup Time 174 TxC High to CDT Inactive. CDT Hoid Time 20 Note 12 T75 CDT Low to Jamming Start Note 8 T76 CRS Valid to TxC High Ext. Carrier Sense Setup Time 30 Note 12 177 TxC High to CRS Inactive. CRS Hold Time 20 Note 12 178 CRS Low to Jamming Start Note 9 T79 Jamming Period Note 10 T80 CRS Inactive Setup Time to RxC High 60 End of Receive Frame 781 CRS Active Hold Time from RxC High 3 INTERFRAME SPACING PARAMETER T82 Inter Frame Delay | | Note 11 *All units are in ns. NOTES: . TTL levels Manchester only . NRZ only Manchester requires 50% duty cycle 1 TTL load + 50 pF 1 TTL load + 100 pF _ . Abnormal end of transmission. CTS expires before RTS . Programmable value: T75 = NCDF x T48 + (12.5 to 23.5) x T48 if collision occurs after preamble NCDFThe collision detection filter configuration value 9. Programmable value: T78 = NCSF x T48 + (12.5 to 23.5) x T48 NCSFThe carrier sense filter configuration value TBD is a function of internal/external carrier sense bit 10.779 = 32 x T48 11. Programmable value: T82 = NIFS x T48 NIFSthe IFS configuration value *12. To guarantee recognition on the next clock 13. Applies to TTL levels 14. 82C501 compatible levels, see Figure 34 15. 82C501 compatible levels, see Figure 35 PNAAAWN 1-35intel. 82586 A.C. TIMING CHARACTERISTICS input and Output Waveforms for AC Tests 2.4 Ws TEST POINTS 18 0.48 231246-34 AC testing inputs are driven at 2.4V for a Logic 1 and 0.45 for a Logic 0. Timing measurements are made at 1.5V for both a Logic 1 and 0. Figure 33. TTL input/Output Voltage Levels for Timing Measurements HIGH LEVELS MAY VARY WITH Voge 231246-35 Figure 34. Tx Input Voltage Levels for Timing Measurements HIGH LEVELS MAY VARY WITH Vog 231246-36 Figure 35. RxC Input Voltage Levels for Timing Measurements * 1-3682586 ae EO a a sr Tag aa { Ts 182 on : Taz ~04 be I CT _ ar hei on -- oa ape _ay AK-- ome KPT 1" se . umneneartn ~~ K] OO KY a aT ls Ts3 Ts4 231246-37 pS \h Y/N THE MEH YY EDS mrs ---_/|\ m____|-__---_1. \ -- cot =| Tr3 __ - 7. Fin ms CRS. Ve ee TN eM VS I T55 XK AY NI NS (MANCHESTER) 231246-38 Figure 36. Transmit and Control and Data Timing Fat Ts j~ T67 RxD 169 _> > T70 231246-39 Figure 37. RxD Timing Relative to RxC ae | ons _. T80 Ta 231246-40 Figure 38. CRS Timing Relative to RxC 1-37