Low Voltage Supervisory Circuits with
Watchdog and Manual Reset in 5-Lead SOT-23
Data Sheet
ADM6823/ADM6824/ADM6825
Rev. B Document Feedback
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FEATURES
Precision low voltage monitoring
9 reset threshold options: 1.58 V to 4.63 V
140 ms (minimum) reset timeout
Watchdog timer with 1.6 sec timeout
Manual reset input
Reset output stages
Push-pull active-low
Open-drain active-low
Push-pull active-high
Low power consumption: 7 µA
Guaranteed reset output valid to VCC = 1 V
Power supply glitch immunity
Specified from −40°C to +125°C
5-lead SOT-23 package
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
FUNCTIONAL BLOCK DIAGRAM
ADM6823
V
CC
V
CC
MR
GND WDI
RESET
RESET
GENERATOR
WATCHDOG
DETECTOR
DEBOUNCE
V
REF
04535-001
Figure 1.
GENERAL DESCRIPTION
The ADM6823/ADM6824/ADM6825 are supervisory circuits
that monitor power supply voltage levels and code execution
integrity in microprocessor-based systems. As well as providing
power-on reset signals, an on-chip watchdog timer can reset
the microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by means of an
external push-button through a manual reset input. The parts
feature different combinations of watchdog input and manual
reset input and output stage configurations, as shown in Table 1.
Each part is available in nine reset threshold options, ranging
from 1.58 V to 4.63 V. The reset and watchdog timeout periods
are fixed at 140 ms (minimum) and 1.6 sec (typical),
respectively.
The ADM6823/ADM6824/ADM6825 are available in 5-lead
SOT-23 packages and typically consume only 7 µA, making
them suitable for use in low power, portable applications.
Table 1. Selection Table
Part No.
Watchdog
Timer
Manual
Reset
Output Stage
RESET
ADM6823 Yes Yes Push-Pull
ADM6824 Yes Push-Pull Push-Pull
ADM6825
Yes
Push-Pull
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Reset Output ..................................................................................9
Manual Reset Input .......................................................................9
Watchdog Input .............................................................................9
Application Information ................................................................ 10
Watchd og Input Current ........................................................... 10
Negative-Going VCC Transients ................................................ 10
Ensuring Reset Valid to VCC = 0 V ........................................... 10
Watchdog Software Considerations ......................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 12
REVISION HISTORY
2/13—Rev. A to Rev. B
Updated Outline Dimensions ...................................................... 11
Changes to Ordering Guide .......................................................... 12
Deleted Automotive Products Section ......................................... 12
9/12—Rev. 0 to Rev. A
Removed ADM6821/ADM6822 (Throughout) ........................... 1
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
Added Automotive Products Section........................................... 11
6/05—Revision 0: Initial Version
Data Sheet ADM6823/ADM6824/ADM6825
Rev. B | Page 3 of 12
SPECIFICATIONS
VCC = 4.5 V to 5.5 V for ADM682xL/ADM682xM; VCC = 2.7 V to 3.6 V for ADM682xT/ADM682xS/ADM682xR; VCC = 2.1 V to 2.75 V
for ADM682xZ/ADM682xY; VCC = 1.53 V to 2.0 V for ADM682xW/ADM682xV; TA = –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range 1 5.5 V
Supply Current 10 20 µA WDI and MR unconnected, VCC = 5.5 V
7 16 µA WDI and MR unconnected, VCC = 3.6 V
RESET THRESHOLD VOLTAGE
ADM682xL 4.50 4.63 4.75 V
ADM682xM 4.25 4.38 4.50 V
ADM682xT 3.00 3.08 3.15 V
ADM682xS
2.85
2.93
3.00
V
ADM682xR 2.55 2.63 2.70 V
ADM682xZ 2.25 2.32 2.38 V
ADM682xY 2.12 2.19 2.25 V
ADM682xW 1.62 1.67 1.71 V
ADM682xV 1.52 1.58 1.62 V
RESET THRESHOLD TEMPERATURE COEFFICIENT 60 ppm/°C
RESET THRESHOLD HYSTERESIS 2 × VTH mV
VCC TO RESET DELAY 20 µs VTH − VCC = 100 mV
RESET TIMEOUT PERIOD 140 200 280 ms
RESET OUTPUT VOLTAGE
VOL (Push-Pull or Open-Drain) 0.3 V VCC ≥ 1 V, ISINK = 50 µA
0.3 V VCC ≥ 1.2 V, ISINK = 100 µA
0.3 V VCC ≥ 2.55 V, ISINK = 1.2 mA
0.4 V VCC ≥ 4.25 V, ISINK = 3.2 mA
VOH (Push-Pull Only) 0.8 × VCC V VCC ≥ 1.8 V, ISOURCE = 200 µA
0.8 × VCC V VCC ≥ 3.15 V, ISOURCE = 500 µA
0.8 × V
CC
V
V
CC
≥ 4.75 V, I
SOURCE
= 800 µA
RESET OUTPUT LEAKAGE CURRENT (OPEN-
DRAIN ONLY)
1 µA RESET not asserted
RESET OUTPUT VOLTAGE (PUSH-PULL ONLY)
VOH 0.8 × VCC V VCC ≥ 1 V, ISOURCE = 1 µA
0.8 × VCC V VCC ≥ 1.5 V, ISOURCE = 100 µA
0.8 × VCC V VCC ≥ 2.55 V, ISOURCE = 500 µA
0.8 × VCC V VCC ≥ 4.25 V, ISOURCE = 800 µA
VOL 0.3 V VCC ≥ 1.8 V, ISINK = 500 µA
0.3 V VCC ≥ 3.15 V, ISINK = 1.2 mA
0.4 V VCC ≥ 4.75 V, ISINK = 3.2 mA
MANUAL RESET INPUT (ADM6823/ADM6825)
MR Input Threshold
VIL 0.3 × VCC V
VIH 0.7 × VCC V
MR
Input Pulse Width
1
µs
MR Glitch Rejection 100 ns
MR to Reset Delay 200 ns
MR Pull-Up Resistance 25 50 75 kΩ
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 4 of 12
Parameter Min Typ Max Unit Test Conditions/Comments
WATCHDOG INPUT (ADM6823/ADM6824)
Watchdog Timeout Period 1.12 1.6 2.40 sec
WDI Pulse Width 50 ns
WDI Input Threshold
V
IL
0.3 × V
CC
V
VIH 0.7 × VCC V
WDI Input Current 120 160 µA VWDI = VCC
−20 −15 µA VWDI = 0
Data Sheet ADM6823/ADM6824/ADM6825
Rev. B | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC −0.3 V to +6 V
Output Current (RESET, RESET) 20 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance 170°C/W
Soldering Temperature
Sn/Pb 240°C, 30 sec
RoHS Compliant
260°C, 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM6823
TOP VI EW
(No t t o Scale)
RESET 1
GND 2
MR 3
VCC
WDI
5
4
04535-003
Figure 2. ADM6823 Pin Configuration
ADM6824
TOP VIEW
(Not to Scale)
RESET
1
GND
2
RESET
3
V
CC
WDI
5
4
04535-004
Figure 3. ADM6824 Pin Configuration
ADM6825
TOP VIEW
(Not to Scale)
RESET
1
GND
2
RESET
3
V
CC
MR
5
4
04535-005
Figure 4. ADM6825 Pin Configuration
Table 4. Pin Function Descriptions
Pin No
ADM6823 ADM6824 ADM6825 Mnemonic Description
1 1 1 RESET Active-Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH.
Push-Pull Output Stage for the ADM6823/ADM6824/ADM6825.
2 2 2 GND Ground.
3 MR Manual Reset Input. This is an active-low input, which, when forced low for at least
1 µs, generates a reset. It features a 50 kΩ internal pull-up.
3 3 RESET Active-High Push-Pull Reset Output.
4 4 WDI Watchdog Input. Generates a reset if the voltage on the pin remains low or high for
the duration of the watchdog timeout. The timer is cleared if a logic transition occurs
on this pin or if a reset is generated.
4 MR Manual Reset Input.
5 5 5 VCC Power Supply Voltage Being Monitored.
Data Sheet ADM6823/ADM6824/ADM6825
Rev. B | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
04535-006
TEMPERATURE (°C) 120–40 –20 0 20 40 60 80 100
I
CC
(µA)
10.0
9.5
7.5
7.0
6.5
9.0
8.5
8.0
6.0
5.5
5.0
4.5
4.0
3.5
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 1.5V
Figure 5. Supply Current vs. Temperature
04535-007
TEMPERATURE (°C) 120–40 0–20 4020 1008060
NORMALIZED RESET TIMEOUT
1.20
1.15
1.10
1.05
0.95
1.00
0.90
0.85
0.80
Figure 6. Normalized RESET Timeout Period vs. Temperature
04535-008
TEMPERATURE (°C) 120–40 0–20 4020 1008060
VCC TO RESET DELAY (µs)
100
90
80
60
70
40
50
20
10
30
0
Figure 7. VCC to RESET Output Delay vs. Temperature
04535-009
TEMPERATURE (°C)120
–40 0
–20 40
20 1008060
NORMALIZED WATCHDOG TIMEOUT
1.20
1.15
1.10
1.05
1.00
0.95
0.90
Figure 8. Normalized Watchdog Timeout Period vs. Temperature
04535-010
TEMPERATURE (°C) 120–40 0–20 4020 1008060
NORMALIZED RESET THRESHOLD
1.05
1.03
1.04
1.01
1.02
0.99
1.00
0.97
0.98
0.95
0.96
Figure 9. Normalized RESET Threshold vs. Temperature
04535-011
RESET THRESHOLD OVERDRIVE (mV) 100010 100
MAXIMUM V
CC
TRANS IENT DURATION (µs)
160
120
140
100
60
80
20
40
0
V
CC
= 4.63V
V
CC
= 2.93V
Figure 10. Maximum VCC Transient Duration vs. RESET Threshold Overdrive
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 8 of 12
04535-017
I
SINK
(mA) 70 123456
V
OUT
(V)
0.20
0.15
0.10
0.05
0
V
CC
= 2.9V
Figure 11. Voltage Output Low vs. ISINK
04535-018
I
SOURCE
(mA) 1.00 0.2 0.4 0.6 0.8
V
OUT
(V)
2.92
2.90
2.88
2.86
2.84
2.82
V
CC
= 2.9V
Figure 12. Voltage Output High vs. ISOURCE
Data Sheet ADM6823/ADM6824/ADM6825
Rev. B | Page 9 of 12
THEORY OF OPERATION
The ADM6823/ADM6824/ADM6825 provide microprocessor
supply voltage supervision by controlling the microprocessor’s
reset input. Code execution errors are avoided during power-
up, power-down, and brownout conditions by asserting a reset
signal when the supply voltage is below a preset threshold. In
addition, the ADM6823/ADM6824/ADM6825 allow supply
voltage stabilization with a fixed timeout before the reset
deasserts after the supply voltage rises above the threshold.
Problems with microprocessor code execution can be moni-
tored and corrected with a watchdog timer (ADM6823/
ADM6824). When watchdog strobe instructions are included
in microprocessor code, a watchdog timer detects if the micro-
processor code breaks down or becomes stuck in an infinite
loop. If this happens, the watchdog timer asserts a reset pulse,
which restarts the microprocessor in a known state.
If the user detects a problem with the system’s operation, a
manual reset input is available (ADM6823/ADM6825) to reset
the microprocessor by means of an external push-button, for
example.
RESET OUTPUT
The ADM6823 features an active-low push-pull output. The
ADM6824/ADM6825 feature dual active-low and active-high
push-pull reset outputs. For active-low and active-high outputs,
the reset signal is guaranteed to be logic low and logic high,
respectively, for VCC down to 1 V.
The reset output is asserted when VCC is below the reset
threshold (VTH), when MR is driven low, or when WDI is
not serviced within the watchdog timeout period (tWD). Reset
remains asserted for the duration of the reset active timeout
period (tRP) after VCC rises above the reset threshold, after MR
transitions from low to high, or after the watchdog timer times
out. Figure 13 shows the reset outputs.
V
CC
1V
V
CC
0V
V
CC
0V
V
TH
V
TH
0V
V
CC
RESET
RESET
t
RD
t
RD
1V
t
RP
t
RP
04535-012
Figure 13. Reset Timing Diagram
MANUAL RESET INPUT
The ADM6823/ADM6825 feature a manual reset input (MR),
which, when driven low, asserts the reset output. When MR
transitions from low to high, reset remains asserted for the
duration of the reset active timeout period before deasserting.
The MR input has a 50 kΩ internal pull-up so that the input
is always high when unconnected. An external push-button
switch can be connected between MR and ground so that the
user can generate a reset. Debounce circuitry is integrated
on-chip for this purpose. Noise immunity is provided on the
MR input, and fast, negative-going transients of up to 100 ns
(typical) are ignored. A 0.1 μF capacitor between MR and
ground provides additional noise immunity.
WATCHDOG INPUT
The ADM6823/ADM6824 feature a watchdog timer, which
monitors microprocessor activity. A timer circuit is cleared
with every low-to-high or high-to-low logic transition on the
watchdog input pin (WDI), which detects pulses as short as
50 ns. If the timer counts through the preset watchdog timeout
period (tWD), reset is asserted. The microprocessor is required
to toggle the WDI pin to avoid being reset. Failure of the
microprocessor to toggle WDI within the timeout period
therefore indicates a code execution error, and the reset pulse
generated restarts the microprocessor in a known state.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
tion on VCC or MR being pulled low. When reset is asserted, the
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
V
CC
1V
V
CC
0V
V
CC
0V
V
TH
0V
V
CC
WDI
RESET
t
RP
t
RD
t
WD
04535-013
Figure 14. Watchdog Timing Diagram
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 10 of 12
APPLICATION INFORMATION
WATCHDOG INPUT CURRENT
To minimize watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw
as much as 160 µA. Pulsing WDI low-high-low at a low duty
cycle reduces the effect of the large input current. When WDI
is unconnected, a window comparator disconnects the watch-
dog timer from the reset output circuitry so that reset is not
asserted when the watchdog timer times out.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM6823/ADM6824/ADM6825 are equipped
with glitch rejection circuitry. The typical performance
characteristic in Figure 10 plots VCC transient duration vs.
the transient magnitude. The curves show combinations of
transient magnitude and duration for which a reset is not
generated for the 4.63 V and 2.93 V reset threshold parts.
For example, with the 2.93 V threshold, a transient that goes
100 mV below the threshold and lasts 8 µs typically does not
cause a reset, but if the transient is any bigger in magnitude
or duration, a reset is generated. An optional 0.1 µF bypass
capacitor mounted close to VCC provides additional glitch
rejection.
ENSURING RESET VALID TO VCC = 0 V
Both active-low and active-high reset outputs are guaranteed
to be valid for VCC as low as 1 V. However, by using an external
resistor with push-pull configured reset outputs, valid outputs
for VCC as low as 0 V are possible. For an active-low reset
output, a resistor connected between RESET and ground pulls
the output low when it is unable to sink current. For the active-
high case, a resistor connected between RESET and VCC pulls
the output high when it is unable to source current. A large
resistance such as 100 kΩ should be used so that it does not
overload the reset output when VCC is above 1 V.
ADM6823/
ADM6824/
ADM6825
VCC
RESET
100kΩ
ADM6824/
ADM6825
VCC
RESET
100kΩ
04535-015
GND GND
Figure 15. Ensuring Reset Valid to VCC = 0 V
WATCHDOG SOFTWARE CONSIDERATIONS
In implementing the microprocessor’s watchdog strobe
code, quickly switching WDI low-high and then high-low
(minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of
using the watchdog function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
the watchdog from timing out. However, if the subroutine
becomes stuck in an infinite loop, the watchdog could not
detect this because the subroutine continues to toggle WDI. A
more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI is set high. The subroutine sets WDI
low when it is called. If the program executes without error,
WDI is toggled high and low with every loop of the program.
If the subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE
SET WDI
LOW
RETURN
INFINITE LOOP:
WATCHDOG
TIMES OUT
RESET
04535-014
Figure 16. Watchdog Flow Diagram
RESET RESET
WDI I/OMR
ADM6823
VCC
MICROPROCESSOR
04535-016
Figure 17. Typical Application Circuit
Data Sheet ADM6823/ADM6824/ADM6825
Rev. B | Page 11 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
Figure 18. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
A
DM682 xx YRJZ
-
RL7
ORDE R ING QUANTITY
RL7: 3,000 PIECE REEL
GE NERIC NU MBER
(3 TO 5)
TE M PE R ATURE RANG E
Y: –40°C TO +125°C PACK AGE CODE
RJ: 5- L E AD S OT-23
Z: LEAD-FREERESET
THRESHOLD
NUMBER
L: 4. 63 V
M: 4.38V
T: 3.08V
S: 2.93V
R: 2.63V
Z: 2. 32 V
Y: 2 .19 V
W: 1. 67V
V: 1 .58 V
04535-019
Figure 19. Ordering Code Structure
ADM6823/ADM6824/ADM6825 Data Sheet
Rev. B | Page 12 of 12
ORDERING GUIDE
Model1, 2
Reset
Threshold (V)
Reset
Timeout (ms)
Temperature
Range Quantity
Package
Description
Package
Option Branding
ADM6823RYRJZ-RL7 2.63 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6823SYRJ-R7 2.93 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0C
ADM6823SYRJZ-RL7 2.93 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6823TYRJ-R7 3.08 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0C
ADM6823TYRJZ-RL7 3.08 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6823VYRJZ-RL7 1.58 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6823WYRJZ-RL7 1.67 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6823ZYRJZ-RL7 2.32 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0Q
ADM6824TYRJZ-R7 3.08 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0D
ADM6825TYRJZ-R7 3.08 140 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N0E
1 Z = RoHS Compliant Part.
2 If ordering nonstandard models, complete the ordering code shown in Figure 19 by inserting the part number and reset threshold suffixes. Contact Sales for
availability of nonstandard models.
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04535-0-2/13(B)