October 1987
Revised January 1999
CD4093BC Quad 2-Input NAND Schmitt Trigger
© 1999 Fairchild Semicond uctor Corpor ation DS005982.prf www.fairchildsemi .com
CD4093BC
Quad 2-Input NAND Schmitt Trigger
General Descript ion
The CD4093B consists of four Schmitt-trigger circuits.
Eac h ci r cui t f unc t i ons as a 2- in pu t NA ND g a te w i th S ch mi t t -
trigger actio n o n bo th inpu ts. The ga te switches at different
points for positive and negative-going signals. The differ-
ence between the positive (VT+) and the negative voltage
(VT−) is defined as hysteresis voltage (VH).
All outputs have equal source and sink currents and con-
form to standard B-series output drive (see Static Electrical
Characteristics).
Features
■Wide supply voltage range: 3.0V to 15V
■Schmitt-trigger on each input
wit h no e xternal components
■Noise immunity greater than 50%
■Equal source and sink currents
■No limit on input rise and fall time
■Standard B-series output drive
■Hysteresis voltage (any input) TA = 25°C
Applications
• Wave and pulse shapers
• High-noise-environment systems
• Monostable multivibrators
• Astable multivibrators
• NAND logic
Ordering Code:
Devices also available in Tape and R eel. Spec if y by appendin g t he suffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
Typical VDD = 5.0V VH = 1.5V
VDD = 10V VH = 2.2V
VDD = 15V VH = 2.7V
Guaranteed VH = 0.1 VDD
Order Number Package Number Package Description
CD4093BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
CD4093BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4093BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions (Note 2)
Note 1: “Abso lute Maximum Ratings” a re those values beyond w hich the
safety of the devi ce c annot be guaranteed; they are not meant to imply t hat
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device opera tio n.
Note 2: VSS = 0V unles s ot herwise specified.
DC Electrical Characteristics (Note 2)
Note 3: IOH and IOL are tested one output at a time.
DC Supply Voltage (VDD)−0.5 to +18 VDC
Input Voltage (VIN)−0.5 to VDD +0.5 VDC
Storage Temperature Range (TS)−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Out lin e 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 26 0°C
DC Supply Vol ta ge (VDD) 3 to 15 VDC
Input Voltage (VIN)0 to V
DD VDC
Operating Temperature Range (TA)−40°C to +85°C
Symbol Parameter Conditions −40°C+25°C+85°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent De vice VDD = 5V 1.0 1.0 7.5 µA
Current VDD = 10V 2.0 2.0 15.0 µA
VDD = 15V 4.0 4.0 30.0 µA
VOL LOW Level VIN = VDD, |IO| < 1 µA
Output Voltage VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level VIN = VSS, |IO| < 1 µA
Output Voltage VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VT−Ne gativ e- Going Thr eshol d |IO| < 1 µA
Voltage (Any Input) VDD = 5V, VO = 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V
VDD = 10V, VO = 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V
VDD = 15V, VO = 13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V
VT+Positive-Going Threshold |IO| < 1 µA
Voltage (Any Input) VDD = 5V, VO = 0.5V 2.75 3.6 2.75 3.3 3.5 2.65 3.5 V
VDD = 10V, VO = 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V
VDD = 15V, VO = 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V
VHHysteresis (VT+ − VT−)V
DD = 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V
(Any Input) VDD = 10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0 V
VDD = 15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0 V
IOL LOW Level Output VIN = VDD
Current (Note 3) VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VIN = VSS
Current (Note 3) VDD = 5V, VO = 4.6V −0.52 0.44 −0.88 −0.36 mA
VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA
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CD4093BC
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, Input tr, tf = 20 ns, unless otherwise specified
Note 4: AC Paramete rs are guarant eed by DC cor related te sting.
Symbol Parameter Conditions Min Typ Max Units
tPHL, tPLH Propagation Delay Time VDD = 5V 300 450 ns
VDD = 10V 120 210 ns
VDD = 15V 80 160 ns
tTHL, tTLH Transition Time VDD = 5V 90 145 ns
VDD = 10V 50 75 ns
VDD = 15V 40 60 ns
CIN Input Capacitance (Any Input) 5.0 7.5 pF
CPD Power Dissipation Capacitance (Per Gate) 24 pF
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CD4093BC
Typical Applications
Gated Oscillator
Assume t1 + t2 >> tPHL + tPLH then:
t0 = RC
l
n [VDD/VT−]
t1 = RC
l
n [(VDD − VT−)/(VDD − VT+)]
t2 = RC
l
n [VT+/VT−]
Gated One-Shot
(a) Negative-Edge Triggered
(b) Positive-Edge Triggered
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CD4093BC
Typical Performance Characteristics
Typical Transfer
Characteristics
Guaranteed Hysteresis vs VDD
Guaranteed Trigger Threshold
Voltag e vs VDD
Guaranteed Hysteresis vs VDD
Input and Output Characteristics
VNML = VIH(MIN) − VOL ≅ VIH(MIN) = VT+(MIN)
VNMH = VOH − VIL(MAX) ≅ VDD − VIL(MAX) = VDD − VT−(MAX)
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CD4093BC
AC Test Cir cuits and Switching Time Waveforms
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CD4093BC
Physical Dimensions in ches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4093BC Quad 2-Input NAND Schmitt Trigger
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or sys tem s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A criti cal comp onent in any comp onent of a l ife suppor t
device or system whose failure to perform can be rea-
sonably expected to cau se the failure of the li fe support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
