Document Number: 91283 www.vishay.com
S10-1139-Rev. D, 17-May-10 1
Power MOSFET
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Surface Mount (IRFR9220, SiHFR9220)
Straight Lead (IRFUFU9220, SiHFU9220)
Available in Tape and Reel
P-Channel
•Fast Switching
Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third Power MOSFETs technology is the key to Vishay
advanced line of Power MOSFET transistors. The efficient
geometry and unique processing of the Power MOSFETs
design achieve very low on-state resistance combined with
high transconductance and extreme device ruggedness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 50 V, Starting TJ = 25 °C, L = 35 mH, Rg = 25 Ω, IAS = - 3.6 A (see fig. 12).
c. ISD - 3.9 A, dI/dt 95 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
PRODUCT SUMMARY
VDS (V) - 200
RDS(on) (Ω)V
GS = - 10 V 1.5
Qg (Max.) (nC) 20
Qgs (nC) 3.3
Qgd (nC) 11
Configuration Single
S
G
D
P-Channel MOSFET
DPAK
(TO-252)
IPAK
(TO-251)
GDS
S
D
G
D
ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and
Halogen-free SiHFR9220-GE3 SiHFR9220TRL-GE3aSiHFR9220TRR-GE3aSiHFR9220TR-GE3aSiHFU9220-GE3
Lead (Pb)-free IRFR9220PbF IRFR9220TRLPbFaIRFR9220TRRPbFaIRFR9220TRPbFaIRFU9220PbF
SiHFR9220-E3 SiHFR9220TL-E3aSiHFR9220TR-E3aSiHFR9220T-E3aSiHFU9220-E3
SnPb IRFR9220 IRFR9220TRLaIRFR9220TRRaIRFR9220TRaIRFU9220
SiHFR9220 SiHFR9220TLaSiHFR9220TRaSiHFR9220TaSiHFU9220
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 200 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at - 10 V TC = 25 °C ID
- 3.6
A
TC = 100 °C - 2.3
Pulsed Drain CurrentaIDM - 14
Linear Derating Factor 0.33 W/°C
Linear Derating Factor (PCB Mount)e0.020
Single Pulse Avalanche EnergybEAS 310 mJ
Repetitive Avalanche CurrentaIAR - 3.6 A
Repetitive Avalanche EnergyaEAR 4.2 mJ
Maximum Power Dissipation TC = 25 °C PD
42 W
Maximum Power Dissipation (PCB Mount)eTA = 25 °C 2.5
Peak Diode Recovery dV/dtcdV/dt - 5.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 260d
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91283
2S10-1139-Rev. D, 17-May-10
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - - 110
°C/W
Maximum Junction-to-Ambient
(PCB Mount)aRthJA --50
Maximum Junction-to-Case (Drain) RthJC --3.0
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 200 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.22 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 200 V, VGS = 0 V - - - 100 μA
VDS = - 160 V, VGS = 0 V, TJ = 125 °C - - - 500
Drain-Source On-State Resistance RDS(on) V
GS = - 10 V ID = - 2.2 Ab--1.5Ω
Forward Transconductance gfs VDS = - 50 V, ID = - 2.2 A 1.1 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
- 340 -
pFOutput Capacitance Coss - 110 -
Reverse Transfer Capacitance Crss -33-
Total Gate Charge Qg
VGS = - 10 V ID = - 3.9 A, VDS = - 160 V,
see fig. 6 and 13b
--20
nC Gate-Source Charge Qgs --3.3
Gate-Drain Charge Qgd --11
Turn-On Delay Time td(on)
VDD = - 100 V, ID = - 3.9 A,
Rg = 18 Ω, RD = 24 Ω, see fig. 10b
-8.8-
ns
Rise Time tr -27-
Turn-Off Delay Time td(off) -7.3-
Fall Time tf -19-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--- 3.6
A
Pulsed Diode Forward CurrentaISM --- 14
Body Diode Voltage VSD TJ = 25 °C, IS = - 3.6 A, VGS = 0 Vb--- 6.3V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = - 3.9 A, dI/dt = 100 A/μsb- 150 300 ns
Body Diode Reverse Recovery Charge Qrr - 0.97 2.0 μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
Document Number: 91283 www.vishay.com
S10-1139-Rev. D, 17-May-10 3
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
www.vishay.com Document Number: 91283
4S10-1139-Rev. D, 17-May-10
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91283 www.vishay.com
S10-1139-Rev. D, 17-May-10 5
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Pulse width 1 µs
Duty factor 0.1 %
R
D
V
GS
R
g
D.U.T.
- 10 V
+
-
V
DS
V
DD
VGS
10 %
90 %
VDS
td(on) trtd(off) tf
www.vishay.com Document Number: 91283
6S10-1139-Rev. D, 17-May-10
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
A
Rg
IAS
0.01 Ω
tp
D.U.T.
L
VDS
+
-
VDD
- 20 V
Driver
15 V
IAS
VDS
tp
QGS QGD
QG
VG
Charge
- 10 V
D.U.T.
- 3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91283 www.vishay.com
S10-1139-Rev. D, 17-May-10 7
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Vishay Siliconix
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91283.
P.W. Period
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Body diode forward
current
Driver gate drive
Inductor current
D = P.W.
Period
+
-
-
-
-
+
+
+
Peak Diode Recovery dV/dt Test Circuit
dV/dt controlled by Rg
D.U.T. - device under test
D.U.T.
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
Rg
Compliment N-Channel of D.U.T. for driver
VDD
ISD controlled by duty factor “D”
Note
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
VGS = - 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
VDD
Re-applied
voltage
Ripple 5 % ISD
Reverse
recovery
current
Document Number: 91344 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-252AA (HIGH VOLTAGE)
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
E
b3
L3
L4
b2
e
b
D H
E1
D1
A
c2
L1
L2
c
A1
L
θ
MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
E 6.40 6.73 0.252 0.265
L 1.40 1.77 0.055 0.070
L1 2.743 REF 0.108 REF
L2 0.508 BSC 0.020 BSC
L3 0.89 1.27 0.035 0.050
L4 0.64 1.01 0.025 0.040
D 6.00 6.22 0.236 0.245
H 9.40 10.40 0.370 0.409
b 0.64 0.88 0.025 0.035
b2 0.77 1.14 0.030 0.045
b3 5.21 5.46 0.205 0.215
e 2.286 BSC 0.090 BSC
A 2.20 2.38 0.087 0.094
A1 0.00 0.13 0.000 0.005
c 0.45 0.60 0.018 0.024
c2 0.45 0.58 0.018 0.023
D1 5.30 - 0.209 -
E1 4.40 - 0.173 -
θ0' 10' 0' 10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Document Number: 91362 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
D
A
c2
c
Lead tip
5
5
(Datum A)
Thermal PAD
E1
4
D1
View A - A
A1
A
A
C
Seating
plane
CC
BB
θ1
θ2
B
4
4
4
3
5
L1
L
L3
3 x b2
3 x b
3
b4
E
2 x e 0.010 C B
M
A
0.25
0.010 BA
0.25
L2
A
C
M
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -
A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265
b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -
b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC
b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380
b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090
b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050
c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060
c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'
c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'
D 5.97 6.22 0.235 0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Application Note 826
Vishay Siliconix
Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.420
(10.668)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.224
(5.690)
0.180
(4.572)
0.055
(1.397)
0.243
(6.180)
0.087
(2.202)
0.090
(2.286)
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Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
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(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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