32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
Data Sheet
AD5535B
Rev. A Document Feedback
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FEATURES
High integration
32-channel, 14-bit denseDAC® with integrated high
voltage output amplifier
Guaranteed monotonic
Housed in 15 mm × 15 mm CSP_BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
550 µA drive capability
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
1.2 MHz channel update rate
Asynchronous RESET facility
–10°C to +85°C temperature range
APPLICATIONS
Optical microelectromechanical systems (MEMS)
Optical crosspoint switches
Micropositioning applications using piezoelectric actuators
Level setting in automotive test and measurement
GENERAL DESCRIPTION
The AD5535B is a 32-channel, 14-bit denseDAC® with an on-chip
high voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REF_IN pin. The output range is 0 V to
50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V.
Each amplifier can source 550 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
The selected digital-to-analog converter (DAC) register is written
to via the 3-wire interface. The serial interface operates at clock
rates of up to 30 MHz and is compatible with DSP and micro-
controller interface standards.
The device is operated with AVCC = 4.75 V to 5.25 V, DVCC =
2.7 V to 5.25 V, V+ = 4.75 V to 5.25 V, and VPP of up to 225 V.
REF_IN is buffered internally on the AD5535B and should be
driven from a stable reference source.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
RF
R1
RF
R1
RF
R1
RF
R1
INTERFACE
CONTROL
LOGIC
DAC
DAC
DAC
DAC
DV
CC
AV
CC
SYNC
D
IN
SCLK
DGND
AGND
DAC_GND
RESET
REF_IN V
PP
PGND V
+
14-BI T BUS
ANODE
CATHODE
V
OUT
0
V
OUT
1
V
OUT
30
V
OUT
31
AD5535B
10852-001
AD5535B Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features ...................................................................................... 1
Applications ............................................................................... 1
General Description ................................................................. 1
Functional Block Diagram ...................................................... 1
Revision History ....................................................................... 2
Specifications ............................................................................. 3
Timing Characteristics ........................................................ 5
Absolute Maximum Ratings .................................................... 6
ESD Caution .......................................................................... 6
Pin Configuration and Function Descriptions ..................... 7
Typical Performance Characteristics ..................................... 9
Terminology ............................................................................ 11
Functional Description .......................................................... 12
DAC Section ........................................................................ 12
Reset Function .................................................................... 12
Serial Interface .................................................................... 12
Microprocessor Interfacing ............................................... 12
Applications ............................................................................. 14
MEMS Mirror Control Application ................................. 14
IPC-2221-Compliant Board Layout ................................. 14
Power Supply Decoupling Recommendations ..................... 15
Guidelines for Printed Circuit Board Layout...................... 15
Outline Dimensions ............................................................... 16
Ordering Guide ................................................................... 16
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Change to General Description Section ......................................... 1
Changes to DAC Section ................................................................ 12
Changes to MEMS Mirror Control Application Section ........... 14
1/13—Revision 0: Initial Version
Data Sheet AD5535B
Rev. A | Page 3 of 16
SPECIFICATIONS
VPP = 215 V; V+ = 5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
K Grade2
Unit Test Conditions/Comments
Min
Typ
Max
DC PERFORMANCE3
Resolution 14 Bits
Integral Nonlinearity (INL) ±0.1 % of FSR
Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Guaranteed monotonic
Zero Code Voltage 0.5 1 V
Output Offset Error –1 +1 V
Offset Drift 0.5 mV/°C
Voltage Gain 49 50 51 V/V
Gain Temperature Coefficient 5 ppm/°C Due to DAC
–200 ppm/°C Due to DAC and amplifier
Channel-to-Channel Gain Match4 –5 +5 %
OUTPUT CHARACTERISTICS
Output Voltage Range3 1 VPP − 1 V
Output Impedance 50 Ω
Resistive Load4, 5 1 MΩ
Capacitive Load4 200 pF
Short-Circuit Current 0.55 mA
DC Crosstalk4 3 4 LSB
DC Power Supply Rejection (PSRR), VPP 70 dB
Long-Term Drift 0.25 LSB Outputs at midscale,
measured over 30 days at 25°C
AC CHARACTERISTICS4
Settling Time
¼ to ¾ Scale Step 60 µs No load
60 µs 200 pF load
1 LSB Step 5 µs No load
5 µs 200 pF load
Slew Rate 10 V/µs No load
3 V/µs 200 pF load
–3 dB Bandwidth 30 kHz
Output Noise Spectral Density 4.5 µV/√Hz Measured at 10 kHz
0.1 Hz to 10 Hz Output Noise Voltage 1 mV p-p
Digital-to-Analog Glitch Impulse 1 LSB change around major
carry
Positive Transition
15
Negative Transition 8 nV-sec
Analog Crosstalk 2.5 µV-sec
Digital Feedthrough 2 nV-sec
VOLTAGE REFERENCE, REF_IN6 AVCC and V+ must exceed REF_IN
by 1.15 V minimum
Input Voltage Range4 1 4.096 V
Input Impedance 60 kΩ
AD5535B Data Sheet
Rev. A | Page 4 of 16
Parameter1
K Grade2
Unit Test Conditions/Comments
Min Typ Max
TEMPERATURE MEASUREMENT DIODE4
Peak Inverse Voltage, PIV 5 V Cathode to anode
Forward Diode Drop, VF 0.65 0.8 V IF = 100 µA, anode to cathode
Forward Diode Current, IF 100 µA Anode to cathode
V
F
Temperature Coefficient, T
C
−2.20
Anode to cathode
DIGITAL INPUTS4
Input Current ±5 ±10 µA
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Input Hysteresis (SCLK and SYNC Only) 200 mV
Input Capacitance
10
POWER SUPPLY VOLTAGES
VPP (50 ×
REF_IN) + 1
225 V
V+ 4.75 5.25 V
AVCC 4.75 5.25 V
DVCC 2.7 5.25 V
POWER SUPPLY CURRENTS7
IPP
All Channels at Full-Scale 50 60 µA/channel
All Channels at Zero-Scale
25
35
I+ 1.2 1.7 mA
AICC 17.5 20 mA
DICC 0.25 0.6 mA
1 See the Terminology section.
2 K Grade temperature range: −10°C to +85°C; typical = +25°C.
3 Linear output voltage range: 7 V to VPP − 1 V.
4 Guaranteed by design and characterization, not production tested.
5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section.
6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is
programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7
V to VPP − 1 V.
7 Outputs unloaded.
Data Sheet AD5535B
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS
VPP = 210 V; V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN
to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2, 3 A Grade Unit Test Conditions/Comments
fUPDATE 1.2 MHz max Channel update rate
fCLKIN 30 MHz max SCLK frequency
t1 13 ns min SCLK high pulse width
t2 13 ns min SCLK low pulse width
t3 15 ns min SYNC falling edge to SCLK falling edge setup time
t4 50 ns min SYNC low time
t5 10 ns min SYNC high time
t6 10 ns min DIN setup time
t7 5 ns min DIN hold time
t8 200 ns min 19th SCLK falling edge to SYNC falling edge for next write
t9 20 ns min RESET pulse width
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
Figure 2. Serial Interface Timing Diagram
1
LSB
16 17 18 19
MSB
1
RESET
2345
t8
t7
t6
t4
t9
D
IN
SYNC
SCLK
t5
t3t2
t1
10852-002
AD5535B Data Sheet
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VPP to AGND 0.3 V to 240 V
V+ to AGND −0.3 V to +7 V
AVCC to AGND, DAC_GND −0.3 V to +7 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND −0.3 V to AVCC + 0.3 V
VOUT0 to VOUT31 to AGND –0.3 V to VPP + 0.3 V
ANODE/CATHODE to AGND, DAC_GND −0.3 V to +7 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range
Industrial −10°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (T
J
max)
150°C
124-Lead CSP_BGA Package,
θJA Thermal Impedance
40°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD
Human Body Model 2.5 kV
Machine Model 250 V
Field Induced Charged Device Model 400 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
Data Sheet AD5535B
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Assignments
Pin No. Mnemonic
A1 NC
A2 VOUT1
A4 VOUT7
A6 VOUT11
A8 VOUT16
A10 VOUT20
A12 VOUT25
A14 NC
B1
V
OUT
0
B3 VOUT4
B5 VOUT9
B7 VOUT13
B9 VOUT17
B11 VOUT21
B13 VOUT26
C2 VOUT3
C12 VOUT22
C14 VOUT29
D1 VOUT2
D13 VOUT23
E2
V
OUT
5
E4 VOUT8
E6 VOUT12
E8 VOUT15
E10 VOUT19
E12 VOUT24
E14 VOUT31
F3 VOUT6
F5 VOUT10
F7 VOUT14
F9 VOUT18
F13 VOUT30
G14 VOUT28
Pin No. Mnemonic
H1 VPP
H2 VPP
H4 to H11 AGND
H13 VOUT27
J3 to J12 AGND
K1 V+
K2 V+
K3 to K14 AGND
L1
NC
L2 NC
L3 to L13 AGND
L14 DAC_GND
M1 to M12 AGND
M13 AVCC
M14 AVCC
N1 PGND
N2 PGND
N3 CATHODE
N4 ANODE
N5 to N14 AGND
P1 NC
P2 REF_IN
P3 DAC_GND
P4 RESET
P5 DVCC
P6 DGND
P7 TEST
P8 DIN
P9 SCLK
P10 SYNC
P11 to P13 AGND
P14 NC
A
B
C
D
E
F
G
J
H
K
L
M
N
P
10
8
7
6
3
2
19
5
411 12 13 14
10
8
7
6
3
2
19
5
411 12 13 14
A
B
C
D
E
F
G
J
H
K
L
M
N
P
10852-003
AD5535B Data Sheet
Rev. A | Page 8 of 16
Table 5. Pin Function Descriptions
Mnemonic Description
AGND Analog GND Pins.
AVCC Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VPP Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 1 V to 225 V.
V+ V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V.
PGND Output Amplifier Ground Reference Pins.
DGND Digital GND Pins.
DVCC Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND Reference GND Supply for All DACs.
REF_IN Reference Voltage for Channel 0 to Channel 31. Reference input range is 1 V to 4 V and can be used to program the full-
scale output voltage from 50 V to 200 V.
VOUT0 to VOUT31 Analog Output Voltages from the 32 Channels.
ANODE Anode of Internal Diode for Diode Temperature Measurement.
CATHODE Cathode of Internal Diode for Diode Temperature Measurement.
SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in
upon the falling edge of SCLK.
SCLK Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. The pin operates at clock speeds of
up to 30 MHz. Internal pull-up device on logic input; therefore, it can be left floating and defaults to a logic high
condition.
DIN Serial Data Input. Data must be valid upon the falling edge of SCLK.
TEST For normal operation, tie this pin low.
RESET Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is
loaded to the DACs.
NC No Connect. Do not connect to these pins.
Data Sheet AD5535B
Rev. A | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Integral Nonlinearity (INL) with Full-Scale Range = 50 V
Figure 5. Differential Nonlinearity (DNL) with Full-Scale Range = 50 V
Figure 6. INL with Full-Scale Range = 200 V
Figure 7. DNL with Full-Scale Range = 200 V
Figure 8. Short-Circuit Current Limit Timing
Figure 9. Worst-Case Adjacent Channel Crosstalk
16
–16 0
INP UT CODE
INL ERRO R ( LSB)
12
8
4
0
–4
–8
–12
2048 4096 6144 8192 10240 12288 14336 16384
VPP = 60V
V+ = AVCC = +5V
REF _IN = 1V
TA = 25°C
10852-018
1.00
–1.00 0
INP UT CODE
DNL E RROR (L S B)
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
2048 4096 6144 8192 10240 12288 14336 16384
VPP = 60V
V+ = AVCC = +5V
REF _IN = 1V
TA= 25° C
10852-019
16
–16 0
INP UT CODE
INL ERRO R ( LSB)
12
8
4
0
–4
–8
–12
2048 4096 6144 8192 10240 12288 14336 16384
V
PP
= 210V
V
+
= AV
CC
= +5. 25V
REF _IN = 4. 096V
T
A
= 25°C
10852-020
1.00
–1.00 0
INP UT CODE
DNL E RROR (L S B)
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
2048 4096 6144 8192 10240 12288 14336 16384
VPP = 210V
V+ = AVCC = +5.25V
REF _IN = 4. 096V
TA = 25°C
10852-021
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
02048 4096 6144 8192 10240 12288 14336 16384
INP UT CODE
DNL E RROR (L S B)
CH1 5V CH2 5V M 500ns CH1 21.6V
T
10kΩ
DAC AMP
CHANNEL 2 CHANNEL 1
CHANNEL 2
CHANNEL 1
10852-008
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
02048 4096 6144 8192 10240 12288 14336 16384
INP UT CODE
DNL E RROR (L S B)
CH1 50V CH2 200mV M 10µs CH1
1
2
T
VPP = 210V
V+ = AVCC = +5.25V
REF _IN = 4. 096V
VOUT = 100V
TA = 25°C
CHANNEL 1: CHANNE L OUTPUT SLEW
CHANNEL 2: AC CROSSTAL K
CHANNEL 2 ARE A
11 µV- sec
10852-009
AD5535B Data Sheet
Rev. A | Page 10 of 16
Figure 10. Output Amplifier Source and Sink Capability
Figure 11. Offset Error vs. Temperature
Figure 12. Gain Error vs. Temperature
Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output,
Switching All Other Channels in Sequence
Figure 14. Settling Time vs. Capacitive Load
0
–5 2
SO URCE /SI NK CURRE NT (mA)
OUTPUT VOLTAGE (V)
140
120
100
80
60
40
20
–4 –3 –2 –1 0 1
V
PP
= 210V
V
+
= AV
CC
= +5. 25V
REF _IN = 4. 096V
V
OUT
= 70V
T
A
= 25°C
10852-022
12.0
8.0
–10
TEMPERATURE (°C)
OFF SET ERROR (mV)
11.5
11.0
10.5
10.0
9.5
9.0
8.5
010 20 30 40 50 60 70 80
V
PP
= 210V
V
+
= AV
CC
= +5. 25V
REF _IN = 4. 096V
10852-028
–1.0
–1.5
–10
TEMPERATURE (°C)
GAIN ERRO R ( %)
010 20 30 40 50 60 70 80
–1.1
–1.2
–1.3
–1.4
VPP = 210V
V+ = AVCC = +5.25V
REF _IN = 4. 096V
10852-029
0.04
–0.04 030
CHANNEL NUM BE R
DC CROS S TALK ( V )
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
510 15 20 25
V
PP
= 210V
V
+
= AV
CC
= +5. 25V
REF _IN = 4. 096V
T
A
= 25°C
VI CTIM CHANNE L = 31
V
OUT
31 = MI DS CALE
FULL-SCALE TRANSITION ON
OTHER CHANNELS IN SE QUENCE .
10852-025
180
000.10
TIME (ms)
OUTPUT VOLTAGE (V)
160
140
120
100
80
60
40
20
0.02 0.04 0.06 0.08
0pF
100pF
200pF
V
PP
= 210V
V
+
= AV
CC
= +5. 25V
REF _IN = 4. 096V
T
A
= 25°C
1/4 FULL-SCALE TO
3/4 FULL-SCALE STEP
10852-026
Data Sheet AD5535B
Rev. A | Page 11 of 16
TERMINOLOGY
Integral Nonlinearity (INL)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function.
It is expressed as a percentage of full-scale range.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.
Zero Code Voltage
A measure of the output voltage present at the device output
with all 0s loaded to the DAC. It includes the offset of the
DAC and the output amplifier and is expressed in V.
Offset Error
Calculated by taking two points in the linear region of the
transfer function, drawing a line through these points, and
extrapolating back to the y-axis. It is expressed in V.
Voltage Gain
Calculated from the change in output voltage for a change in
code, multiplied by 16,384, and divided by the REF_IN voltage.
This is calculated between two points in the linear section of the
transfer function.
Gain Error
A measure of the output error with all 1s loaded to the DAC,
and the difference between the ideal and actual analog output
range. Ideally, the output should be 50 × REF_IN. It is expressed
as a percentage of full-scale range.
DC Power Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in VPP
supply voltage. It is expressed in dB, and VPP is varied ±5%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and the output change of all other DACs. It is expressed
in LSB.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within ±0.5 LSB of its final
value. Measured for a step change of ¼ to ¾ full scale.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as
the area of the glitch in nV-sec when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Analog Crosstalk
The area of the glitch transferred to the output (VOUT) of one DAC
due to a full-scale change in the output (VOUT) of another DAC.
The area of the glitch is expressed in nV-sec.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from
the digital control inputs when the part is not being written to
(SYNC is high). It is specified in nV-sec and measured with a
worst-case change on the digital input pins, for example, from
all 0s to all 1s and vice versa.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise
is characterized as a spectral density (voltage per √Hz). It is
measured by loading all DACs to midscale and measuring noise
at the output. It is measured in μV/√Hz.
AD5535B Data Sheet
Rev. A | Page 12 of 16
FUNCTIONAL DESCRIPTION
The AD5535B consists of a 32-channel, 14-bit DAC with 200 V
high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA
package. The output voltage range is programmable via the
REF_IN pin. The output range is 0 V to 50 V when REF_IN =
1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to
the device is through a serial interface operating at clock rates of
up to 30 MHz, which is compatible with DSP and microcontroller
interface standards. A 5-bit address and a 14-bit data-word are
loaded into the AD5535B input register via the serial interface.
The channel address is decoded, and the data-word is converted
into an analog output voltage for this channel.
At power-on, all the DAC registers are loaded with 0s.
DAC SECTION
The architecture of each DAC channel consists of a resistor
string DAC, followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary, and the ideal DAC
output voltage is given by
14
_
2
50 DV
VINREF
OUT
××
=
where D is the decimal equivalent (0 to 16,383) of the binary
code, which is loaded to the DAC register.
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output amplifier
is from 7 V to VPP − 1 V. The amplifier output bandwidth is
typically 30 kHz, and is capable of sourcing 550 µA and sinking
2.8 mA. Settling time for a ¼ to ¾ full-scale step change is
typically 60 µs with a load of up to 200 pF.
RESET FUNCTION
The reset function on the AD5535B can be used to reset all
nodes on the device to their power-on reset condition. All the
DACs are loaded with 0s, and all registers are cleared. Take
the RESET pin low to implement the reset function.
SERIAL INTERFACE
The serial interface is controlled by the three following pins:
• SYNC, which is the frame synchronization pin for the serial
interface.
• SCLK, which is the serial clock input that operates at clock
speeds of up to 30 MHz.
• DIN, which is the serial data input and data must be valid
upon the falling edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535B input register.
A4 to A0 Bits
The A4 to A0 bits can address any one of the 32 channels. A4 is
the MSB of the address, while A0 is the LSB.
DB13 to DB0 Bits
The DB13 to DB0 bits are used to write a 14-bit data-word into
the addressed DAC register.
Figure 2 is the timing diagram for a serial write to the
AD5535B. The serial interface works with both a continuous
and a discontinuous serial clock. The first falling edge of SYNC
resets the serial clock counter to ensure that the correct number
of bits are shifted into the serial shift register. Any further edges
on SYNC are ignored until the correct number of bits are
shifted in. After 19 bits are shifted in, the SCLK is ignored. For
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC. The user must allow 200 ns
(minimum) between successive writes.
Figure 15. Serial Data Format
MICROPROCESSOR INTERFACING
AD5535B-to-ADSP-BF527 Interface
The Blackfin® DSP is easily interfaced to the AD5535B without
the need for extra logic. A data transfer is initiated by writing a
word to the TX register after SPORT is enabled. In a write
sequence, data is clocked out on each rising edge of the serial
clock of the DSP and clocked into the AD5535B on the falling
edge of its SCLK. The SPORT can be configured to transmit 19
SCLKs while TFS is low. Figure 16 shows the connection diagram.
Figure 16. AD5535B-to-ADSP-BF527 Interface
A4 A3 A2 A1 A0 DB13 T O DB0
MSB LSB
10852-010
10852-011
ADSP-BF527
SYNCSPORT_TFS SCLK
SPORT_TSCK SDINSPORT_DTO
GPIO0 RESET
AD5535B
Data Sheet AD5535B
Rev. A | Page 13 of 16
AD5535B-to-MC68HC11 Interface
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit (CPOL)
= 0, and clock phase bit (CPHA) = 1. The SPI is configured by
writing to the SPI control register (SPCR). SCK of the MC68HC11
drives the SCLK of the AD5535B and the MOSI output drives
the serial data line (DIN) of the AD5535B. The SYNC signal is
derived from a port line (PC7). When data is being transmitted
to the AD5535B, the SYNC pin is taken low (PC7).
Data appearing on the MOSI output is valid on the falling edge
of SCK. The MC68HC11 transfers only eight bits of data during
each serial transfer operation; therefore, three consecutive write
operations are necessary to transmit 19 bits of data. Data is
transmitted MSB first. It is important to left justify the data in
the SPDR register so that the first 19 bits transmitted contain
valid data. PC7 must be pulled low to start a transfer. PC7 is then
taken high and pulled low again before any further write cycles
can take place. Figure 17 shows the connection diagram.
Figure 17. AD5535B-to-MC68HC11 Interface
AD5535B-to-PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
In this example, I/O port RA1 is being used to pulse SYNC and
to enable the serial port of the AD5535B. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1 must
be pulled low to start a transfer. RA1 must then be brought high
and pulled low again before any further write cycles can take
place. Figure 18 shows the connection diagram.
Figure 18. AD5535B-to-PIC16C6x/7x Interface
AD5535B-to-8051 Interface
The AD5535B requires a clock synchronized to the serial data.
Therefore, the 8051 serial interface must operate in Mode 0. In
this mode, serial data exits the 8051 through RxD, and a shift
clock is output on TxD. The SYNC signal is derived from a port
line (P1.1). Figure 19 shows how the 8051 is connected to the
AD5535B. Because the AD5535B shifts data out upon the rising
edge of the shift clock and latches data in upon the falling edge,
the shift clock must be inverted. Note that the AD5535B also
requires its data to be MSB first. Because the 8051 outputs LSB
first, the transmit routine must take this into account.
Figure 19. AD5535B-to-8051 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5535B*
MC68HC11*
SCLK
D
IN
SYNC
SCK
MOSI
PC7
10852-012
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5535B*
PIC16C6x/7x*
SCLK
D
IN
SYNC
SCK/RC3
SDI/RC4
RA1
10852-013
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5535B* 8051*
SCLK
D
IN
SYNC
TxD
RxD
P1.1
10852-014
AD5535B Data Sheet
Rev. A | Page 14 of 16
APPLICATIONS INFORMATION
MEMS MIRROR CONTROL APPLICATION
The AD5535B is targeted to all optical switching control systems
based on MEMS technology. The AD5535B is a 32-channel,
14-bit DAC with integrated high voltage amplifiers. The output
amplifiers are capable of generating an output range of 0 V to
200 V when using a 4 V reference. The full-scale output voltage
is programmable from 50 V to 200 V using reference voltages
from 1 V to 4 V. Each amplifier can output 550 µA and directly
drives the control actuators, which determine the position of
MEMS mirrors in optical switch applications.
The AD5535B is generally used in a closed-loop feedback system,
as shown in Figure 20, with a high resolution ADC and DSP.
The exact position of each mirror is measured using capacitive
sensors. The sensor outputs are multiplexed using an ADG739
4-to-1 multiplexer to an 8-channel, 14-bit ADC (AD7856). An
alternative solution is to multiplex using a 32-to-1 multiplexer
(ADG732) into a single-channel ADC (AD7671). The control
loop is driven by an ADSP-21065L, a 32-bit SHARC® DSP with
an SPI-compatible SPORT interface. With 14-bit monotonic
behavior and a 0 V to 200 V output range, coupled with its fast
serial interface, the AD5535B is ideally suited for controlling a
cluster of MEMS-based mirrors.
Figure 20. AD5535B in a MEMS-Based Optical Switch
IPC-221-COMPLIANT BOARD LAYOUT
The diagram in Figure 21 is a typical 2-layer printed circuit board
(PCB) layout for the AD5535B that complies with the specifications
outlined in IPC-221. Do not connect to the four corner balls
labeled as original no connects. Connect balls labeled as
additional no connects to AGND.
The routing shown in Figure 21 shows the feasibility of
connecting to the high voltage balls while complying with
the spacing requirements of IPC-221. Figure 21 also shows
the physical distances that are available.
Figure 21. Layout Guidelines to Comply with IPC-221
ADSP-21065L
AD5535B
OUT P UT RANG E
0V TO 200V
V
OUT
0
14-BIT DAC
14-BIT DAC
REF198
(4.096V)
ACTUATORS
FOR
MEMS
MIRROR
ARRAY
SENSOR
+
4-TO-1 M UX
(ADG739)
OR
32-TO-1 M UX
(ADG732)
8-CHANNEL
ADC (AD7856)
OR
SINGLE-
CHANNEL
ADC (AD7671)
+210V
+5V
V
PP
V
+
REF_IN
V
OUT
31
10852-015
A
B
C
D
E
F
G
J
H
K
L
M
N
P
10
8
7
6
3
2
19
5
411 12 13 14
1.414mm
2mm
250µm RAD
SPACE = 405µm
100µm
250µm RAD
SPACE = 405µm
250µm RAD
SPACE = 433µm 100µm
250µm RAD
SPACE = 433µm
SPACE = 433µm 100µm
DETAIL A
A1 BALL PAD CO RNE R
1
1
1
ORIGINAL
NO CONNECT S
ADDITIONAL
NO CONNECT S
1
10852-016
Data Sheet AD5535B
Rev. A | Page 15 of 16
POWER SUPPLY DECOUPLING RECOMMENDATIONS
On the AD5535B, it is recommended to tie all grounds together
as close to the device as possible. If the number of supplies must be
reduced, bring all supplies back separately and make a provision
on the board via a link option to drive the AVCC and V+ pins
from the same supply. Decouple all power supplies adequately
with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors.
GUIDELINES FOR PCB LAYOUT
Design printed circuit boards such that the analog and digital
sections are separated and confined to the designated analog
and digital sections of the board. This facilitates the use of ground
planes that can be separated easily. A minimum etch technique
is generally the best for ground planes because it optimizes
shielding of sensitive signal lines. Join digital and analog ground
planes in one place only, at the AGND and DGND pins of the
high resolution converter. To isolate the high frequency bus of
the processor from the bus of the high resolution converters, buffer
or latch data and address buses on the board. These act as a
Faraday shield and increase the signal-to-noise performance of
the converters by reducing the amount of high frequency digital
coupling. Avoid running digital lines under the device because
they couple noise onto the die. Allow the ground plane to run
under the IC to avoid noise coupling.
Use as large a trace as possible for the supply lines of the device
to provide low impedance paths and reduce the effects of glitches
on the power supply line. Shield components, such as clocks with
fast-switching signals, with digital ground to avoid radiating noise
to other sections of the board. Never run clock signals near the
analog inputs of the device. Avoid crossovers of digital and analog
signals. Keep traces for analog inputs as wide and short as possible
and shield with analog ground if possible. Run traces on opposite
sides of the 2-layer PCB at right angles to each other to reduce the
effects of feedthrough through the board.
A microstrip technique is by far the best, but it is not always
possible to use with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
and signals are placed on the solder side. Multilayer printed
circuit boards with dedicated ground, power, and tracking
layers offer the optimum solution in terms of obtaining analog
performance, but at increased manufacturing costs.
Good decoupling is vitally important when using high resolu-
tion converters. Decouple all analog supplies with 10 µF tantalum
capacitors in parallel with 0.1 µF ceramic capacitors to analog
ground. To achieve the best results from the decoupling components,
place them as close to the device as possible, ideally right up
against the IC or the IC socket. The main aim of a bypassing
element is to maximize the charge stored in the bypass loop
while simultaneously minimizing the inductance of this loop.
Inductance in the loop acts as an impedance to high frequency
transients and results in power supply spiking. By keeping the
decoupling as close to the device as possible, the loop area is
kept as small as possible, thereby reducing the possibility of
power supply spikes. Decouple digital supplies of high resolution
converters with 10 µF tantalum capacitors and 0.1 µF ceramic
capacitors to the digital ground plane. Decouple the V+ supply
with a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor
to AGND.
Decouple all logic chips with 0.1 µF ceramic capacitors to digital
ground to decouple high frequency effects associated with
digital circuitry.
AD5535B Data Sheet
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
Figure 22. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-124-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Function Output Voltage Span Temperature Range Package Description Package Option
AD5535BKBC 32 DACs 0 V to 200 V maximum −10°C to +85°C 124-Lead CSP_BGA BC-124-2
AD5535BKBCZ 32 DACs 0 V to 200 V maximum −10°C to +85°C 124-Lead CSP_BGA BC-124-2
EVAL-AD5535BEBZ Evaluation Board
1 Z = RoHS Compliant Part.
DETAI L A
BALL DIAM E TER
A
B
C
D
E
F
G
J
H
K
L
M
N
P
10 876321
954
11
1213
14
*1.25 M AX
0.85 M IN
*0.41
0.36
0.31
*0.46 NOM
*COM P LIANT W IT H JE DE C S TANDARDS M O-192- AAE - 1
WITH E X CE P TI ON T O DI M E NS IO NS INDI CATED BY AN AS TERI S K.
NOM INAL BALL S IZ E IS RE DUCE D FRO M 0.60mm T O 0. 46mm.
A1 BALL
CORNER
TOP VI EW
DETAIL A
BOTTOM VIEW
SEATING
PLANE
COPLANARITY
0.12
13.00
REF
12-19-2012-A
15.10
15.00 S Q
14.90
BALL A1
PAD CO RNE R
1.00
BSC
1.70 M AX
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10852-0-4/13(A)