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GENERAL DESCRIPTION
The DS33R11/DS33ZH11 design kit is an easy-to-
use evaluation board for the DS33R11 and the
DS33ZH11 Ethernet transport-over-serial link
devices. The DS33ZH11 section of the design kit
contains an option for either T3E3 or T1E1 serial
links. The DS33R11 chipset has an integrated T1E1
transceiver. All serial links are complete with line
interface, transformers, and network connections.
Dallas’ ChipView software is provided with the design
kit, giving point-and-click access to configuration and
status registers from a Windows-based PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
Windows is a registered trademark of Microsoft Corp.
DESIGN KIT CONTENTS
DS33R11DK/DS33ZH11DK Main Board (DS33R11 +
DS33ZH11)
CD ROM:
ChipView Software and Manual
DS33R11DK/DS33ZH11DK Data Sheet
Configuration Files
FEATURES
Demonstrates Key Functions of DS33R11 and
DS33ZH11 Ethernet Transport Chipsets
DS33ZH11 Section Includes DS21348 T1E1
LIU and DS3150 T3E3 LIU, Transformers, BNC
and RJ48 Network Connectors and
Termination
Provides Support for Hardware and Software
Modes
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
DS33R11 Register Set
All DS33R11 and DS33ZH11 Interface Pins are
Easily Accessible for External Data
Source/Sink
LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
ORDERING INFORMATION
PART DESCRIPTION
DS33R11DK Design Kit for DS33R11 and
DS33ZH11
www.maxim-ic.com
DS33R11DK/DS33ZH11DK
Ethernet Transport Design Kit
DS33R11DK/DS33ZH11DK
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TABLE OF CONTENTS
GENERAL DESCRIPTION ..........................................................................................................1
DESIGN KIT CONTENTS............................................................................................................1
ORDERING INFORMATION .......................................................................................................1
COMPONENT LIST.....................................................................................................................3
SYSTEM FLOORPLAN ...............................................................................................................8
PC BOARD ERRATA..................................................................................................................8
FILE LOCATIONS .......................................................................................................................9
BASIC OPERATION..................................................................................................................10
POWERING UP THE DESIGN KIT ...............................................................................................................10
General ............................................................................................................................................................... 10
BASIC DS33R11 INITIALIZATION .............................................................................................................. 10
Additional Configuration for DS33R11 ............................................................................................................... 10
BASIC DS33ZH11 INITIALIZATION............................................................................................................11
Additional Configuration for DS33ZH11 ............................................................................................................. 11
MONITOR AND CAPTURE ETHERNET TRAFFIC ...............................................................................11
LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS ..............................12
ADDRESS MAP (ALL CARDS) ................................................................................................16
DS33R11 INFORMATION .........................................................................................................16
DS33R11DK/DS33ZH11DK INFORMATION ............................................................................17
TECHNICAL SUPPORT ............................................................................................................17
SCHEMATICS ...........................................................................................................................17
DS33R11DK/DS33ZH11DK
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COMPONENT LIST
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER
C01, C28, CB03, CB49,
CB136, CB146, CB192,
CP01, CP2, CP03
10 470µF ±20%, 6.3V tantalum capacitors
(D case)
KEM
T491D477M006AS
C02, C11, C30, CB36,
CB37, CB40–CB43,
CB45, CB153, CB195,
CB197
13 1µF ±10%, 16V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1C105K
C03–C06, C13, C14,
C17, C20, C22, C26,
C29, . . .incomplete
listing (94 devices total)
94 0.1µF ±10%, 16V ceramic capacitors
(0603)
Phycomp
06032R104K7B20D
C07, C08, C09, C12,
C16, C18, C19, C21,
C23, C24, C31, . . .
incomplete listing (81
devices total)
81 10µF ±20%, 10V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1A106M
C10, CB23, CB24, CB26,
CB33, CB91, CB95,
CB151, CB161, CB162,
CB175, CB177, CB181,
CB185, CB189, CB190
16 0.1µF ±20%, 16V X7R ceramic
capacitors (0603)
AVX
0603YC104MAT
C15, CB76, CB77,
CB169, CB179, CB188 6 10µF ±20%, 10V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1A106M
C25, C27, CB154–
CB156, CB158–CB160,
CB166, CB173, CB174,
CB182, CB183
13 4.7µF, 6.3V ceramic multilayer
capacitors (0603)
UNK
ECJ-1VB0J475M
CB105 1
0.1µF ±10%, 16V ceramic capacitor
(0805)
Phycomp
08052R104K7B20D
CB180 1
1µF ±10%, 16V ceramic capacitor (1206) Panasonic
ECJ-3YB1C105K
DB01 1 1A, 40V Schottky diode International Rectifier
10BQ040
DS01, DS02, DS05,
DS13, DS14 5 Red LEDs (SMD) Panasonic
LN1251C
DS03, DS08, DS15,
DS19 4 Red LEDs (SMD) Panasonic
LN1251C
DS04, DS07, DS12,
DS21 4 Green LEDs (SMD) Panasonic
LN1351C
DS06, DS09, DS10,
DS11, DS16, D17, DS18,
DS20
8 Amber LEDs (SMD) Panasonic
LN1451C
GND_TP01, GND_TP02,
GND_TP03,
GND_TPB01,
GND_TPP01–
GND_TPP23
27 Standard ground clip Keystone
4954
H01–H06, HB01, HB02,
HB03 9 Kit, 4-40 hardware, 0.5" nylon standoff
and nylon hex-nut
Lab stock
4-40KIT6
DS33R11DK/DS33ZH11DK
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DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER
J01, J05, J06, J18, J36 5 Terminal strip (10-pin, dual row, vertical) Samtec
TSW-105-07-T-D
J02 1 DB9 right-angle connector (long case) AMP
747459-1
J03, J10, J11, J14–J17,
J25, J26, J27, J32, J34,
J35
13 100-mil, 2-position jumpers Lab stock
Not applicable
J04 1 100-mil, 2 x 7-position jumper Lab stock
Not applicable
J07, J08, J09 3 Not Populated
14-pin headers, dual row, vertical
Samtec
NOPOP-HDR-TSW-107-14-T-D
J12, J13, J22, J23, J30,
J33 6 L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT DO NOT POPLUATE DNP
J19, J24 2
Not Populated
5-pin connectors, BNC
75Ω, right angle
Trompetor
NOPOP-UCBJR220
J20, JB03 2 8-pin single-port RJ48 connectors MOLEX
15-43-8588
J21, J37 2 8-pin connectors (fastjack single, for
national PHY)
Halo Electronics
HFJ11-2450E
J28, J29, J31 3 20-pin headers (dual row, vertical) Samtec
HDR-TSW-110-14-T-D
J38, J39 2 5-pin BNC connectors (75Ω, right angle) Trompetor
UCBJR220
J40, J41 2 5-pin BNC connectors (right angle) Trompetor
UCBJR220
JB01, JB05 2 Sockets, banana plug, horizontal, black Mouser Electronics
164-6218
JB02, JB04 2 Sockets, banana plug, horizontal, red Mouser Electronics
164-6219
JP01–JP11, JPB01 12 100-mil, 3-position jumpers Lab stock
Not applicable
R1, R2 2 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
R01 1
1.0MΩ ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ105V
R02 1
10kΩ ±1%, 1/10W resistor (0805) Panasonic
ERJ-6ENF1002V
R03, R04, R05, R09,
R14, R15, R21, RB35,
RB52, RB53, RB58,
RB69, RB70, RB73,
RB77–RB86, RB89,
RB90, RB93–RB96,
RB101, RB132, RB133,
RB137, RB138, RB144,
RB151–RB155, RB159,
RB162
43 30Ω, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ300V
R06, R08, R23, R24 4 49.9Ω ±1%, 1/16W resistors (0603) Panasonic
ERJ-3EKF49R9V
DS33R11DK/DS33ZH11DK
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DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER
R07, R10, R12, R13,
RB15 5 0Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEY0R00V
R11, RB167 2 10.0kΩ ±1%, 1/16W resistors (0603 ) Panasonic
ERJ-3EKF1002V
R16–R19 4
0Ω ±5%, 1/10W resistors (0805) Panasonic
ERJ-6GEY0R00V
R20, R22 2 330Ω ±5%, 1/8W resistors (1206) Panasonic
ERJ-8ENF3300V
RB01–RB03, RB06–
RB13, RB17, RB18,
RB22, RB25, RB27,
RB28, RB32, RB33
19 10kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
RB04, RB05, RB30,
RB31, RB34, RB36–
RB43, RB59–RB61,
RB63, RB99, RB100,
RB150
20 10kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
RB129 1
30Ω ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ300V
RB14, RB19, RB44–
RB47, RB49–RB51,
RB54, RB97, RB98,
RB102, RB104, RB116,
RB178
16 2.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ202V
RB148, RB149 2 61.9Ω ±1%, 1/10W resistors (0805) Panasonic
ERJ-6ENF61R9V
RB156 1
330Ω ±5%, 1/10W resistor (0805) Panasonic
ERJ-6GEYJ331V
RB16, RB20, RB48,
RB66, RB67, RB68,
RB71, RB74, RB75,
RB135, RB142, RB146,
RB157, RB161, RB165,
RB169, RB174, RB176
18 330Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ331V
RB177 1
51.1Ω ±1%, 1/10W resistor (0805) Panasonic
ERJ-6ENF51R1V
RB21, RB23 2 330Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ331V
RB24 1
1.0kΩ ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ102V
RB26, RB103, RB105–
RB115, RB117–RB128,
RB130, RB131, RB134,
RB136, RB139–RB141,
RB143, RB163, RB166,
RB170
36 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ102V
RB29 1
0Ω ±5%, 1/8W resistor (1206) Panasonic
ERJ-8GEYJ0R00V
DS33R11DK/DS33ZH11DK
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DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER
RB55, RB56, RB57,
RB62, RB64, RB65,
RB72, RB76, RB145,
RB147, RB158, RB160,
RB164, RB168, RB173,
RB175
16 5.1kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ512V
RB87, RB91 2 60.4Ω ±1%, 1/10W resistors (0805) Panasonic
ERJ-6ENF60R4V
RB88, RB92, RB171,
RB172 4 54.9Ω ±1%, 1/16W resistors (0603) Panasonic
ERJ-3EKF54R9V
SHORT01 1
2-position SMD jumper
Do not populate. Intended to have
solder bridge during assembly.
Not populated
SW01, SW02 2 4-pin single-pole switch Panasonic
EVQPAE04M
T01 1 16-pin dual SMT transformer Pulse Engineering
TX1099
T02, T03 2 6-pin SMT transformers (1:2CT,
transmitter/receiver)
Pulse Engineering
PE-65968
TB01 1
12-pin SMT transformer (1CT:1CT and
1CT:2CT)
Pulse Engineering
PE-68877
TP01–TP03, TPB01–
TPB11, TPP01,TPP02 16 Test points (one plated hole)
Do not stuff. —
U01, U15 2 Microprocessor voltage monitors
2.93V reset, 4-pin SOT143
Maxim
MAX811SEUS-T
U02 1
2Mb SPI serial EEPROM
8-pin SO, 2.7V to 3.6V
Atmel
AT25F2048N-10SU-2.7
U03 1 MMC2107 Processor Motorola
MMC2107
U04 1
FPGA IC
1.2V, 20mm x 20mm, 144-pin TQFP
Lattice Semiconductor
LFEC3E-3T144C
U05, UB03 2 Cypress SRAM, Lab Stock Lab stock
U06, U07 2 High-speed inverters Fairchild Semiconductor
NC7SZ86
U08, UB07 2 1.8V or Adj
8-Pin µMAX/SO
Maxim
MAX1792EUA18
U09 1
DS33R11, Z44/2156 MCM
27mm x 27mm, 256-pin BGA
Dallas Semiconductor
DS33R11
U10, U14 2 DsPHYTER II Single 10/100 Ethernet
transceiver (65-pin LLP)
National Semiconductor
DP83847ALQA56A
DS33R11DK/DS33ZH11DK
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DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER
U11 1
DS33ZH11 ELITE 10/100 Ethernet
transport over serial link
10mm x 10mm, 100-pin CSBGA
Dallas Semiconductor
DS33ZH11
U12 1 DS21348 LIU 44-pin TQFP Dallas Semiconductor
DS21348
U13 1
DS3150 T3/E3/STS-1 LIU I/F
48-pin TQFP
Dallas Semiconductor
DS3150T
UB01 1
Dual RS-232 transceiver with 3.3V/5V
internal capacitors
Maxim
MAX3233E
UB02 1
LDO regulator with reset,1.20V output
300mA, 6-pin SOT23
Maxim
MAX1963EZT120-T
UB04, UB05 2 Synchronous DRAM, 1Meg x 32 x 4
banks, 86-pin TSOP
Micron
MT48LC4M32B2TG-7
UB06 1 High-speed buffer Fairchild Semiconductor
NC7SZ86
XB01 1 Low-profile 8.0MHz crystal ECL
EC1-8.000M
Y01, YB05 2 Oscillator, crystal clock
3.3V, 2.048MHz (needs socket)
SaRonix
NTH039A3-2.0480
Y02 1
Not populated
Oscillator, crystal clock
3.3V, 25.000MHz (low jitter)
SaRonix
NTH089AA3-25.000
Y03, YB03 2 Oscillator, crystal clock
3.3V, 100.000MHz
SaRonix
NTH089A3-100.0000
Y04 1
SPI serial EEPROM
2.7V, 16k, 8-pin DIP (needs socket)
Atmel
AT25160A-10PI-2.7
Y05 1
Oscillator, crystal clock,
3.3V, 34.368MHz (needs socket)
SaRonix
NTH089AA3-34.368
YB01 1
Oscillator, crystal clock
3.3V, 44.736MHz (needs socket)
SaRonix
NTH089AA3-44.736
YB02 1
Oscillator, crystal clock
3.3V, 1.544MHz (needs socket)
SaRonix
NTH039A3-1.5440
YB04 1
Oscillator, crystal clock
3.3V, 25.000MHz (low jitter)
SaRonix
NTH089AA3-25.000
DS33R11DK/DS33ZH11DK
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SYSTEM FLOORPLAN
PC BOARD ERRATA
• Center tap of T02 was not pulled to V3_3 in DS33R11DK/DS33ZH11DK01A0 revision (page 23 in schematic).
Pin T02.2 is pulled to V3_3 with a wire in the DS33R11DK/DS33ZH11DK01A0 revision.
• Reference designators were assigned for R1, R2 and R01, R02. R1 and R2 will be renamed in the next design.
• Component R1, R2 and Y05 are on bottom of the PC board but do not have the same prefix as other
components on the bottom side.
• Silkscreen for J36.6 is mislabeled. It reads “RT0” but should read “RT1.”
• Oscillators Y03 and YB03 are not suitable for use as input clocks for the Ethernet PHY. Because of this, the
oscillators will only be used as the SDRAM oscillators. These oscillators generate too much jitter to function as
the input clock for the PHY. This requires that the PHY is driven by the default oscillator, YB04 and YB02.
Jumpers JP03 and JP11 have been modified to prevent accidental selection of the wrong oscillator.
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
TRANSFORMER AND NETWORK
CONNECTIONS (T3E3)
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
BACKPLANE JUMPERS—TO DS33ZH11
10/100 ETHERNET PHY AND
MAGNETICS
10/100 ETHERNET PHY AND
MAGNETICS
LEDs
LEDs
LEDs
DS33R11
DS3150
T3E3 LIU
CONFIGURATION
JUMPERS
DS3150
T3E3 LIU
CONFIGURATION
JUMPERS
EEPROM
(CONFIG)
SDRAM
DS33ZH11
TSER RSER TCLK RCLK
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
SDRAM
TEST POINTS
TEST POINTS
TEST POINTS
DS33R11/DS33ZH11 DESIGN KIT
DS33R11 SECTION DS33ZH11 SECTION
DS33R11DK/DS33ZH11DK
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FILE LOCATIONS
This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file
from the Maxim website at www.maxim-ic.com/DS33R11DK.
All locations are given relative to the top directory of the CD/zip file.
Table 1. DS33Z11 Register Definition and Configuration Files
FILE NAME. FILE USAGE
.\DS33R11_cfg_demo_gui\DS33Z11.def
Top level definition file to select in
ChipView’s register mode. This file
autoloads the remaining definition files
shown below. (Note: The DS33R11 is
composed of an integrated DS33Z11 and
an integrated DS2155.)
.\DS33R11_cfg_demo_gui\SU_LI_PORT1.def
.\DS33R11_cfg_demo_gui\DS2155.def
Dependant files. These are called by the
DS33Z11.def file, which is listed above.
.\DS33R11_cfg_demo_gui\basic_Config.eset
GUI interface for loading settings when
running the Zchip plug-in (launched from
the Tools menu of the ChipView program).
.\DS33R11_cfg_demo_gui\basic_config.mfg
.\DS33R11_cfg_demo_gui\e1_gapclk_crc4_hdb3_nocas.ini
Files for manually configuring the
DS33Z11 and DS2155 to convert Ethernet
traffic to serial a T1E1 stream.
.\DS33R11_cfg_demo_gui\DS2155_T1_BERT_ESF.ini
.\DS33R11_cfg_demo_gui\gapclk_llb_DS2155_T1_ESF_LBO0_2.ini
Stand-alone configuration files for
evaluating the DS33R11’s integrated
DS2155 T1E1 transceiver. These files are
for evaluating DS2155 functionality, and
disrupt the Ethernet to serial traffic flow.
DS33R11DK/DS33ZH11DK
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BASIC OPERATION
Powering Up the Design Kit
• Connect PCB 3.3V and GND banana plugs to power supply. A 2A supply is recommended. At steady-state, the
system should draw approximately 700mA.
• Verify that jumpers are configured as described in Table 2.
General
• Upon power-up, the DS33R11 Queue overflow LED (DS02 red) will not be lit; also, the INT LED (DS01 red) will
not be lit. PHY LINK LED (DS07 green) should be lit if the Ethernet is connected. Transceiver RLOS LED
(DS05 red) will be lit.
• DS33ZH11 does not have Queue overflow or INT pins. DS21348 and DS3150 RLOS LEDs (DS15 and DS13
red) will be lit.
Following are several basic system initializations.
Basic DS33R11 Initialization
This section covers two basic methods for configuring the DS33R11.
1. Device-Driver Based Configuration. If the pins J09.4+J09.6 are jumpered, the device driver autoconfigures
the DS33R11 upon power-up. This enables traffic to pass from the Ethernet port to the serial port. Consult
the device driver documentation for further details.
2. Register-Based Configuration. Launch ChipView.exe and select Register View. When prompted for a
definition file, pick the file named DS33Z11.def. Three definition files will load: DS33Z11 control, DS33Z11
port, and DS2155 transceiver. Go to the File menu and select File→Memory Config File→Load .MFG file.
When prompted, select the file named basic_config.mfg. Following this, load the file
e1_gapclk_crc4_hdb3_nocas.ini using the menu selection File→Initalization Config File→Load .INI file.
Additional Configuration for DS33R11
• Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on.
• Place a loopback connector at the T1E1 network side; RLOS LED DS05 should go out.
• At this point any packets sent to the DS33R11 are echoed back. Incoming packets (i.e., ping) should cause the
RX LED to blink, after which the TX LED should also blink.
DS33R11DK/DS33ZH11DK
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Basic DS33ZH11 Initialization
This section covers the EEPROM methods for configuring the DS33ZH11.
1) If the HWMODE jumper is installed, the DS33ZH11 will retrieve configuration settings from the on-board
EEPROM during power-up.
2) Select which serial device to use: either the DS3150 T3E3 LIU or the DS21348 T1E1 LIU can be selected. In
making this selection the backplane jumpers JP05–JP08 must be installed to select between the two serial
devices. Connecting pins 2+3 of each jumper selects the DS3150, connecting pins 1+2 of each jumper selects
the DS21348.
3) Configure the serial device as shown in Table 2.
Additional Configuration for DS33ZH11
• Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on.
• Place a loopback connector at the network side; the RLOS LED should go out. The RLOS LED is DS15 for
T1E1 and DS13 for T3E3.
• At this point any packets sent to the DS33ZH11 are echoed back. Incoming packets (i.e., ping) should cause
the RX LED to blink, after which the TX LED should also blink.
Monitor and Capture Ethernet Traffic
• Although ping is mentioned, it is not recommended. The ping command goes through the computer’s TCPIP
stack, and sometimes is not sent out the PC’s network connector (i.e., if the PC’s ARP cache is out of date).
Additionally, ping requires two PCs, as a PC with only one adapter cannot ping itself (a local ping gets sent to a
local host instead of out the connector). However, note that ping is still a valuable test once the prototyping
stage is complete.
• Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited demo
is available at the website www.tamos.com/products/commview.
• Ethereal is an excellent (and free) packet capture utility. Download at www.ethereal.com.
• Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This allows
for end-to-end testing using a single PC. When using two adapters, the PC has a different IP address for each
adapter. Test equipment allows selection of either adapter. Operating system-based network traffic is sent out
the default adapter. Typically, this is the adapter that has recently had connection to a live network.
DS33R11DK/DS33ZH11DK
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LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS
The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board, from top to bottom then left to right
(with the board held so that the RS232 connector is on the left edge).
Table 2. Main Board PC Board Configuration
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION
GROUND
(banana plug) Power supply ground — 2
VDD 3.3V
(banana plug) Power supply VDD — 2
System power. Always connected
to power supply. Connectors are
provided at the top left and bottom
right of board. Connect either set to
power supply.
J01 JTAG — 17
JTAG interface for Lattice EC3
FPGA.
J02 RS-232 DB9
connector — 14
RS-232 DB9 connector, operates in
ASCII mode at 57.6K baud, 8, N, 1.
SW01 Reset 12 Drives reset controller U01.
DS01 LED — 15
Displays interrupt status of
DS33R11 (lit when interrupt is
asserted).
DS02 LED 7
Displays Queue overflow status of
DS33R11 (lit when Queue
overflows).
J04 OnCe BDM — 14 Debug connector for processor.
J03 Flash VPP 3.3V 14
Jumper for driving MMC2107 flash
VPP to 5V .
J05 JTAG — 10
JTAG interface for DS2155 portion
of DS33R11.
J06 JTAG — 11
JTAG interface for DS33Z11
portion of DS33R11.
Y01 Clock — 11
Oscillator for DS2155 portion of the
DS33R11.
J07, J08 Addr / Dat — 16 Address and Databus Test points
for DS33R11.
J09
Configuration pins
(See next two rows
for details.)
Schematic
Page16
Configuration switches for selecting device driver
behavior. Additional detail given below.
J09.2+J09.4 Removed Not installed
Pin J09.2 has been removed. Jumpering this pin to
J09.4 causes a conflict with J09.6 FPGA pin.
J09.4+J09.6 Driver Enable Installed
Enables device driver and interrupt handler when
jumper is installed.
J09.8+J09.10 RCLK select (FPGA) User selection
Causes device to select serial link TCLK = RCLK
when jumpered. When not jumpered TCLK =
MCLK.
Y02 Ethernet PHY Clock — 3 25.000MHz clock for DS33R11
Ethernet PHY.
JP03 Clock select
Pins 1+2
Jumpered 3
Must be set with pins 1+2
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
J10 Jumper Installed 10
Connects DS33R11 receive serial
lines.
J11 Jumper Installed 10
Connects DS33R11 transmit serial
lines.
DS33R11DK/DS33ZH11DK
13 of 44
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION
JP01 3-pin jumper
Pins 2+3
jumpered 10 Drives DS33R11 TDEN pin to
VCC.
JP02 3-pin jumper
Pins 2+3
jumpered 10 Drives DS33R11 RDEN pin to
VCC.
J18 Test points
Pins 9+10 and
5+6 jumpered 10
Test points, connecting RCLK and
TCLK to channel clock pins of
transceiver.
J12, J13 Test points — 11 Test points for integrated
transceiver of DS33R11.
J14, J15, J16 Jumpers Not installed 4
Installation forces Ethernet PHY
mode. When not installed the PHY
autonegotiates its settings.
DS06, DS07,
DS08 LED — 4
Activity LEDs for Ethernet PHY. Tx
lights when PHY sends a packet;
Link lights when the PHY has found
a link partner.
DS10, DS11,
DS09 LED — 4
Ethernet PHY mode LEDs. Used
for display of Speed, Duplex, and
Collision.
J21 LAN network
connection — 5 RJ45 connector for Ethernet PHY.
J22, J23 Test points — 4 Test points for MII interface
between PHY and DS33R11.
J19, J20 J24 WAN Network
Connection — 11
T1E1 coax and RJ45 connectors
for network.
J17, J25 Jumper Not installed 11 Connects adjacent coax connector
to ground.
Y03 Clock — 10
100MHz SDRAM clock for
DS33R11.
J28
Configuration pins
(See next 10 rows for
details.)
Schematic
Page 23
Pin bias for DS3150. When not jumpered, this pin is
pulled to ground, jumper drives pin to VCC. A basic
description of the pin function is given below. Refer
to the data sheet for full detail.
J28.20 DS3150 pin (ZCSE) Not installed
0 = B3ZS/HDB3 encoder/decoder enabled (NRZ
interface enabled)
1 = B3ZS/HDB3 encoder/decoder disabled (bipolar
interface enabled)
J28.18 DS3150 pin (TTS) Installed
0 = tri-state the transmit output driver, disable the
jitter attenuator in the transmit path
1 = enable the transmit output driver, disable the
jitter attenuator in the transmit path
J28.16 DS3150 pin (TESS) Installed 0 = E3
1 = T3 (DS3)
J28.14 DS3150 pin (TDS1) Not installed
J28.12 DS3150 pin (TDS0) Not installed
00=Transmit normal data clocked in on
TPOS/TNRZ and TNEG
11=Transmit PRBS
J28.10 DS3150 pin (RMON) Not installed
0 = disable the monitor preamp, disable the jitter
attenuator in the receive path
1 = enable the monitor preamp, disable the jitter
attenuator in the receive path
J28.8 DS3150 pin (LBKS) Installed 0 = analog loopback enabled
1 = no loopback enabled
J28.6 DS3150 pin (LBO) Installed 0 = cable length 225ft
1 = cable length < 225ft
DS33R11DK/DS33ZH11DK
14 of 44
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION
J28.4 DS3150 pin (ICE) —
0 = Normal RCLK/Normal TCLK: update
RPOS/RNRZ and RNEG/RLCV on falling edge of
RCLK; sample TPOS/TNRZ and TNEG on rising
edge of TCLK
1 = Normal RCLK/Inverted TCLK: update
RPOS/RNRZ and RNEG/RLCV on falling edge of
RCLK; sample TPOS/TNRZ and TNEG on falling
edge of TCLK
J28.2 DS3150 pin (EFE) Not installed 0 = enhanced features disabled
1 = enhanced features enabled
JP09 Clock selection
Pins 3+2
jumpered 23
Selects DS3150 MCLK. Jumper
pins 1+2 for MCLK = RCLK; jumper
pins 3+2 for MCLK = OSC_YB01.
DS12, DS13,
DS14 LED — 23
DS3150 LEDs for PRBS, LOS and
DM.
J38, J39 BNC — 23 DS3150 BNC network interface.
JP05–JP08 Serial backplane User config 18
Jumper pins 1+2 to select
DS21348 T1E1, jumper pins 2+3 to
select DS3150.
J29
Configuration pins
(See next 10 rows for
details.)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J29.1 DS21348 pin
(CS_EGL)
0 = -12dB (short haul)
1 = -43dB (long haul)
J29.3 DS21348 pin
(RD_ETS)
0 = E1
1 = T1
J29.5 DS21348 pin
(WR_NRZ)
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG
outputs a positive-going pulse when device
receives a BPV, CV, or EXZ
J29.7 DS21348 pin
(ALE/SCLKE)
0 = disable 2.048MHz synchronization transmit and
receive mode
1 = enable 2.048Hz synchronization transmit and
receive mode
J29.9 DS21348 pin (VSM) Should be tied low for 3.3V operation.
J29.11 DS21348 pin (LO) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J29.13 DS21348 pin (DJA) 0 = jitter attenuator enabled
1 = jitter attenuator disabled
J29.15 DS21348 pin
(JAMUX)
E1 (ETS = 0) JAMUX
MCLK = 2.048MHz 0
T1 (ETS = 1)
MCLK = 2.048MHz 1
MCLK = 1.544MHz 0
J29.17 DS21348 pin (JAS) 0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
J29.19 DS21348 pin (HBE)
Schematic
Page 25
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
DS33R11DK/DS33ZH11DK
15 of 44
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION
J31
Configuration pins
(See next 10 rows for
details)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J31.1 DS21348 pin (MM1)
J31.3 DS21348 pin (MM0)
Monitor mode selection. See Table 2-11 in the
DS21348 data sheet.
J31.5 DS21348 pin
(LOOP1)
J31.7 DS21348 pin
(LOOP0)
Loop 1, Loop 0:
11 = RLB
10 = LLB
01 = ALB
J31.9 DS21348 pin (TX1)
J31.11 DS21348 pin (TX0) Transmit data control (pattern vs. TPOS/TNEG)
J31.13 DS21348 pin (TPD)
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the
TTIP and TRING pins
J31.15 DS21348 pin (CES)
0 = update RNEG/RPOS on rising edge of RCLK;
sample TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK;
sample TPOS/TNEG on rising edge of TCLK
J31.17 DS21348 pin
(TEST) Set high to tri-state all outputs and I/O pins.
J31.19 DS21348 pin
(PBTS/RT0)
Schematic
Page 25
Selects receive termination in conjunction with RT1.
J36
Configuration pins
(See next three rows
for details.)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J36.2 DS21348 pin (L1) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J36.4 DS21348 pin (L2) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J36.6 DS21348 pin (RT1)
The silkscreen on this pin is mislabeled. Should
read RT1 with a function of selecting receive
termination.
JP10 Clock selection 25 —
DS15 LED 25 —
J40, J41 Network connection 24 —
J27 DS33ZH11 pin
(MODEC1) 21 —
J26 DS33ZH11 pin
(HWMODE) 21 —
JPB01 Jumper 21 —
J30, J33 Test points
Schematic
Page 25
26 Test points for MII interface
between PHY and DS33ZH11.
JP11 Clock selection
Pins 2+3
jumpered 18
Must be set with pins 1+2
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
J32, J35, J34 Jumpers Not installed 26
Installation forces Ethernet PHY
mode. When not installed, the PHY
autonegotiates its settings
DS33R11DK/DS33ZH11DK
16 of 44
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION
DS19, DS20,
DS21 LED — 19
Activity LEDs for Ethernet PHY. Tx
lights when PHY sends a packet;
Link lights when the PHY has found
a link partner.
DS16, DS17,
DS18 LED — 19
Ethernet PHY mode LEDs. Used
for display of Speed, Duplex, and
Collision.
SW02 Reset button — 19 —
GROUND
(banana plug) Power supply ground — 2 Redundant power supply
connection (see top left of board).
VDD 3.3V
(banana plug) Power supply VDD — 2 Redundant power supply
connection (see top left of board).
YB01 DS3150 MCLK — 23 44.736MHz, for use with DS3150 in
T3 mode (bottom side of PC board)
YB02 DS21348 MCLK — 25
1.544MHz, for use with DS21348 in
T1 mode (bottom side of PC board)
YB04 Ethernet clock — 18
25.000MHz driver for DS33ZH11
Ethernet PHY (bottom side of PC
board).
YB03 SDRAM clock — 21
100MHz SDRAM clock for
DS33ZH11 (bottom side of PC
board).
YB05 Spare oscillator — 25
2.048MHz, for use with DS21348 in
E1 mode (bottom side of PC
board).
Y05 Spare oscillator — 23
34.368MHz for use with DS3150 in
E3 mode (bottom side of PC
board).
ADDRESS MAP (ALL CARDS)
The external device address space begins at 0x81000000. All offsets given below are relative to this offset.
Table 3. Overview of Daughter Card Address Map
OFFSET DEVICE DESCRIPTION
0X0000 to
0X0087 FPGA Processor board identification
0X1000 to
0X1FFF
DS33R11 Ethernet to Serial Engine. Uses
CS_X1.
0X4000 to
0X4FFF
DS33R11
T1E1 portion of DS33R11. Uses CS_X4.
Registers in the DS33R11 can be easily modified using the ChipView host-based user-interface software with the
definition files previously mentioned.
DS33R11 INFORMATION
For more information about the DS33R11, refer to the DS33R11 data sheet available on our website at
www.maxim-ic.com/DS33R11.
DS33R11DK/DS33ZH11DK
17 of 44
DS33R11DK/DS33ZH11DK INFORMATION
For more information about the DS33R11DK/DS33ZH11DK, including software downloads, refer to the data sheet
available on the our websit e at www.maxim-ic.com/DS33R11DK.
TECHNICAL S UPPORT
For additional technical support, go to www.maxim-ic.com/support.
SCHEMATICS
The DS33R11/DS33ZH11DK schematics are featured in the following pages. As this is a hierarchal schematic
some explanation is in order. The board is composed of two top-level hierarchal blocks: the DS33R11 block and
the DS33ZH11, both of these are nested hierarchy blocks. The DS33R11 hierarchy block contains individual
hierarchy blocks for the Ethernet PHY, DS33R11 and microprocessor portions of the design. The DS33ZH11
hierarchy block contains individual hierarchy blocks for the Ethernet PHY, DS33ZH11, T1E1 LIU, and the T3E3 LIU
portions of the design.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
DS21348 LIU BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGES 24-25
ETHERNET PHY
PAGE 3 SYMBOL
SCHEMATIC
PAGES 04-05
DS3150 LIU BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGE 23
ETHERNET PHY
PAGE 18 SYMBOL
SCHEMATIC
PAGES 26-27
DS33ZH11 BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGES 20-22
DS33ZH11 BLOCK
PAGE 3 SYMBOL
SCHEMATIC
PAGES 06-11
µP BLOCK
PAGE 3 SYMBOL
SCHEMATIC
PAGES 12-17
DS33R11 SECTION
PAGE 1 TOP LEVEL
OF DESIGN
CONTAINS 34
HIERARCHY
BLOCKS
SCHEMATIC
PAGES 18-27
DS33R11 SECTION
PAGE 1 TOP LEVEL
OF DESIGN
CONTAINS 3
HIERARCHY
BLOCKS
SCHEMATIC
PAGES 03-17
DS33RZH11 PC BOARD LAYOUT & SCHEMATIC HIERARCY BLOCK PAGE LISTING
PAGE 01: DS33R11 AND DS33ZH11 DESIGN TOP LEVEL HIERARCHY BLOCKS
PAGE 03: HIERARCHY BLOCKS FOR DS33R11, PROCESSOR AND ETHERNET
ONLY SIGNALS WITH IMPORT/OUTPORT CONNECTORS HAVE CONNECTION OUTSIDE THE
PAGES 18-19: HIERARCHY BLOCKS FOR DS33ZH11, ETHERNET AND SERIAL (WAN) INTERFACE
PAGES 04-05: ETHERNET PHYSICAL INTERFACE (PHY)
PAGES 06-11: DS33R11
PAGES 12-17: PROCESSOR CARD
PAGES 20-22: DS33ZH11
PAGE 23: DS3150 LINE INTERFACE UNIT (LIU)
PAGES 24-25: DS21348 LINE INTERFACE UNIT (LIU)
PAGES 26-27: ETHERNET PHYSICAL INTERFACE (PHY)
DS33ZH11 TOP LEVEL
HIERARCHY BLOCK
PAGES 18-27
HIERARCHY BLOCK
PAGES 03-17
DS33R11 TOP LEVEL
NOTES: EACH HIERARCHY BLOCK IS INDEPENDENT OF THE NEXT.
PAGE 02: DECOUPLING /MOUNTING HOLES
DS33ZH11 DESIGN
DS33R11 DESIGN:
CONTENTS
HIERARCHY BLOCK. THESE SIGNALS APPEAR AS PINS ON THE HIERARCHY BLOCK CONNECTOR
PRINTED Fri Sep 23 11:01:48 2005
BLOCK NAME: _ztopdn_. PARENT BLOCK: <CON_PARENT_NAME>
01/05/2005
1/2(BLOCK)
1/27(TOTAL)
STEVE SCULLY
DS33ZH11-R11DK01A0
FPGA_ZHSPICS
FPGA_ZHSPISCK
FPGA_ZHMISO
FPGA_ZHMOSI
FPGA_SPICS
ZMISO
ZSPISCK
ZMOSI
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
_ds33zh11dk_design
ZMOSI
ZSPISCK
ZMISO
FPGA_SPICS
_ds33r11dk_design
FPGA_ZHMOSI
FPGA_ZHMISO
FPGA_ZHSPISCK
FPGA_ZHSPICS
GROUND TESTPOINTS
2/2(BLOCK)
STEVE SCULLY
DS33ZH11-R11DK01A0
2/27(TOTAL)
01/05/2005
BLOCK NAME: _ztopdn_. PARENT BLOCK: <CON_PARENT_NAME>
B
A
B
A
B
A
B
A
2
1
JB05
2
1
JB02
2
1
JB01
2
1
JB04
CB151
CB175
CB74
CB125
CB127
2
1
C14
1
H03
1
H04
1
HB01
1
H01
1
HB03
1
H02
1
H05
1
HB02
1
H06
1
2
DB01
2
1
CB58
2
1
CB64
2
1
CB131
2
1
CB22
2
1
CB20
2
1
CB54
2
1
C03
2
1
CB47
2
1
CB48
2
1
C17
2
1
C20
2
1
CB132
2
1
CB62
2
1
C22
2
1
CB32
2
1
CB19
2
1
CB28
2
1
CB59
2
1
CB60
2
1
CB124
2
1
CB61
2
1
CB21
2
1
CB27
2
1
CB30
2
1
CB31
2
1
CB10
2
1
CB139
2
1
CB38
2
1
CB118
2
1
CB140
2
1
CP01
2
1
CP02
2
1
CP03
2
1
C01
2
1
C28
2
1
CB136
2
1
CB03
C19
CB52
CB100
C16
C18
C12
C08
CB51
CB17
C09
CB75
CB50
CB06
CB18
CB01
CB149
CB150
CB134
CB133
CB53
CB57
CB55
CB107
CB16
CB13
CB116
CB09
CB15
CB35
CB14
CB34
CB05
CB04
CB46
CB138
CB02
CB143
CB142
C23
CB141
CB07
CB147
CB39
CB11
C21
C24
CB145
CB144
CB08
CB137
CB135
1
GND_TPP05
1
GND_TPP04
1
GND_TPP03
1
GND_TPP02
1
GND_TPP09
1
GND_TPP08
1
GND_TPP07
1
GND_TPP06
1
GND_TPB01
1
GND_TPP13
1
GND_TPP12
1
GND_TPP11
1
GND_TPP10
1
GND_TP02
1
GND_TPP16
1
GND_TPP15
1
GND_TPP14
1
GND_TPP20
1
GND_TPP19
1
GND_TP03
1
GND_TPP18
1
GND_TPP17
1
GND_TPP21
1
GND_TPP22
1
GND_TP01
1
GND_TPP23
1
GND_TPP01
10UF
.1UF
RED
BLACK BLACK
RED
10UF
470UF
1.00STANDOFF_NUT
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
0.1UF
0.1UF
10UF
1 1
10UF
1 1
1.00STANDOFF_NUT
10UF
10UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
470UF
470UF
10UF
10UF
470UF
470UF
470UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
470UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
10UF
.1UF
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
CONN_BANANA_2P
A
B
CONN_BANANA_2P
A
B
CONN_BANANA_2P
A
B
V3_3
CONN_BANANA_2P
A
B
V3_3
44 4 4 44444
V3_3
V3_3
V3_3
PAGES 12-17 PAGES 04-05
PAGES 06-11
PROCESSOR HIERARCHY BLOCK R11 HIERARCHY BLOCK MII ETHERNET HIERARCHY BLOCK
DS33R11 DESIGN KIT
PAGE NUMBERS (BOTTOM RIGHT) ARE LISTED BY BOTH THE PAGE NUMBER IN THE BLOCK, AND BY THE PAGE NUMBER WITHIN THE ENTIRE DESIGN
NOTES: ALL HIERARCHY BLOCK NAMES END IN _DN. PINS ON HIERARCHY BLOCKS DO NOT HAVE PIN NUMBERS (BUT PINS ON SYMBOLS DO).
SIGNALS INSIDE AHIERARCHY BLOCK ARE LOCAL TO THAT BLOCK -THE SIGNAL TEMP IN BLOCK_A_DN IS DIFFERENT THAN TEMP IN BLOCK_B_DN.
CROSS REFERENCE INDICATORS ARE REFERENCEING AGIVEN NET TO OTHER PAGES IN THE DESIGN (PAGE NUMBER GIVEN IS ACCORDING TO ENTIRE DESIGN, NOT THE CURRENT BLOCK)
DS33ZH11-R11DK01A0 01/05/2005
STEVE SCULLY
BLOCK NAME: _ds33r11dk_design. PARENT BLOCK: \_ztopdn_\
3/27(TOTAL)
1/1(BLOCK)
PRINTED Sat Sep 17 15:05:43 2005
TXD0
MII_CLK
MDC
MDIO
TXD1
TXD2
TXD3
TX_CLK
RXDV
COL_DET
RX_CRS
RX_ERR
RX_CLK
LED_DPLX_ADD0
LED_COL_ADD1
LED_GDLINK_ADD2
LED_RX_ADD4
LED_TX_ADD3
RXD0
RXD3
RXD2
RXD1
TX_EN
RESET
CS_ETH
CS_SER
RD
DAT<7..0>
ADDR<9..0>
REF_CLK_IN
MDIO
RST_SERIAL
RST_ETH
COL_DET
TXD0
WR
TX_EN
INT
RXD0
RXD1
RXD2
RXD3
RX_CLK
RX_CRS
RX_ERR
RXDV
TXD1
REF_CLKO_PN
TXD2
TXD3
TX_CLK
MDC
FPGA_ZHSPISCK
FPGA_ZHSPICS
FPGA_ZHMOSI
RESET
RD_DUT
WR_DUT
INT3
CS_X1
CS_X2
CS_X5
INT4
INT5
CS_X3
CS_X4
D_DUT<7..0>
RESET_AH
INT2
a_dut_<9..0>
FPGA_ZHMISO
RESET
TX_EN
RXD1
RXD2
RXD3
RXD0
LED_TX_A3
LED_RX_A4
LED_GDLINK_A2
LED_COL_A1
LED_DPLX_A0
RX_CLK
RX_ERR
RX_CRS
COL_DET
RXDV
TX_CLK
TXD3
TXD2
TXD1
MDIO
MDC
TXD0
I25
DAT<7..0>
Y02
JP03
R04
R05
DS08
DS06
RB57
RB68
DS07
RB66
RB55
RB67
DS09
RB56
RB75
RB72
DS11
RB71
RB76
FPGA_ZHMOSI
FPGA_ZHSPICS
FPGA_ZHSPISCK
FPGA_ZHMISO
ADDR<9..0>
WR
RD
CS_ETH
INT
I28
I34
RST_SERIAL
RESET
REF_CLKO
REF_CLK_IN
MDC
RESET
MDIO
CS_SER
I32
NPOP-25.000MHZ_3.3V
I30
30
30
1
I20
AMBER
5.1K
1
LED_GDLINK_A2
5.1K
1
1
330
AMBER
1
5.1K
1
330
1
1
1
AMBER
1
330
5.1K
1
1
330
GREEN
330
1
5.1K
1
1
RED
LED_DPLX_A0
LED_COL_A1
LED_TX_A3
LED_RX_A4
GND
V3_3
I4
I11
I15
I19
I21
I22
1
2
1
2
1
2
1
2
1
3
2
1
8
4 5
1
2
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
OUT
OUT
OUT
_motprocrescard_dn
FPGA_ZHMISO
a_dut_<9..0>
INT2
RESET_AH
D_DUT<7..0>
CS_X4
CS_X3
INT5
INT4
CS_X5
CS_X2
CS_X1
INT3
WR_DUT
RD_DUT
RESET
FPGA_ZHMOSI
FPGA_ZHSPICS
FPGA_ZHSPISCK
VCC
1
OSC
GND OUT
V3_3
_z11andlan_dn
MDC
TX_CLK
TXD3
TXD2
REF_CLKO_PN
TXD1
RXDV
RX_ERR
RX_CRS
RX_CLK
RXD3
RXD2
RXD1
RXD0
INT
TX_EN
WR
TXD0
COL_DET
RST_ETH
RST_SERIAL
MDIO
REF_CLK_IN
ADDR<9..0>
DAT<7..0>
RD
CS_SER
CS_ETH
_mii_wan_dn
RESET
TX_EN
RXD1
RXD2
RXD3
RXD0
LED_TX_ADD3
LED_RX_ADD4
LED_GDLINK_ADD2
LED_COL_ADD1
LED_DPLX_ADD0
RX_CLK
RX_ERR
RX_CRS
COL_DET
RXDV
TX_CLK
TXD3
TXD2
TXD1
MDIO
MDC
MII_CLK
TXD0
V3_3
V3_3
BEGINNING OF MII ETHERNET HIERARCHY BLOCK
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
BE PLACED CLOSE TO PIN
C1 AND RBIAS MUST
COMPONETS FOR
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
0.2 BETWEEN CONNECTORS.
ALLOW USE OF ADIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4PORTS MUST BE PLACED WITH EQUAL SPACING AND ACOMMONCENTER LINE
STRAP ADAPTING OPTION OF DP83847
ANALOG SUPPLY CAPS
TO BE PLACED CLOSE TO
PIN 14 OF PHY
BLOCK NAME: _mii_wan_dn. PARENT BLOCK: \_ds33r11dk_design\
4/27(TOTAL)
PRINTED Fri Sep 23 11:01:50 2005
DS33ZH11-R11DK01A0
STEVE SCULLY
01/05/2005
1/2(BLOCK)
RESERVED12
RESERVED13
RESERVED16
RESERVED17
RESERVED18
GND1
GND2
GND3
GND4
GND5
RESERVED10
RESERVED11
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
VDD/IO_VDD1
VDD/IO_VDD2
VDD/ANA_VDD
VDD1
VDD2
VDD3
RESERVED2
RESERVED1
RBIAS
RESET*
C1
X2
X1
AN_0
AN_1
AN_EN
LED_SPEED
LED_RX/PHYAD4
LED_COL/PHYAD1
LED_DPLX/PHYAD0
MDIO
MDC
RESERVED3
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
RESERVED15
RESERVED14
0.1UF
CM98
CM32
0.1UF
CP15
0.1UF
CM82
CP09
10UF
AN0
AN1
AN_EN
?
AMBER
CM77
AN_V3_3
CP08
CM75
CM29
CM89
JP24
JP25
RM36
RM35
RM34
TPP01
RM24
TPP02
RP11
UP15
CP07
CM78
RM02
LED_DPLX_ADD0
LED_TX_ADD3
10UF
10.0K
RESET
0.1UF
MII_CLK
LED_COL_ADD1
LED_RX_ADD4
RBIAS
AN_V3_3
330
1
C1PIN
0.1UF
0.1UF
5.1K
TX_EN
TX_CLK
COL_DET
RX_CRS
RXD3
RXD2
RXD1
RX_CLK
RX_ERR
RXD0
RXDV
5.1K
MDC
MDIO
30
TXD1
TXD0
TXD3
TXD2
0.1UF
0.1UF
10UF
CP17
10UF
10UF
0.1UF
CM67
LED_SPEED<1>
LED_GDLINK_ADD2
5.1K
JMP_2
JMP_2
JMP_2
1
?
?
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
SHOULD BE PLACED CLOSE TO PHY
END OF MII ETHERNET HIERARCHY BLOCK
CAPS FOR XFRM CENTER TAP
BLOCK NAME: _mii_wan_dn. PARENT BLOCK: \_ds33r11dk_design\
5/27(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33ZH11-R11DK01A0 01/05/2005
SH1
P2
P8
P6
P3
P4
SH2
P1
P5
COL
TXD<2>
RD+
RD-
RXD<3>
TXD<3>
RX_CLK
RXD<1>
RXD<0>
RXD<2>
TD-
TD+
CRS/LED_CFG*
TX_CLK
TX_ER
TX_EN
TXD<0>
TXD<1>
RX_DV
RX_ER/PAUSE_EN*
30
RXD0
49.9
TD_N
.1UF
.1UF
RXDV
TD_P
TD_NRD_N
RD_P
COL_DET
RX_CRS
30
30
RXD3
RXD2
RXD1
30
49.9
54.9
54.9
.1UF
RD_N
TD_P
RD_P
SYM_1
TXD3
30
30
TXD2
TXD1
TXD0
TX_EN
RX_ERR
30
30
TX_CLK
RX_CLK
UP15
CM59
JP21
RM10
CP12
RM06
RM21
RM03
RP08
RM05
RM08 RP06
RM13
RM09
CM63
RM12
RM14
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
BEGINNING OF DS33R11 HIERARCHY BLOCK
DS33ZH11-R11DK01A0
STEVE SCULLY
1/6(BLOCK)
6/27(TOTAL)
01/05/2005
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
RCLK
A<6>
A<9>
A<8>
TSER
A<3>
A<5>
A<7>
D<0>
D<6>
D<5>
D<4>
A<4>
TCHBLK
TPOSI
TPOSO
TNEGO
TESO
TDATA
BPCLK
RCHCLK
RCHBLK
MCLK
JTDI
TCHCLK
RSER
RSIG
RSIGF
RFSYNC
RLOS/LTC
RMSYNC
RNEGI
RNEGO
RPOSI
RPOSO
RSYSCLK
RTIP
RRING
TRING1
TRING2
TTIP1
TTIP2
RCL
LIUC
RCLKI
RCLKO
RDATA
D<2>
D<3>
TNEGI
D<7>
D<1>
A<2>
TSYSCLK
JTCLK
WR*
8XCLK
SER_CS*
XTALD
TSTRST
TEST1
TEST2
JTRST
TSIG
RSYNC
TSYNC
TSSYNC
TCLKO
TCLKI
TCLK
RD*
JTMS
ETH_CS*
INT*
A<1>
A<0>
JTDO
SPI_CS
TPB07
2
1
DS05
RB48
TPB09
TPB08
J4
C11
R2
R1
E4
C1
C4
A5
B4
E3
T2
T1
E1
B3
D3
C3
D6
C6
D4
A4
C2
D1
D2
G1
A2
A9
D7
K1
F4
G4
P3
L3
H2
M1
N3
J3
N2
L4
U3
N1
A3
H3
B11
M3
M4
G3
B5
G2
A1
H4
B2
B8
B9
C5
B6
A6
A10
A11
B12
A12
C13
B13
A13
C14
B14
A14
B1
C15
C16
B16
A16
C17
B17
A17
C18
B18
A18
K4
U09
INT
S_RLOS
S_RLOS
ZSPICS
S_JTDO
CS_ETH
S_JTMS
RD
S_TCLK
S_TCLKI
S_TCLKO
S_TSSYNC
S_TSYNC
S_RSYNC
S_TSIG
S_JTRST
RST_SERIAL
CS_SER
S_8XCLK
WR
S_JTCLK
S_TSYSCLK
S_TNEGI
S_RDATA
S_RCLKO
S_RCLKI
S_LIUC
S_RCL
RRING
RTIP
S_RSYSCLK
S_RPOSO
S_RPOSI
S_RNEGO
S_RNEGI
S_RMSYNC
S_RFSYNC
S_RSIGF
S_RSIG
S_RSER
S_TCHCLK
S_JTDI
S_MCLK
S_RCHBLK
S_RCHCLK
S_BPCLK
S_TNEGO
S_TPOSO
S_TPOSI
S_TCHBLK
S_TSER
S_RCLK
3
2
1
TTIP
7
0
5
8
6
4
7
9
1
2
3
4
5
6
0
ADDR<9..0>
DAT<7..0>
330
RED
S_TDATA
S_TESO
TRING
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
CONTROL &TRANSCEIVER PORT
DS33R11_U1
SPI_CS
JTDO
A<0>
A<1>
INT*
ETH_CS*
JTMS
RD*
TCLK
TCLKI
TCLKO
TSSYNC
TSYNC
RSYNC
TSIG
JTRST
TEST2
TEST1
TSTRST
XTALD
SER_CS*
8XCLK
WR*
JTCLK
TSYSCLK
A<2>
D<1>
D<7>
TNEGI
D<3>
D<2>
RDATA
RCLKO
RCLKI
LIUC
RCL
TTIP2
TTIP1
TRING2
TRING1
RRING
RTIP
RSYSCLK
RPOSO
RPOSI
RNEGO
RNEGI
RMSYNC
RLOS/LTC
RFSYNC
RSIGF
RSIG
RSER
TCHCLK
JTDI
MCLK
RCHBLK
RCHCLK
BPCLK
TDATA
TESO
TNEGO
TPOSO
TPOSI
TCHBLK
A<4>
D<4>
D<5>
D<6>
D<0>
A<7>
A<5>
A<3>
TSER
A<8>
A<9>
A<6>
RCLK
OUT
IN
IN
IN
IO
IN
STEVE SCULLY
7/27(TOTAL)
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
01/05/2005
2/6(BLOCK)
DS33ZH11-R11DK01A0
ZJTCLK
RDEN0
RSER0
TCLKI0
TDEN0
RCLKI0
TSER0
H10S0
HWMODE
RST*
RMIIS
MODEC0
MODEC1
AFCS
COL0
CRS0
REFCLK
REFCLKO
RXERR0
RXDV0
QOVF
SWE*
ZJTDI
SDATA<27>
SDATA<28>
SDATA<29>
SDATA<30>
SDATA<26>
SDATA<25>
SDATA<24>
SDATA<23>
SDATA<22>
SDATA<21>
SDATA<20>
SDATA<19>
SDATA<18>
SDATA<17>
SDATA<16>
SDATA<15>
SDATA<14>
SDATA<13>
SDATA<12>
SDATA<11>
SDATA<10>
SDATA<9>
SDATA<8>
SDATA<7>
SDATA<6>
SDATA<5>
SDATA<4>
SDATA<3>
SDATA<1>
RXD0_3
RXD0_1
RXD0_0
RXD0_2
RXCLK0
ZJTDO
SDATA<31>
SDA<3>
SDA<4>
SDA<5>
SDA<6>
SDA<7>
SDA<9>
SDA<8>
SDA<10>
SDA<11>
SDA<2>
SDA<1>
SDA<0>
SRAS
SBA0
SBA1
SCAS*
SCS*
SDCLKI
SDCLKO
STEN
STMD
SMASK1
SMASK3
SMASK2
TXCLK0
TXD0_1
TXD0_3
SMASK0
TXD0_2
TXD0_0
SDATA<0>
SDATA<2>
MDIO
MDC
TXEN0
ZJTMS
ZJTRST*
FULLH0
DCEDTE
R03
1
TP01
RB20
DS02
C7
C8
B7
C9
A7
F20
E19
E20
F18
F19
H19
E2
D5
F1
W10
E18
D18
W9
V15
V16
V7
Y6
Y8
V8
W16
W17
V17
W19
Y18
T20
T19
U20
W20
U19
Y20
V19
Y19
V18
Y17
Y16
W1
W3
V1
V3
V2
V4
W4
V6
W6
V5
W5
Y3
Y5
Y2
Y4
W2
W11
V14
Y10
V12
Y12
W13
V13
Y14
W15
Y15
W12
W14
V10
W7
V11
Y11
K18
K19
M18
L20
L19
L18
M20
A8
H1
G19
A20
A19
P2
F2
H18
B20
B19
C20
C19
C10
N20
N19
G20
M19
N18
K20
U09
RB70
RB96
RB77
RB80
RB82
RB81
RB79
SD_CLKO
SD_WE
SD_RAS
TX_CLK
DCEDTES
FULLDS
Z_JTRST
Z_JTMS
MDC
SD_DQM0
SD_DQM2
SD_DQM3
SD_DQM1
SCANMOD
SCANEN
SD_CLKI
SD_CS
SD_CAS
SD_BA1
SD_BA0
Z_JTDO
RX_CLK
RXD2
RXD0
RXD1
RXD3
Z_JTDI
QOVF
RXDV
RX_ERR
REF_CLKO_PN
REF_CLK_IN
RX_CRS
COL_DET
AFCS
MODEC1
MODEC0
RMIIMIIS
HWMODE
H10S
Z_RCLKI
Z_TDEN
Z_TCLKI
Z_RSER
Z_RDEN
Z_JTCLK
QOVF
330
TXD2
SD_A<11..0>
RST_ETH
30
TXD3
TXD1
TXD0
30
0
1
3
2
4
6
5
8
7
9
10
11
31
30
29
28
27
26
25
24
23
22
21
20
30
1
0
30
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
2
3
4
Z_TSER
SD_DQ<31..0>
30
30
TX_EN
MDIO
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IO
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
ETHERNET TO SERIAL ENGINE
DS33R11_U1
DCEDTE
FULLH0
ZJTRST*
ZJTMS
TXEN0
MDC
MDIO
SDATA<2>
SDATA<0>
TXD0_0
TXD0_2
SMASK0
TXD0_3
TXD0_1
TXCLK0
SMASK2
SMASK3
SMASK1
STMD
STEN
SDCLKO
SDCLKI
SCS*
SCAS*
SBA1
SBA0
SRAS
SDA<0>
SDA<1>
SDA<2>
SDA<11>
SDA<10>
SDA<8>
SDA<9>
SDA<7>
SDA<6>
SDA<5>
SDA<4>
SDA<3>
SDATA<31>
ZJTDO
RXCLK0
RXD0_2
RXD0_0
RXD0_1
RXD0_3
SDATA<1>
SDATA<3>
SDATA<4>
SDATA<5>
SDATA<6>
SDATA<7>
SDATA<8>
SDATA<9>
SDATA<10>
SDATA<11>
SDATA<12>
SDATA<13>
SDATA<14>
SDATA<15>
SDATA<16>
SDATA<17>
SDATA<18>
SDATA<19>
SDATA<20>
SDATA<21>
SDATA<22>
SDATA<23>
SDATA<24>
SDATA<25>
SDATA<26>
SDATA<30>
SDATA<29>
SDATA<28>
SDATA<27>
ZJTDI
SWE*
QOVF
RXDV0
RXERR0
REFCLKO
REFCLK
CRS0
COL0
AFCS
MODEC1
MODEC0
RMIIS
RST*
HWMODE
H10S0
TSER0
RCLKI0
TDEN0
TCLKI0
RSER0
RDEN0
ZJTCLK
FROM Z11 SYSCLKO
SYNCHRONOUS DRAM
MT48LC4M32B2 -1MEG X32 X4BANKS
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
DS33ZH11-R11DK01A0
STEVE SCULLY
3/6(BLOCK)
01/05/2005
8/27(TOTAL)
VDD4
VDD3
VDDQ6
VDDQ1
CLK
CS*
CKE
CAS*
WE*
DQM<0>
RAS*
DQM<1>
DQM<2>
DQM<3>
BA<0>
BA<1>
A<0>
A<1>
A<3>
A<2>
A<4>
A<6>
A<5>
A<8>
A<7>
A<9>
A<10>
A<11>
DQ<5>
DQ<6>
DQ<7>
DQ<8>
DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<14>
DQ<13>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<20>
DQ<19>
DQ<21>
DQ<23>
DQ<22>
DQ<25>
DQ<24>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
VDDQ5
VDDQ4
DQ<4>
VDD2
VDD1
DQ<2>
DQ<3>
DQ<1>
DQ<0>
DQ<30>
DQ<31>
VSSQ8
VSSQ6
VSSQ7
VSSQ5
VSSQ3
VSSQ4
VSSQ1
VSSQ2
VSS3
VSS4
VSS1
VSS2
VDDQ7
VDDQ8
VDDQ3
VDDQ2
17
84
78
52
46
38
32
12
6
86
72
58
44
81
75
55
49
41
35
9
3
43
29
15
1
19
59
28
71
16
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
20
68
67
18
23
22
21
24
66
65
64
63
62
61
60
27
26
25
UB04
SD_CS
SD_WE
SD_BA1
SD_BA0
SD_RAS
SD_CAS
SD_DQM3
SD_DQM2
SD_DQM1
SD_DQM0
SD_CLKO
SD_A<11..0>
10
SD_DQ<31..0>
8
7
6
5
4
29
28
27
26
25
24
23
22
3
21
20
19
18
17
16
15
14
13
2
12
11
10
9
8
6
7
5
4
3
1
2
30
31
1
0
11
9
0
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MT48LC4M32B2_TSOP_U
VDDQ2
VDDQ3
VDDQ8
VDDQ7
VSS2
VSS1
VSS4
VSS3
VSSQ2
VSSQ1
VSSQ4
VSSQ3
VSSQ5
VSSQ7
VSSQ6
VSSQ8
DQ<31>
DQ<30>
DQ<0>
DQ<1>
DQ<3>
DQ<2>
VDD1
VDD2
DQ<4>
VDDQ4
VDDQ5
DQ<29>
DQ<28>
DQ<27>
DQ<26>
DQ<24>
DQ<25>
DQ<22>
DQ<23>
DQ<21>
DQ<19>
DQ<20>
DQ<18>
DQ<17>
DQ<16>
DQ<15>
DQ<13>
DQ<14>
DQ<12>
DQ<11>
DQ<10>
DQ<9>
DQ<8>
DQ<7>
DQ<6>
DQ<5>
A<11>
A<10>
A<9>
A<7>
A<8>
A<5>
A<6>
A<4>
A<2>
A<3>
A<1>
A<0>
BA<1>
BA<0>
DQM<3>
DQM<2>
DQM<1>
RAS*
DQM<0>
WE*
CAS*
CKE
CS*
CLK
VDDQ1
VDDQ6
VDD3
VDD4
V3_3
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
4/6(BLOCK)
9/27(TOTAL)
RST
SHDN
IN
OUT
GND
SET
OUT
IN
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS17
VSS16
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
1.8VDD8
1.8VDD9
1.8VDD3
1.8VDD6
1.8VDD7
1.8VDD5
1.8VDD10
1.8VDD12
1.8VDD11
1.8VDD13
DVDD1
DVDD3
DVDD2
DVDD4
DVDD5
DVDD6
DVDD7
DVDD8
3VDD16
3VDD15
3VDD14
3VDD13
3VDD12
3VDD11
3VDD10
3VDD9
3VDD8
3VDD7
3VDD6
3VDD5
3VDD4
3VDD3
3VDD2
3VDD1
TVDD
RVDD2
RVDD1
VSS6
VSS4
VSS5
VSS1
VSS2
VSS3
TVSS3
TVSS2
TVSS1
RVSS5
RVSS4
RVSS3
RVSS1
RVSS2
DVSS1
DVSS2
DVSS3
DVSS4
TVSS4
1.8VDD4
1.8VDD2
1.8VDD1
2
1
CB103
2
1
CB123
2
1
CB66
2
1
CB108
2
1
CB96
2
1
CB111
2
1
CB112
CB68
CB85
CB129
CB99
CB130
2
1
CB120
2
1
CB109
2
1
CB117
2
1
CB97
2
1
CB82
2
1
CB121
2
1
CB88
2
1
CB92
2
1
CB83
2
1
CB70
2
1
CB80
2
1
CB49
2
1
CB69
2
1
CB101
2
1
CB113
2
1
C04
2
1
CB71
2
1
CB86
2
1
CB115
2
1
CB94
2
1
CB110
2
1
CB146
2
1
CB93
2
1
CB90
2
1
CB114
2
1
CB102
2
1
CB104
2
1
CB128
2
1
CB81
2
1
CB79
2
1
CB106
2
1
CB73
2
1
CB84
CB148
CB67
CB98
CB63
CB119
CB89
U8
P20
U7
U9
U6
U5
U4
U16
U15
U14
A15
U13
U12
D19
J19
W18
H20
U11
U10
D9
D8
D10
U18
V20
Y1
W8
Y7
U2
T3
R3
P1
U1
M2
L2
J1
K2
J2
K3
L1
T4
R4
P4
N4
D14
D13
D12
D11
D15
D17
D16
E17
L17
M17
T18
N17
P17
K17
R17
T17
F17
R18
G17
D20
G18
H17
J17
U17
Y13
P18
R20
P19
V9
J20
F3
B10
R19
J18
C12
Y9
B15
U09
1
2
CB45
2
1
CB36
2
1
CB42
2
1
CB43
54
8
7
3
2
6
1
U08
1
2
CB44
1
2
CB37
1
2
CB40
1
2
CB41
10UF
0.1UF
10UF
0.1UF
1UF
V1_8ZCHIP
V1_8ZCHIP
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
470UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
470UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
10UF
1UF
1UF
1UF
1UF
10UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
V1_8ZCHIP
0.1UF
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
POWER &GROUND
DS33R11_U1
1.8VDD1
1.8VDD2
1.8VDD4
TVSS4
DVSS4
DVSS3
DVSS2
DVSS1
RVSS2
RVSS1
RVSS3
RVSS4
RVSS5
TVSS1
TVSS2
TVSS3
VSS3
VSS2
VSS1
VSS5
VSS4
VSS6
RVDD1
RVDD2
TVDD
3VDD1
3VDD2
3VDD3
3VDD4
3VDD5
3VDD6
3VDD7
3VDD8
3VDD9
3VDD10
3VDD11
3VDD12
3VDD13
3VDD14
3VDD15
3VDD16
DVDD8
DVDD7
DVDD6
DVDD5
DVDD4
DVDD2
DVDD3
DVDD1
1.8VDD13
1.8VDD11
1.8VDD12
1.8VDD10
1.8VDD5
1.8VDD7
1.8VDD6
1.8VDD3
1.8VDD9
1.8VDD8
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS16
VSS17
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
V3_3
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
SERIAL SIGNALS WITH OFF PORT FLAGS GOTO THE 140 PIN WAN CONNECTORS
JUMPERS FOR ETHERNET RSER RCLK RDEN -VALID COMBINATIONS:
PLACE TESTPOINTS FOR ETHERNET DATAEN AND CLK NEAR CORRESPONDING 3PIN JUMPER
E_RDEN=VCC AND E_RCLKI=S_RCHCLK
E_RDEN=S_RCHBLK AND E_RCLKI=S_RCLK
01/05/2005
5/6(BLOCK)
10/27(TOTAL)
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
STEVE SCULLY
DS33ZH11-R11DK01A0
1
2
J11
1
2
J10
JP01
JP02
10
9
8
7
65
4
3
2
1
J18
10
9
8
7
65
4
3
2
1
J05
RB30
RB31
TP03
TP02
8
1
54
Y03
R14
2
1
RB44
2
1
RB19
2
1
RB50
2
1
RB49
2
1
RB47
2
1
RB51
2
1
RB54
2
1
RB14
2
1
RB46
2
1
RB45
Z_RDEN
Z_TSER
Z_RSER
Z_TDEN
FULLDS
MODEC1
DCEDTES
HWMODE
MODEC0
RMIIMIIS
AFCS
SCANMOD
SCANEN
2.0K
S_RCHCLK
S_RCLK
S_TCHCLK
S_TCLK
S_TCLKO
100.000MHZ_3.3V
10K
10K
Z_JTCLK
Z_JTMS
Z_JTDI
Z_JTDO
Z_JTRST
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
S_TCHBLK
MDC
MDIO
S_RCHBLK
S_TSER
SD_CLKI
30
S_RSER
Z_TCLKI
Z_RCLKI
2.0K
H10S
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
VCC
1
OSC
GND OUT
V3_3
V3_3
V3_3
SPARE INVERTERS
ALL UNMARKED BIAS RESISTORS ARE 10K
END OF DS33R11 HIERARCHY BLOCK
6/6(BLOCK)
STEVE SCULLY
DS33ZH11-R11DK01A0
11/27(TOTAL)
01/05/2005
BLOCK NAME: _z11andlan_dn. PARENT BLOCK: \_ds33r11dk_design\
A
D
G
B
C
F
H
E
RB53
RB69
RB58
RB73
RB52
RB83
R09
JP04
RB61
RB59
RB39
RB37
RB60
RB38
RB63
10
9
8
7
65
4
3
2
1
J06
RB34
RB36
8
1
54
Y01
10
9
8
7
65
4
3
2
1
J13
10
9
8
7
65
4
3
2
1
J12
1
2
CB105
RB35
2
1
RB91
R13
2
1
RB87
R10
R07
R12 C11
RB33
TPB03
RB32
TPB04
4
1
U07
12
1
10
3
11
2
TB01
94
7
6
85
TB01
8
7
6
5
4
3
2
1
J20
4
1
U06
TPB06
1
5
4
3
2
J19
TPB05
1
2
J17
1
5
4
3
2
J24
1
2
J25
S_LIUC
S_TSYNC
S_BPCLK
S_RDATA
S_8XCLK
S_RSYSCLK
S_TNEGI
S_TPOSI
30
30
S_TSER
S_RSYSCLK
S_TSYNC
S_LIUC
10K
S_RNEGI
S_RPOSO
S_TSYSCLK
S_JTMS
S_MCLK
RJ_PIN5
S_TCLK
S_RCLK
S_MCLK
S_TESO
S_TCLKO S_TDATA
S_TNEGO
S_TPOSO
S_RCLKI
S_RPOSI
30
30
30
30
10K
10K
10K
RRING
S_JTDO
S_JTDI
S_JTCLK
TRING
TTIP
RJ_PIN5
RJ_PIN2
RJ_PIN4
RJ_PIN1
RTIP
10K
0.1UF
30
0.0
60.4
0.0
0.0
0.0
10K
10K
S_JTRST
10K
S_TSSYNC
RJ_PIN1
60.4
S_TSIG
INVERTER
INVERTER
10K
10K
S_TCLKI
30
S_RNEGO
S_RCLKO
10K
1UF
2.048MHZ_3.3V
RJ_PIN4
RJ_PIN2
S_RFSYNC
S_TSYSCLK
S_TSSYNC
S_TSIG
S_RSYNC
S_RMSYNC
S_RSIGF
S_RSIG
S_RLOS
S_RCL
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
NC7SZ86_U
CONN_BNC_5P
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
VCC
1
OSC
GND OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
6
10
8
4
1
2
3
5
7
9
CONN_10P
CONN_BNC_5P
NC7SZ86_U
1:1
1:2
CONN_RJ48
E
H
F
C
B
G
D
A
V3_3
BEGINNING OF PROCESSOR HIERARCHY BLOCK
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
PRINTED Fri Sep 23 11:01:52 2005
12/27(TOTAL)
STEVE SCULLY
01/05/2005
1/6(BLOCK)
DS33ZH11-R11DK01A0
MR*
GND
VCC
RESET*
VDD4
VDD1
VDD2
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSSA
VSSF
VSSSYN
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
A0
A1
A2
A3
A4
A5
A6
A7
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D31
A8
VRL
RW
VDD5
VDD3
VDDSYN
VDD8
VDD7
VDD6
VPP
VDDA
VDDF
VDDH
TEA*
VSTBY
VRH
OE*
SHS*
TA*
TXD1
RXD2
INT4
INT5*
INT2*
INT3*
XTAL
MISO
MOSI
YC0
INT0*
TMS
CS0*
RESET*
CLKOUT
RSTOUT*
SCK
DE*
CS2*
CS1*
CSE0
TC2
EB2*
EB1*
EB0*
PQB3
PQB2
PQB1
INT6*
EB3*
CSE1
TDO
TDI
TC1
CS3*
PQA1
PQA0
PQA3
PQA4
PQB0
SS*
TRST*
TCLK
EXTAL
ICOC22
ICOC23
ICOC20
ICOC21
ICOC11
ICOC12
ICOC13
INT1*
TEST
ICOC10
TXD2
INT7*
RXD1
RB26
C02
80
124
66
69
142
138
63
135
133
130
67
78
94
93
68
70
120
118
104
105
106
107
108
109
110
111
90
91
89 88
84
82
79
75
72
71
52
53
54
55
56
57
58
61
125
96
98
100
101
143
60
62
81
83
85
86
128
U03
92
126
73
114
140
127
76
64
44
32
18
8
112
113
87
123
103
74
115
141
129
77
65
45
33
19
9
102
99
97
59
95
37
38
39
40
41
42
144
1
43
2
3
4
5
7
10
12
15
16
17
46
20
21
22
25
27
30
31
34
35
36
48
51
13
14
23
24
26
28
29
116
117
119
47
121
122
131
132
134
136
137
139
6
11
49
50
U03
4
2
3
1
U01
4
3
2
1
SW01
RB29
CB33
PQB0
PQB2
PQB3
KIT_STATUS
INT2
OSC_MCU
ONCE_TCLK
ONCE_TRST_B
1UF
17
TC2
SS
TA
RCON
OE
VRH
TEA
RW
SCI1_IN
USER_LED1
SCI2_OUT
ICOC10
TEST
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
PQA4
PQA3
PQA0
PQA1
CS3
TC1
ONCE_TDI
2107_TDO
CSE1
EB3
TIM_16H_8L
PQB1
EB0
EB1
EB2
CSE0
CS1
CS2
CPUCLK_OUT
CS0
ONCE_TMS
YCO
MOSI
MISO
XTAL
INT4
RUN_KIT_USR
USER_LED2
INT3
SCI2_IN
SCI1_OUT
25
20
2.93V
22
13
12
11
10
8
9
7
6
5
3
21
4
1
0
.1UF
0.0
20
0
2
3
4
5
31
30
29
27
19
28
26
24
23
6
7
8
9
10
21
18
19
17
18
16
13
12
11
16
15
14
GND
PA<22..0>
2
PD<31..0>
1
22
15
14
VDDSYN
FLASH_VPP
ONCE_DE_B
SCK
PROC_RESET_OUT
PROC_RESET
PROC_RESET
1.0K
RESET
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
MMC2107
CONTROL
RXD1
INT7*
TXD2
ICOC10
TEST
INT1*
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
EXTAL
TCLK
TRST*
SS*
PQB0
PQA4
PQA3
PQA0
PQA1
CS3*
TC1
TDI
TDO
CSE1
EB3*
INT6*
PQB1
PQB2
PQB3
EB0*
EB1*
EB2*
TC2
CSE0
CS1*
CS2*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
TMS
INT0*
YC0
MOSI
MISO
XTAL
INT3*
INT2*
INT5*
INT4
RXD2
TXD1
MMC2107
PORT
TA*
SHS*
OE*
VRH
VSTBY
TEA*
VDDH
VDDF
VDDA
VPP
VDD6
VDD7
VDD8
VDDSYN
VDD3
VDD5
RW
VRL
A8
D31
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
A0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSSSYN
VSSF
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
VDD2
VDD1
VDD4
V3_3
MAX811_U
RESET*
VCC
GND
MR*
V3_3
RESET AND CHIP CONFIGURATION
XTAL W/ PLL
BOOT INTERNAL
D18 HAS A10K LOAD TO GND
D18 HAS A10.5K LOAD TO V3V
BOOT EXT
WHEN SET FOR
INTERN/EXTERN
BOOT
RESET CONFIGURATION
FULL DRIVE
MASTER MODE
INTERNAL
FLASH ENABLE
DS33ZH11-R11DK01A0
STEVE SCULLY
01/05/2005
2/6(BLOCK)
13/27(TOTAL)
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
A8
A9
A10
A11
A12
A13
A14
A15
A16
VCC
GND
OE*
WE*
N_C
A0
A1
A2
A3
A4
A5
A6
A7
CE2
CE1*
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
A8
A9
A10
A11
A12
A13
A14
A15
A16
VCC
GND
OE*
WE*
N_C
A0
A1
A2
A3
A4
A5
A6
A7
CE2
CE1*
2
1
RB12
2
1
1
RB22
2
1
RB10
2
1
1
RB18
2
1
1
RB17
2
1
RB11
1
2
1
RB09
1
2
1
RB13
2
1
1
RB08
29
32
24
1
21
20
19
18
17
15
14
13
16
30
22
26
27
5
6
7
8
9
10
2
31
3
28
4
25
23
11
12
U05
2
1
1
RB07
29
32
24
1
21
20
19
18
17
15
14
13
16
30
22
26
27
5
6
7
8
9
10
2
31
3
28
4
25
23
11
12
UB03
PA<17..1>
PD<23..16>
PD<31..24>
PD<18>
PD<19>
PD<28>
PD<22>
PD<23>
PD<21>
PD<16>
PD<17>
PD<26>
16
10K
10K
10K
10K
10K
10K
10K
17
10K
10K
18
20
9
10
11
12
8
7
6
5
19
13
14
16
15
17
4
3
2
1
24
21
25
26
27
28
29
30
31
10K
22
9
10
11
12
13
14
16
8
7
6
5
4
3
2
1
15
17
OE
EB0
CS0
CY62128V
PA<17..1>
CY62128V
OE
EB1
CS0
RCON
23
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
BUT DO NOT POPULATE
JTAG CONFIGURATION
ALIGN KEY
PIN
ONCETDI
MMC2107
ONCETDO
PIN
TDI
...FPGA+FLASH...
PLACE PADS FOR CAP
3/6(BLOCK)
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
14/27(TOTAL)
R2IN
R2OUT
R1IN
T1IN
FORCEON
R1OUT
T1OUT
VCC
FORCEOFF*
V+1
V+2
C1+
C1-
C2+
C2-
V-
GND
T2OUT
T2IN
INVALID*
J
E
D
B
A
C
F
G
H
1
2
1
RB23
2
1
DS04
2
1
RB21
2
1
DS03
1
2
J03
2
1
1
RB24
1
2
XB01
1
2
1
R01
2
1
RB27
1
2
1
RB28
9
8
7
6
5
4
3
2
1
J02
1
2
1
RB03
1
2
1
RB06
9
17
12
11
19
3
7
4
1
20
6
8
2
18
5
10
16
15
14
13
UB01
2
1
RB01
2
1
1
RB25
1413
12
11
10
9
8
7
65
4
3
2
1
J04
KIT_STATUS
PRT1_OUT
SCI1_IN
SCI1_OUT
PRT1_IN
ONCE_TRST_B
ONCE_DE_B
ONCE_TMS
CON14P
10K
OSC_MCU
PRT1_IN
PRT1_OUT
XTAL
10K
10K
10K
10K
10K
1.0M
8.0MHZ
PROC_RESET
ONCE_TCLK
2107_TDO
ONCE_TDI
1.0K
FLASH_VPP
RED
330
330
GREEN
USER_LED1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
V3_3
CONN_DB9P
H
G
F
C
A
B
D
EJ
V3_3
MAX3233E
INVALID*
T2IN
T2OUT
GND
V-
C2-
C2+
C1-
C1+
V+2
V+1
FORCEOFF*
VCC
T1OUT
R1OUT
FORCEON
T1IN
R1IN
R2OUT R2IN
V3_3
CON14P
MEM_SO /RUN_DRV INSTALL JUMPER TO RUN DEVICE DRIVER
MEM_SI /TCLKEQRCLK INSTALL JUMPER TO SET TCLK=RCLK
MEM_CS /EN_INTS INSTALL JUMPER TO ENABLE INTERRUPT SERVICE
MEM_SCK MUST BE AT PIN77 FOR TQFP144
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
4/6(BLOCK)
15/27(TOTAL)
PR12B/DI/CSSPI*
PR11B/BUSY/SISPI
PR11A/D7/SPID0
PT17B/PCLKC0_0
PR15B
PL9A/PCLKT7_0
PR16B
PR18A/VREF1_3
PR16A
PR15A/RDQS15
PR14B/RLM0_PLLC_FB_A
PR13B/RLM0_PLLC_IN_A
PR13A/RLM0_PLLT_IN_A
PR9B/PCLKC2_0
PR9A/PCLKT2_0
PR8B
PR8A
PR7A
PR7B
PR2A/VREF2_2
PR2B/VREF1_2
PT18A
PT18B
PT19A/VREF1_1
PT13A
PT13B
PT19B/VREF2_1
PT20B
PT21A
PT20A
PT21B
PT22A/TDQS22
PT22B
PT23A
PT25A
PT25B
PL8A
PL8B
PL7B
PL7A
PL2B/VREF1_7
PL2A/VREF2_7
PB24B/D5/SPID2
PB25B/D6/SPID1
PB23B/D4/SPID3
PB22B/D3/SPID4
PB21B/D1/SPID6
PB20B/D0/SPID7
PL16A
PB10A
PB11A
PB11B
PB13B
PB14A/BDQS14
PB14B
PB15A
PB15B
PB16B/VREF1_5
PB16A/VREF2_5
PB17B/PCLKC5_0
PB18A/WRITE*
PL18A/VREF1_6
PL18B/VREF2_6
PL16B
PL15A/LDQS15
PL15B
PL14B
PL12B/LLM0_PLLC_FB_A
PL12A/LLM0_PLLT_FB_A
PL11B/LLM0_PLLC_IN_A
PL11A/LLM0_PLLT_IN_A
PB18B/CS1*
PB21A/D2/SPID5
PB22A/BDQS22
PB23A
PB10B PT10B
PT10A
PT14A/TDQS14
PB20A/VREF2_4
PB19B/CS*
PB19A/VREF1_4
PB17A/PCLKT5_0
PT12A
PT12B
PL13A
PL13B
PL14A
PT14B
PR12A/DOUT/CSO*
PR14A/RLM0_PLLT_FB_A
PT16A/VREF2_0
PT15B
PT15A
PT17A/PCLKT0_0
PT16B/VREF1_0
PL9B/PCLKC7_0
RB15
DS01
RB16
111
112
113
114
115
116
118
119
120
121
122
123
124
127
129
130
131
132
133
134
135
137
138
139
140
141
142
100
101
102
103
104
105
106
107
74
75
76
77
78
79
81
82
83
85
86
87
88
9
8
7
6
5
4
3
2
35
34
33
32
31
30
29
27
26
25
23
22
21
20
70
69
68
67
66
65
64
62
61
60
59
58
57
56
53
51
50
49
48
47
46
45
43
42
41
40
39
U04
FPGA_ZHSPICS
WR_DUT
PD<31..16>
23
RESET_AH
CS_X1
CS_X6
CS_X2
CS_X5
CS_X3
CS_X4
RESET
CS2
CS1
CS0
RW
OE
INT2
INT_LED
RD_DUT
330
0
1
2
3
4
5
6
7
D_DUT<7..0>
0.0
PA<16..0>
16
17
18
19
20
21
22
24
25
26
28
30
31
29
27
CPUCLK_OUT
A_DUT_<9..0>
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
INT5
USERFPGA2
MEM_SCK
ALE_DUT
97_IO
FPGA_ZHMOSI
FPGA_ZHSPISCK
FPGA_ZHMISO
EB0
EB1
MEM_SO RUN_DRV
TCLKEQRCLK
EN_INTSMEM_CS
MEM_SI
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
BANK 3
LFEC_T144_U
BANK 0
I/O PORT
BANK 6
BANK 4BANK 5
BANK 1
BANK 2
INPUT
PLL
PLL
INPUT
PLL
INPUT
BANK 7
INPUT
PLL
INPUT
PLL
PLL
INPUT
PL9B/PCLKC7_0
PT16B/VREF1_0
PT17A/PCLKT0_0
PT15A
PT15B
PT16A/VREF2_0
PR14A/RLM0_PLLT_FB_A
PR12A/DOUT/CSO*
PT14B
PL14A
PL13B
PL13A
PT12B
PT12A
PB17A/PCLKT5_0
PB19A/VREF1_4
PB19B/CS*
PB20A/VREF2_4
PT14A/TDQS14
PT10A
PT10BPB10B
PB23A
PB22A/BDQS22
PB21A/D2/SPID5
PB18B/CS1*
PL11A/LLM0_PLLT_IN_A
PL11B/LLM0_PLLC_IN_A
PL12A/LLM0_PLLT_FB_A
PL12B/LLM0_PLLC_FB_A
PL14B
PL15B
PL15A/LDQS15
PL16B
PL18B/VREF2_6
PL18A/VREF1_6
PB18A/WRITE*
PB17B/PCLKC5_0
PB16A/VREF2_5
PB16B/VREF1_5
PB15B
PB15A
PB14B
PB14A/BDQS14
PB13B
PB11B
PB11A
PB10A
PL16A
PB20B/D0/SPID7
PB21B/D1/SPID6
PB22B/D3/SPID4
PB23B/D4/SPID3
PB25B/D6/SPID1
PB24B/D5/SPID2
PL2A/VREF2_7
PL2B/VREF1_7
PL7A
PL7B
PL8B
PL8A
PT25B
PT25A
PT23A
PT22B
PT22A/TDQS22
PT21B
PT20A
PT21A
PT20B
PT19B/VREF2_1
PT13B
PT13A
PT19A/VREF1_1
PT18B
PT18A
PR2B/VREF1_2
PR2A/VREF2_2
PR7B
PR7A
PR8A
PR8B
PR9A/PCLKT2_0
PR9B/PCLKC2_0
PR13A/RLM0_PLLT_IN_A
PR13B/RLM0_PLLC_IN_A
PR14B/RLM0_PLLC_FB_A
PR15A/RDQS15
PR16A
PR18A/VREF1_3
PR16B
PL9A/PCLKT7_0
PR15B
PT17B/PCLKC0_0
PR11A/D7/SPID0
PR11B/BUSY/SISPI
PR12B/DI/CSSPI*
OUT
IN
OUT
OUT
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
5/6(BLOCK)
DS33ZH11-R11DK01A0
STEVE SCULLY
01/05/2005
16/27(TOTAL)
2
1
R2
2
1
R1
1413
12
11
10
9
8
7
65
4
3
2
1
J07
1413
12
11
10
9
8
7
65
4
3
2
1
J08
1413
12
11
10
9
8
7
65
4
3
2
1
J09
2
1
RB40
2
1
RB41
2
1
RB42
2
1
RB43
TCLKEQRCLK
EN_INTS
RUN_DRV
10K
10K
10K
INT3
NOPOP
INT2
A_DUT_<9..0>
10K
WR_DUT
RESET
CS_X2
CS_X4
CS_X3
RD_DUT
CS_X1 INT3
INT2
NOPOP
7
6
5
4
3
2
1
A_DUT_<9..0>
D_DUT<7..0>
INT4
10K
10K
RESET_AH
RESET
CS_X4
INT4
INT5
CS_X2
CS_X5
CS_X1
RD_DUT
WR_DUT
CS_X3
INT2
INT3
0
NOPOP
INT5
0
1
2
D_DUT<7..0>
3
4
5
6
7
8
9
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
OUT
OUT
OUT
V3_3
OUT
V3_3
OUT
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
2
3
7
13
8
5
9
11
6
4
10
12
14
1
CONN_14P
OUT
OUT
OUT
IN
IN
IN
IN
IO
OUT
OUT
V3_3
END OF PROCESSOR HIERARCHY BLOCK
17/27(TOTAL)
6/6(BLOCK)
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
BLOCK NAME: _motprocrescard_dn. PARENT BLOCK: \_ds33r11dk_design\
VCCIO6B
VCCIO7
GND5
GND6A
GND4
NC2
NC1
GND0
GND1
GND2/GND1
GND3A/GND4
GND3B
GND6B/GND5
GND7/GND0
GND8
GND9
GND10
DONE
TCK
VCCIO6A
VCCIO5B
VCC1
VCC2
TMS
CFG0
CFG2
CFG1
CCLK
VCCIO0A
PROGRAM*
INIT*
VCCIO0B
VCCIO1A
VCCIO1B
VCCIO2
VCCIO5A
VCCIO4B
VCCIO3A
TDO
TDI
VCC3
VCCJ
VCCAUX1
VCCAUX2
XRES
VCCIO3B
VCCIO4A
CS*
SCK
SO
VCC
HOLD*
WP*
GND
SI
IN
IC
OUT
RST*GND
SHDN*
3
4
6
1
5
2
UB02
3
8
2
5
6
7
4
1
U02
10
9
8
7
65
4
3
2
1
J01
CB24
CB23
CB26
CB12
CB25
CB29
RB05
RB04
10
19
1
36
24
44
38
71
55
84
73
108
125
110
143
136
126
54
99
92
13
17
18
16
14
93
12
11
95
96
15
144
37
28
52
63
80
72
109
98
117
128
97
89
90
91
94
U04
RB02
1
TPB01
1
TPB02
R02
I28
I26
I24
I10
I6
I5
MEM_SI
MEM_SO
MEM_SCK
MEM_CS
L_TDO
L_TDI
L_TDI
L_TDO
RESET
MEM_SCK
L_TMS
L_TCK
V1_2
L_TCK
L_TMS
V1_2
2.7V
.1UF
.1UF
.1UF
10UF
10UF
10UF
10K
10K
97_IO
10K
10K
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1963
SHDN*
GND RST*
OUT
IC
IN
V3_3
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
CONN_10P
7
1
5
GND
3
TCK
TMS
TDI
VCC
TDO
V3_3
V3_3
CONTROL
LFEC_T144_U
ALL LOW FOR
SPI3 MODE
NEEDS 10K,1% RESISTOR
PLACE CLOSE TO PIN
VCCIO4A
VCCIO3B
XRES
VCCAUX2
VCCAUX1
VCCJ
VCC3
TDI
TDO
VCCIO3A
VCCIO4B
VCCIO5A
VCCIO2
VCCIO1B
VCCIO1A
VCCIO0B
INIT*
PROGRAM*
VCCIO0A
CCLK
CFG1
CFG2
CFG0
TMS
VCC2
VCC1
VCCIO5B
VCCIO6A
TCK
DONE
GND10
GND9
GND8
GND7/GND0
GND6B/GND5
GND3B
GND3A/GND4
GND2/GND1
GND1
GND0
NC1
NC2
GND4
GND6A
GND5
VCCIO7
VCCIO6B
V3_3
PAGE NUMBERS (BOTTOM RIGHT) ARE LISTED BY BOTH THE PAGE NUMBER IN THE BLOCK, AND BY THE PAGE NUMBER WITHIN THE ENTIRE DESIGN
CROSS REFERENCE INDICATORS ARE REFERENCEING AGIVEN NET TO OTHER PAGES IN THE DESIGN (PAGE NUMBER GIVEN IS ACCORDING TO ENTIRE DESIGN, NOT THE CURRENT BLOCK)
DS33ZH11 DESIGN KIT
MII ETHERNET HIERARCHY BLOCK
T1E1 LIU HIERARCHY BLOCK
DS33ZH11 HIERARCHY BLOCK
T3E3 LIU HIERARCHY BLOCK
BUFFER FOR DELAY
NOTES: ALL HIERARCHY BLOCK NAMES END IN _DN. PINS ON HIERARCHY BLOCKS DO NOT HAVE PIN NUMBERS (BUT PINS ON SYMBOLS DO).
SIGNALS INSIDE AHIERARCHY BLOCK ARE LOCAL TO THAT BLOCK -THE SIGNAL TEMP IN BLOCK_A_DN IS DIFFERENT THAN TEMP IN BLOCK_B_DN.
PAGES 20-22 PAGES 26-27
PAGES 24-25
PAGE 23
PRINTED Fri Sep 23 11:01:54 2005
1/2(BLOCK)
18/27(TOTAL)
DS33ZH11-R11DK01A0 01/05/2005
STEVE SCULLY
BLOCK NAME: _ds33zh11dk_design. PARENT BLOCK: \_ztopdn_\
ZMISO
RXD2
RXDV
TX_EN
TXD3
TXD2
TXD1
TXD0
RX_ERR
RX_CRS
RX_CLK
RXD3
RXD1
RXD0
TX_CLK
FPGA_SPICS
ZSPISCK
ZMOSI
REF_CLKO
RST_ZCHIP
TSER
TCLKI
RSER
RCLKI
RCLK
RPOS
TPOS
TCLK
RST
TPOS
TCLKI
RPOS
RCLK
TXD0
MII_CLK
MDC
MDIO
TXD1
TXD2
TXD3
TX_CLK
RXDV
COL_DET
RX_CRS
RX_ERR
RX_CLK
LED_DPLX_ADD0
LED_COL_ADD1
LED_GDLINK_ADD2
LED_RX_ADD4
LED_TX_ADD3
RXD0
RXD3
RXD2
RXD1
TX_EN
RESET
R21
RB101
RB129
RB138
RB132
4
1
UB06
2
3
1
JP06
2
3
1
JP07
2
3
1
JP08
2
3
1
JP05
2
3
1
JP11
8
1
5 4
YB04
TE3_RPOS
TE1_TPOS
TE1_RCLK
ZH_RXD1
ZH_RXD2
ZH_RXD3
ZH_RX_CRS
ZH_RXDV
ZH_RCLKI
ZH_RSER
ZH_TCLKI
RST_ZCHIP
REF_CLKO
ZMOSI
ZSPISCK
FPGA_SPICS
ZH_TX_CLK
ZH_RXD0
ZH_RX_CLK
ZH_RX_ERR
ZH_TXD0
ZH_TXD1
ZH_TXD2
ZH_TXD3
ZH_TX_EN
ZMISO
ZH_TSER
PHY_CLK
REF_CLKO
JMP_3
TE3_TPOS
TE3_RCLK
TE3_TCLK
30
V3_3
GND
TE1_TCLK
LED_DPLX_A0
LED_COL_A1
LED_GDLINK_A2
LED_RX_A4
LED_TX_A3
25.000MHZ_3.3V
RST_PRF
TE1_RPOS
RST_PRF
BUFFER
30
30
30
30
1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
VCC
1
OSC
GNDOUT
OUT
IN
IN
NC7SZ86_U
V3_3
_mii_wan_dn
RESET
TX_EN
RXD1
RXD2
RXD3
RXD0
LED_TX_ADD3
LED_RX_ADD4
LED_GDLINK_ADD2
LED_COL_ADD1
LED_DPLX_ADD0
RX_CLK
RX_ERR
RX_CRS
COL_DET
RXDV
TX_CLK
TXD3
TXD2
TXD1
MDIO
MDC
MII_CLK
TXD0
_TE1LIU_WAN_DN
RCLK
RPOS
TCLKI
TPOS
RST
_te3liu_wan_dn
TCLK
TPOS
RPOS
RCLK
V3_3
_zh11_dn
RCLKI
RSER
TCLKI
TSER
RST_ZCHIP
REF_CLKO
ZMOSI
ZSPISCK
FPGA_SPICS
TX_CLK
RXD0
RXD1
RXD3
RX_CLK
RX_CRS
RX_ERR
TXD0
TXD1
TXD2
TXD3
TX_EN
RXDV
RXD2
ZMISO
DS33ZH11 MII CLK IS GATED BY RESET
160 US BEFORE RESET DEACTIVATES
MII PHY REQUIRES MII CLK TO BE STABLE FOR
PRINTED Fri Sep 23 11:01:54 2005
2/2(BLOCK)
19/27(TOTAL)
BLOCK NAME: _ds33zh11dk_design. PARENT BLOCK: \_ztopdn_\
DS33ZH11-R11DK01A0 01/05/2005
STEVE SCULLY
MR*
GND
VCC
RESET*
CB158
CB156
CB182
C25
2
1
CB192
2
1
C34
2
1
CB196
2
1
CB191
2
1
CB152
2
1
CB176
2
1
CB186
C27
CB166
CB173
CB174
CB183
C35
CB172
C33
CB164
CB167
CB165
4
SW02
4
2
3
1
U15
RB178
CB194
2
1
DS19
RB168
2
1
DS20
RB169
RB174
2
1
DS21
RB173
RB176
RB175
2
1
DS18
RB165
RB164
2
1
DS16
RB157
RB158
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
1
470UF
1
0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
4.7UF
1
10UF
1
10UF
1
10UF
10UF
1
10UF
1
10UF
1
I35
I34
I20
I18
I15
I11
I8
RST_ZCHIP RST_PRF
LED_TX_A3
LED_RX_A4
LED_GDLINK_A2
LED_COL_A1
LED_DPLX_A0
MAX811SEUS-T
2.93V
SOT143
2.0K
0.1UF
1
RED
5.1K
1
1
AMBER
330
1
1
330
1
GREEN
5.1K
1
1
330
5.1K
1
AMBER
1
330
1
5.1K
1
1
AMBER
1
330
5.1K
1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX811_U
RESET*
VCC
GND
MR*
V3_3
V3_3
SERIES TERMINATION
MII TX PINS USUALY HAVE
ZH11 PACKAGE ALLOWS FOR
CLOSE PLACEMENT, RESISTORS OMITTED
THIS PAGE ARE 30 OHM
UNMARKED RESISTORS ON
BEGINING OF DS33ZH11 HIERARCHY BLOCK
01/05/2005
1/3(BLOCK)
20/27(TOTAL)
STEVE SCULLY
DS33ZH11-R11DK01A0
BLOCK NAME: _zh11_dn. PARENT BLOCK: \_ds33zh11dk_design\
SDA<0>
6VDD3.3
2VDD3.3
1VDD3.3
0VDD3.3
TSER
SDA<1>
REF_CLKO
RX_CRS/CRS_DV
RX_ERR
RX_CLK
RX_DV
RXD<3>
TX_CLK
TX_EN
D<1>/MISO
D<0>/MOSI
D<2>/SPICK
SPI_CS*
HWMODE
SDATA<27>
SDATA<25>
SDATA<24>
SDATA<23>
SDATA<18>
SDATA<19>
SDATA<26>
SDATA<22>
SDATA<21>
SDATA<20>
SDATA<17>
SDATA<16>
SDATA<14>
SDATA<15>
SDATA<6>
SDATA<5>
SDATA<7>
SDATA<8>
SDATA<9>
SDATA<10>
SDATA<12>
SDATA<11>
SDATA<13>
SDATA<2>
SDATA<3>
SDATA<4>
SDATA<1>
SDATA<0>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
2VDD1.8
0VDD1.8
1VDD1.8
(FUTURE A1) 5VDD3.3
3VDD3.3
TCLKI
RCLKI
RXD<2>
RXD<1>
RXD<0>
4VDD1.8
3VDD1.8
RSER
SDA<3>
SDA<4>
SDA<6>
SDA<5>
SDA<7>
SDA<8>
SDA<9>
SDA<10>
SDA<11>
SDMASK<0>
SDMASK<1>
SDMASK<2>
SDCS*
SDMASK<3>
SDCLKO
SYSCLKI
SRAS*
SCAS*
SWE*
SBA<1>
SDA<2>
MODEC<1>
SDATA<28>
SDATA<29>
SDATA<30>
SDATA<31>
VSS5
VSS4
VSS3
VSS2
VSS1 (FUTURE A2)
VSS0 (FUTURE A0)
RST*
4VDD3.3
SBA<0>
RB133
E7
E6
E5
E4
B4
A5
A9
B8
B7
A8
B6
A6
A2
B1
K10
G3
K3
B5
C5
J6
E3
F3
H3
J3
C6
G6
G8
G9
C7
H9
H8
J9
K9
H7
J8
K7
K8
J7
G7
K6
E1
D2
D1
G1
F1
C2
E2
D3
C3
J2
K2
K1
G2
J1
F2
H1
K4
H5
F5
F8
G4
G5
H4
C4
F9
H6
K5
J5
F4
J4
F7
C10
C9
D10
D9
B9
A10
C8
B10
C1
B3
G10
B2
A4
A3
E10
E9
E8
H10
D8
D7
A1
D6
J10
D5
H2
D4
F10
A7
F6
U11
TSER
SD_BA0
RST_ZCHIP
FUT_A0
FUT_A2
MODEC1
SD_BA1
SD_WE
SD_CAS
SD_RAS
SD_CLKI
SD_CLKO
SD_DQM3
SD_CS
SD_DQM2
SD_DQM1
SD_DQM0
RSER
RXD0
RXD1
RXD2
RCLKI
TCLKI
FUT_A1
TXD0
TXD1
TXD2
TXD3
HWMODE
ZSPICS
ZSPISCK
ZMOSI
ZMISO
TX_EN
TX_CLK
RXD3
RXDV
RX_CLK
RX_ERR
RX_CRS
REF_CLKO
SD_DQ<31..0>
26
V1_8LVREG
9
SD_DQ<31..0>
21
20
19
18
11
8
7
5
6
4
3
0
25
24
23
22
17
16
15
14
12
11
9
10
8
7
6
4
0
31
30
29
28
27
JMP_3
10
5
3
1
2
1
2
SD_A<11..0>
13
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
V3_3
IN
IN
IN
OUT
DS33ZH11_U1
SBA<0>
4VDD3.3
RST*
VSS0 (FUTURE A0)
VSS1 (FUTURE A2)
VSS2
VSS3
VSS4
VSS5
SDATA<31>
SDATA<30>
SDATA<29>
SDATA<28>
MODEC<1>
SDA<2>
SBA<1>
SWE*
SCAS*
SRAS*
SYSCLKI
SDCLKO
SDMASK<3>
SDCS*
SDMASK<2>
SDMASK<1>
SDMASK<0>
SDA<11>
SDA<10>
SDA<9>
SDA<8>
SDA<7>
SDA<5>
SDA<6>
SDA<4>
SDA<3>
RSER
3VDD1.8
4VDD1.8
RXD<0>
RXD<1>
RXD<2>
RCLKI
TCLKI
3VDD3.3
(FUTURE A1) 5VDD3.3
1VDD1.8
0VDD1.8
2VDD1.8
TXD<0>
TXD<1>
TXD<2>
TXD<3>
SDATA<0>
SDATA<1>
SDATA<4>
SDATA<3>
SDATA<2>
SDATA<13>
SDATA<11>
SDATA<12>
SDATA<10>
SDATA<9>
SDATA<8>
SDATA<7>
SDATA<5>
SDATA<6>
SDATA<15>
SDATA<14>
SDATA<16>
SDATA<17>
SDATA<20>
SDATA<21>
SDATA<22>
SDATA<26>
SDATA<19>
SDATA<18>
SDATA<23>
SDATA<24>
SDATA<25>
SDATA<27>
HWMODE
SPI_CS*
D<2>/SPICK
D<0>/MOSI
D<1>/MISO
TX_EN
TX_CLK
RXD<3>
RX_DV
RX_CLK
RX_ERR
RX_CRS/CRS_DV
REF_CLKO
SDA<1>
TSER
0VDD3.3
1VDD3.3
2VDD3.3
6VDD3.3
SDA<0>
CONFIG SWITCHES FOR Z11
LOW
LOW
DS33ZH11-R11DK01A0
21/27(TOTAL)
STEVE SCULLY
01/05/2005
2/3(BLOCK)
BLOCK NAME: _zh11_dn. PARENT BLOCK: \_ds33zh11dk_design\
CS*
SCK
SO
VCC
HOLD*
WP*
GND
SI
RST
SHDN
IN
OUT
GND
SET
OUT
IN
RB102
8
1
54
YB03
RB104
RB116
1
2
J27
RB98
1
2
J26
RB97
R15
2
3
1
JPB01
CB161
CB157
CB193
CB155
CB159
CB160
CB154
1
2
CB153
2
1
CB197
2
1
CB195
2
1
C30
54
8
7
3
2
6
1
UB07
3
8
2
5
6
7
4
1
Y04
RB100
RB99
FUT_A1
JMP_3
ZSPICS
FPGA_SPICS
MODEC1
JMP_2
.1UF
4.7UF
V1_8LVREG
4.7UF
4.7UF
2.7V
10UF
10UF
1
1
1
1UF
1
1UF
1
1UF
2
1UF
10K
4.7UF
ZMISO
10K
1
30
2.0K
JMP_2
2.0K
2.0K
2.0K
100.000MHZ_3.3V
2.0K
SD_CLKI
HWMODE
FUT_A0
FUT_A2
ZSPISCK
ZMOSI
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
1
OSC
GND OUT
V3_3
V3_3
V3_3
OUT
IN
IN
IN
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
V3_3
BE NON- SWAPABLE
ADDRESS PINS APPEAR THAT THEY SHOULD
FROM Z11 SYSCLKO
MT48LC4M32B2 -1MEG X32 X4BANKS
SYNCHRONOUS DRAM
BLOCK NAME: _zh11_dn. PARENT BLOCK: \_ds33zh11dk_design\
DS33ZH11-R11DK01A0
STEVE SCULLY
3/3(BLOCK)
01/05/2005
22/27(TOTAL)
VDD4
VDD3
VDDQ6
VDDQ1
CLK
CS*
CKE
CAS*
WE*
DQM<0>
RAS*
DQM<1>
DQM<2>
DQM<3>
BA<0>
BA<1>
A<0>
A<1>
A<3>
A<2>
A<4>
A<6>
A<5>
A<8>
A<7>
A<9>
A<10>
A<11>
DQ<5>
DQ<6>
DQ<7>
DQ<8>
DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<14>
DQ<13>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<20>
DQ<19>
DQ<21>
DQ<23>
DQ<22>
DQ<25>
DQ<24>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
VDDQ5
VDDQ4
DQ<4>
VDD2
VDD1
DQ<2>
DQ<3>
DQ<1>
DQ<0>
DQ<30>
DQ<31>
VSSQ8
VSSQ6
VSSQ7
VSSQ5
VSSQ3
VSSQ4
VSSQ1
VSSQ2
VSS3
VSS4
VSS1
VSS2
VDDQ7
VDDQ8
VDDQ3
VDDQ2
17
84
78
52
46
38
32
12
6
86
72
58
44
81
75
55
49
41
35
9
3
43
29
15
1
19
59
28
71
16
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
20
68
67
18
23
22
21
24
66
65
64
63
62
61
60
27
26
25
UB05
SD_BA1
SD_BA0
SD_CS
SD_WE
SD_CAS
SD_RAS
SD_DQM0
SD_DQM1
SD_DQM2
SD_CLKO
SD_DQM3
SD_DQ<31..0>
SD_A<11..0>
8
7
6
5
4
29
28
27
26
25
24
23
22
3
21
20
19
18
17
16
15
14
13
2
12
11
10
9
8
6
7
5
4
3
1
2
30
31
1
0
11
10
9
0
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MT48LC4M32B2_TSOP_U
VDDQ2
VDDQ3
VDDQ8
VDDQ7
VSS2
VSS1
VSS4
VSS3
VSSQ2
VSSQ1
VSSQ4
VSSQ3
VSSQ5
VSSQ7
VSSQ6
VSSQ8
DQ<31>
DQ<30>
DQ<0>
DQ<1>
DQ<3>
DQ<2>
VDD1
VDD2
DQ<4>
VDDQ4
VDDQ5
DQ<29>
DQ<28>
DQ<27>
DQ<26>
DQ<24>
DQ<25>
DQ<22>
DQ<23>
DQ<21>
DQ<19>
DQ<20>
DQ<18>
DQ<17>
DQ<16>
DQ<15>
DQ<13>
DQ<14>
DQ<12>
DQ<11>
DQ<10>
DQ<9>
DQ<8>
DQ<7>
DQ<6>
DQ<5>
A<11>
A<10>
A<9>
A<7>
A<8>
A<5>
A<6>
A<4>
A<2>
A<3>
A<1>
A<0>
BA<1>
BA<0>
DQM<3>
DQM<2>
DQM<1>
RAS*
DQM<0>
WE*
CAS*
CKE
CS*
CLK
VDDQ1
VDDQ6
VDD3
VDD4
V3_3
SPARE (SOCKETED) OSCILLATOR
USE 34.368 MHZ FOR E3
USE 44.736 MHZ FOR T3
BEGINING AND END OF T3E3 LIU HIERARCHY BLOCK
NETWORK INTERFACE
TXTIP
RXTIP
RXRING
TRANSMIT
RED
RED
GRN
RECEIVE
TXRING
NOTE: CENTER TAP OF T02 WAS NOT PULLED TO V3_3
IN DS33RZH11DK01A0 REVISION. PIN T02.2 IS PULLED
TO V3_3 WITH AWIRE IN THE DS33RZH11DK01A0 REVISION
PRINTED Thu Sep 22 16:21:49 2005
DS33ZH11-R11DK01A0
STEVE SCULLY
01/05/2005
BLOCK NAME: _te3liu_wan_dn. PARENT BLOCK: \_ds33zh11dk_design\
23/27(TOTAL)
1/1(BLOCK)
75 OHM RA
6
CB181
.1UF
330
R22
330 OHM (1%)
2
75 OHM RA
J39
PRBS
LOS
DM
GREEN
330
RED
RED
330
330
ZCSE
TTS
TESS
TDS1
TDS0
RMON
LBKS
LBO
ICE
EFE
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
RX_PLUS
RX_MINUS
TX_MINUS
PE-65968
.1UF
330 OHM (1%)
330
PE-65968
RCLK
44.736MHZ_3.3V
JMP_3
34.368MHZ_3.3V
ZCSE
RPOS
RCLK
TPOS
10K
RX_PLUS
RX_MINUS
RMON
TX_PLUS
MCLK
LBO
LOS
DM
PRBS
TTS
ICE
LBKS
EFE
TDS1
TDS0
TCLK
TX_MINUS
TESS
MCLK
TCLK
U13
8
43
10
40
13
39
26
29
33
28
34
35
42
44
18
2
46
15
17
16
22
9
11
5
6
20
21
37
38
1
3
4
7
12
14
19
23
24
25
30
31
32
36
41
45
47
48
27
R20
J38
3
4
5
1
2
3
4
5
1
T02
1
2
3
4
T03
1
2
3
4
6
Y05
4 5
1
8
YB01
4 5
1
8
RB150
CB185
JP09
1
3
2
J28
1
2
3
4
5 6
7
8
9
10
11
12
13 14
15 16
17 18
19
20
RB127
RB126
RB124
RB123
RB122
RB121
RB120
RB125
RB119
RB118
RB146
RB142
RB135
DS14
1
2
DS13
1
2
DS12
1
2
TX_PLUS
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
1:2
CONN_BNC_5P
CONN_BNC_5P
V3_3
V3_3
CONN_20P
15
9
5 6
3
2
1
16
18
20
8
10
7
19
17
4
12
11
1413
V3_3
VCC
1
OSC
GND OUT
VCC
1
OSC
GND OUT
V3_3
V3_3
OUT
OUT
IN
OUT
1:2
TX- TDSO
TDSI/OFSEL
EFE
ICE
RMON
TESS
TTS*
LBKS*
ZCSE*
RCLK
RPOS/RNRZ
RNEG
VSS<10>
VSS<11>
VSS<12>
VSS<13>
VSS<14>
VSS<15>
VSS<16>
VSS<17>
VSS<9>
VSS<8>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<0>
VSS<1>
VSS<6>
VSS<7>
PRBS
DM*
LOS*
LBO
VDD<0>
MCLK
VDD<5>
VDD<4>
VDD<3>
RX-
RX+
TCLK
TNEG
DS3150T
TX+
TPOS/TNRZ
VDD<2>
VDD<1>
DS21348 LIU, TRANSFORMERS AND CONNECTORS
BEGINING OF T1E1 LIU HIERARCHY BLOCK
/
BLOCK NAME: _te1liu_wan_dn. PARENT BLOCK: \_ds33zh11dk_design\
01/05/2005
1/2(BLOCK)
24/27(TOTAL)
STEVE SCULLY
DS33ZH11-R11DK01A0
A
D
G
B
C
F
H
E
CB177
8
7
6
5
4
3
2
1
JB03
2
1
RB177
2
1
RB149
2
1
RB148
2
1
R18
2
1
R19
1
2
3
4
16
15
14
T01
1
2
J41
2
1
R17
2
1
R16
2
1
CB180
5
6
7
8
11
10
9
T01
1
2
J40
RRING
TRING
RTIP
TTIP
0.0
0.0
1UF
51.1
61.9
61.9
0.0
0.0
11
1
1
1
11
1
0603YC104MAT
.1UF
0L_SMT0603_20PCT
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
CONN_BNC_5PIN
1:0.8
1:1
CONN_BNC_5PIN
CONN_RJ48
E
H
F
C
B
G
D
A
1:0.8
1:1
CONFIGURED FOR HW MODE
UNMARKED BIAS RESISTORS ARE 1.0K OHM
USE 1.544MHZ FOR T1
USE 2.048MHZ FOR E1
L1, L2, PBEO, BPCLK =NC
HARDWARE
END OF T1E1 LIU HIERARCHY BLOCK
SPARE (SOCKETED) OSCILLATOR
25/27(TOTAL)
2/2(BLOCK)
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
BLOCK NAME: _te1liu_wan_dn. PARENT BLOCK: \_ds33zh11dk_design\
A4_LO
PBEO
RCL_LOTC
VSM
HRST*
RRING
RPOS
RNEG
A0_HBE
TCLK
TNEG
TPOS
TRING
TTIP
INT*
AD1_MM0
AD0_MM1
AD2_LOOP1
AD3_LOOP0
AD4_TX1
RCLK
RTIP
A1_JAS
A2_JAMUX
AD5_TX0
AD6_TPD
AD7_CES
TEST
VSS
VSS1
MCLK
PBTS_RT0
ALE_SCLKE
BPCLK
A3_DJA
BIS0
BIS1
VDD
VDD1
WR*
RD*
CS*
L2
L1
10
9
8
7
65
4
3
2
1
J36
2019
18
17
1615
1413
12
11
10
9
8
7
65
4
3
2
1
J29
2019
18
17
1615
1413
12
11
10
9
8
7
65
4
3
2
1
J31
8
1
54
YB02
2
3
1
JP10
8
1
54
YB05
RB163
RB166
RB170
RB105
RB106
RB107
RB109
RB111
RB108
RB110
RB112
RB113
RB143
RB140
RB136
RB134
RB131
RB130
RB128
RB117
RB115
RB114
RB103
RB139
RB141
2
1
RB156
2
1
DS15
3
35
22
20
36
21
34
37
41
42
26
43
27
28
38
39
2
40
25
44
24
30
5
6
23
29
1
31
33
32
4
12
13
14
15
16
17
18
19
7
8
9
10
11
U12
2.048MHZ_3.3V
1.0K
BIS1
1.0K
BIS0
1.0K
L1
1.0K
L2
1.0K
RT1
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
1.0K
MM1
1.0K
MM0
1.0K
LOOP1
1.0K
LOOP0
1.0K
TX1
1.0K
TX0
1.0K
TPD
1.0K
CES
1.0K
TEST
1.0K
PBTS
1.544MHZ_3.3V
RED
TCLKI
RTIP
LO
RST
WR_NRZ
VSM
MCLK
RCLK
TTIP
TPOS
MM0
CS_EGL
RD_ETS
TX0
1
330
RT1
ALE
RLOS_LIU
TRING
RNEG
L2
JAS
TPD DJA
CES
RRING
RPOS
BIS1
1
PBTS
LOOP1
RCLK
MCLK
L1
HBE
JAMUX
CLK1544
1.0K
1.0K
1.0K
1.0K
ALE
CS_EGL
WR_NRZ
RD_ETS
VSM
HBE
JAS
LO
DJA
JAMUX
TX1
LOOP0
BIS0
TEST
MM1
JMP_3
MCLK
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
OUT
IN
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
CONN_20P
15
9
5 6
3
2
1
16
18
20
8
10
7
19
17
4
12
11
1413
CONN_20P
15
9
5 6
3
2
1
16
18
20
8
10
7
19
17
4
12
11
1413
VCC
1
OSC
GND
OUT
V3_3
OUT
OUT
VCC
1
OSC
GND OUT
IN
DS21348
L1
L2
CS*
RD*
WR*
VDD1
VDD
BIS1
BIS0
A3_DJA
BPCLK
ALE_SCLKE
PBTS_RT0
MCLK
VSS1
VSS
TEST
AD7_CES
AD6_TPD
AD5_TX0 A2_JAMUX
A1_JAS
RTIP
RCLK
AD4_TX1
AD3_LOOP0
AD2_LOOP1
AD0_MM1
AD1_MM0
INT*
TTIP
TRING
TPOS
TNEG
TCLK
A0_HBE
RNEG
RPOS
RRING
HRST*
VSM
RCL_LOTC
PBEO
A4_LO
BEGINNING OF MII ETHERNET HIERARCHY BLOCK
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
BE PLACED CLOSE TO PIN
C1 AND RBIAS MUST
COMPONETS FOR
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
STRAP ADAPTING OPTION OF DP83847
ANALOG SUPPLY CAPS
TO BE PLACED CLOSE TO
PIN 14 OF PHY
1
JMP_2
JMP_2
JMP_2
5.1K
LED_GDLINK_ADD2
LED_SPEED<1>
0.1UF
10UF
10UF
10UF
0.1UF
0.1UF
TXD2
TXD3
TXD0
TXD1
30
MDIO
MDC
5.1K
RXDV
RXD0
RX_ERR
RX_CLK
RXD1
RXD2
RXD3
RX_CRS
COL_DET
TX_CLK
TX_EN
5.1K
0.1UF
0.1UF
C1PIN
1
330
AN_V3_3
RBIAS
LED_RX_ADD4
LED_COL_ADD1
MII_CLK
0.1UF
RESET
10.0K
10UF
LED_TX_ADD3
LED_DPLX_ADD0
AN_V3_3
AMBER
AN_EN
AN1
AN0
10UF
0.1UF
0.1UF
0.1UF
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
1/2(BLOCK)
01/05/2005
STEVE SCULLY
DS33ZH11-R11DK01A0
PRINTED Fri Jun 30 02:47:52 2006
26/27(TOTAL)
BLOCK NAME: _mii_wan_dn. PARENT BLOCK: \_ds33zh11dk_design\
RB147
RB160
RB145
RB162
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U14
RB167
2
1
CB178
2
1
CB179
65
4
9
7
3
10
8
1
2
J30
65
4
9
7
3
10
8
1
2
J33
RB161
1
2
DS17
TPB10
TPB11
2
1
J34
2
1
J32
2
1
J35
2
1
CB169
2
1
C29
2
1
C26
2
1
CB187
2
1
CB184
2
1
CB188
CB163
C31
2
1
CB171
2
1
C32
2
1
CB170
2
1
CB168
PAGE:
DATE:TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
SHOULD BE PLACED CLOSE TO PHY
END OF MII ETHERNET HIERARCHY BLOCK
CAPS FOR XFRM CENTER TAP
RX_CLK
TX_CLK
30
30
RX_ERR
TX_EN
TXD0
TXD1
TXD2
30
30
TXD3
SYM_1
RD_P
TD_P
RD_N
.1UF
54.9
54.9
49.9
30
RXD1
RXD2
RXD3
30
30
RX_CRS
COL_DET
RD_P
RD_N TD_N
TD_P
RXDV
.1UF
.1UF
TD_N
49.9
RXD0
30
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
01/05/2005
DS33ZH11-R11DK01A0
STEVE SCULLY 2/2(BLOCK)
27/27(TOTAL)
BLOCK NAME: _mii_wan_dn. PARENT BLOCK: \_ds33zh11dk_design\
RB159
RB152
RB153
9
2
8
6
3
4
10
1
5
J37
CB190
CB162
RB171
CB189
RB172
R24
R23
RB137
RB144
RB154
RB155
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U14
RB151
PAGE:
DATE:TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
