INCH-POUND MIL-M-38510/207E 5 October 2007 SUPERSEDING MIL-M-38510/207D 16 February 2007 MILITARY SPECIFICATION MICROCIRCUIT, DIGITAL, 256-BIT, SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON Inactive for new design after 24 July 1995 This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535. 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, PROM microcircuits which employ thin film nichrome (NiCr) resistors, tungsten (W), titanium tungsten (TiW), or zapped vertical emitter (ZVE) as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead material and finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type 01, 03 02, 04 Circuit 32 word / 8 bits per word PROM with open collector 32 word / 8 bits per word PROM with tri-state output 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter E F Descriptive designator Terminals Package style GDIP1-T16 or CDIP2-T16 GDFP2-F16 or CDFP3-F16 16 16 Dual-in-line Flat pack Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to memory@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at http://assist.daps.dla.mil AMSC N/A FSC 5962 MIL-M-38510/207E 1.3 Absolute maximum ratings. Supply voltage range .................................................................... Input voltage range ....................................................................... Storage temperature range ........................................................... Lead temperature (soldering, 10 seconds) .................................... Thermal resistance, junction to case (JC): Cases E and F ........................................................................ Output voltage applied .................................................................. Output sink current ........................................................................ Maximum power dissipation (PD) .................................................. -0.5 V dc to +7.0 V dc -1.5 V dc at -10 mA to +5.5 V dc -65 to +150C +300C See MIL-STD-1835 1/ -0.5 V dc to +VCC 100 mA 739 mW dc 2/ Maximum junction temperature (TJ) .............................................. +175C 3/ 1.4 Recommended operating conditions. Supply voltage range (VCC) .......................................................... +4.5 V dc minimum to +5.5 V dc maximum Minimum high-level input voltage (VIH) ......................................... 2.0 V dc Maximum low-level input voltage (VIL) .......................................... 0.8 V dc Normalized fanout (each output) ................................................... 16 mA Case operating temperature range (TC) ........................................ -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard for Microelectronics. Interface Standard Electronic Component Case Outline (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) ____ 1/ Heat sinking is recommended to reduce the junction temperature. 2/ Must withstand the added PD due to short circuit test (e.g. IOS). 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions per method 5004 of MIL-STD-883. 2 MIL-M-38510/207E 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.3.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3.2 Truth tables. 3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C inspection (see 4.4), the devices shall be programmed by the manufacturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 Programmed devices. The truth table for programmed devices shall be as specified by the altered item drawing. 3.3.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6). 3.5 Electrical performance characteristics. Unless otherwise specified, the electrical performance characteristics are as specified in table I, and apply over the full recommended case operating temperature range. 3.6 Electrical test requirements. The electrical test requirements for each device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF-38535. 3.8 Processing options. Since the PROM is an unprogrammed device capable of being programmed by either the manufacturer or the user to result in a wide variety of PROM configurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified through group A testing as defined in 3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Manufacture-programmed PROM delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 14 (see Appendix A MIL-PRF-38535.) 3 MIL-M-38510/207E TABLE I. Electrical performance characteristics. Test Symbol High-level output voltage VOH Low-level output voltage VOL Input clamp voltage VIC Conditions 1/ -55C TC +125C unless other wise specified VCC = 4.5 V, IOH = -2 mA, VIL = 0.8 V, VIH = 2.0 V VCC = 4.5 V, IOL = 16 mA, Limits Device type Min 02, 04 2.4 Max Units V 01, 02, 03, 04 0.5 V TC = +25C 01, 02, 03, 04 -1.5 V VIL = 0.8 V, VIH = 2.0 V VCC = 4.5 V, IIN= -10 mA, Maximum collector cut-off current ICEX1 VCC = 5.5 V, VOH = 5.2 V 01, 03 100 A High impedance (off-state) output high current IOHZ VCC = 5.5 V, VOH = 5.2 V 02, 04 40 A High impedance (off-state) output low current IOLZ VCC = 5.5 V, VOL = 0.5 V 02, 04 -40 A High level input current IIH1 VCC = 5.5 V, VIN = 5.5 V 01, 02, 03, 04 50 A IIH2 VCC = 5.5 V, VIN = 4.5 V , special programming pin Low level input current IIL VCC = 5.5 V, VIN = 0.5 V Short circuit output current IOS Supply current ICC VCC = 5.5 V, VIN = 0 V, outputs = open Propagation delay time, high to low level logic, address to output tPHL1 VCC = 4.5 V and 5.5 V, Propagation delay time, low to high level logic, address to output tPLH1 Propagation delay time, high to low level logic, enable to output Propagation delay time, low to high level logic, enable to output VCC = 5.5 V, 2/ VO = 0.0 V CL = 30 pF, see figure 4 VCC = 4.5 V and 5.5 V, CL = 30 pF, see figure 4 tPHL2 tPLH2 VCC = 4.5 V and 5.5 V, CL = 30 pF, see figure 4 VCC = 4.5 V and 5.5 V, CL = 30 pF, see figure 4 100 01, 02, 03, 04 -1.0 -250 A 02, 04 -10 -100 mA 01, 02, 03, 04 130 mA 01, 02 80 ns 03, 04 35 01, 02 80 03, 04 35 01, 02 50 03, 04 25 01, 02 50 03, 04 25 1/ Complete terminal conditions shall be specified in table III. 2/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test. 4 ns ns ns MIL-M-38510/207E Device types 01, 02, 03, and 04 Case outlines E and F Terminal number Terminal symbol 1 O1 2 O2 3 O3 4 O4 5 O5 6 O6 7 O7 8 GND 9 O8 10 A0 11 A1 12 A2 13 A3 14 A4 15 CE 16 VCC FIGURE 1. Terminal connections. 5 MIL-M-38510/207E Word Address number CE A4 A3 A2 A1 A0 NA L X X X X X NA H X X X X X Word DATA number CE O1 O2 O3 O4 O5 O6 O7 O8 NA L 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ NA H OC OC OC OC OC OC OC OC NOTES: 1. 2. 3. 4. 5. NA = Not applicable. X = Input may be high level, low level or open circuit. OC = Open circuit (high resistance output). Program readout can only be accomplished with enable input at low level. The outputs for an unprogrammed device shall be high for circuits A and B; and shall be low for circuits C, G, and H. FIGURE 2. Truth table (unprogrammed). 6 MIL-M-38510/207E FIGURE 3. Functional block diagrams. 7 MIL-M-38510/207E NOTE: This circuit is also used as circuit H. FIGURE 3. Functional block diagrams - Continued. 8 MIL-M-38510/207E FIGURE 3. Functional block diagrams - Continued. 9 MIL-M-38510/207E NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory. 2. CL = 30 pF minimum, including jig and probe capacitance; R1 = 330 25% and R2 = 680 20 %. 3. Outputs may be under load simultaneously. FIGURE 4. Switching time test circuit. 10 MIL-M-38510/207E NOTE: All other waveform characteristics shall be as specified in table IVA. FIGURE 5A. Typical programming voltage waveforms during programming for circuit A. 11 MIL-M-38510/207E NOTES: 1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check respectively. 2. All other waveform characteristics shall be as specified in table IVB. FIGURE 5B. Typical programming voltage waveforms during programming for circuit B. 12 MIL-M-38510/207E NOTE: All other waveform characteristics shall be as specified in tables IVC. FIGURE 5C. Typical programming voltage waveforms during programming for circuit C. 13 MIL-M-38510/207E FIGURE 5D. Typical programming voltage waveforms during programming for circuit G. 14 MIL-M-38510/207E NOTES: 1. All other waveform characteristics shall be as specified in tables IVH. 2. Programming verification at both high and low VCC margins is optional. For convenience, verification can also be executed at the operating VCC limits specified in the dc characteristics. FIGURE 5E. Typical programming voltage waveforms during programming for circuit H. 15 MIL-M-38510/207E 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF-38535, appendix B. d. Class B devices processed to an altered item drawing may be programmed either before or after burn-in at the manufacturer's discretion. The required electrical testing shall include, as a minimum, the final electrical tests for programmed devices as specified in table II herein. Class S devices processed by the manufacturer to an altered item drawing shall be programmed prior to burn-in. 4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535. Qualification data for subgroups 7 through 11 shall be by attributes only. 4.3.1 Qualification extension. When authorized by the qualifying activity, for qualification inspection, if a manufacturer qualifies faster device type which is manufactured identically to slower device types on this specification, then the slower device types may be qualified by conducting only group A electrical tests and any electrical specified as additional group C subgroups and submitting data in accordance with MIL-PRF38535 (for example, groups B, C, and D tests are not required). 4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF-38535 and as specified herein for groups A, B, C, and D inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows: a. Electrical test requirements shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted. c. For unprogrammed devices, a sample shall be selected to satisfy programmability requirements prior to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to programming (see 3.3.2.1). If more than 2 devices fail to program, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 24 total devices with no more than 4 total device failures allowed. d. For unprogrammed devices, 10 devices from the programmability sample shall be subjected to the requirements of group A, subgroups 9, 10, and 11. If more than two total devices fail in all three subgroups, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 20 total devices with no more than 4 total device failures allowable. 16 MIL-M-38510/207E TABLE II. Electrical test requirements. Subgroups (see table III) 1/, 2/, 3/ Class S Class B devices devices MIL-PRF-38535 test requirements Interim electrical parameters 1 Final electrical test parameters for unprogrammed devices Final electrical test parameters for programmed devices Group A test requirements Group B end-point electrical parameters when using the method 5005 QCI option Group C end-point electrical parameters Group D test requirements 1 1*, 2, 3, 7*, 8 1*, 2, 3, 7* 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1*, 2, 3, 7*, 8 1*, 2, 3, 7*, 8, 9, 1, 2, 3, 7, 8 9, 10, 11 1, 2, 3, 7, 8 1, 2, 3, 7, 8 N/A 1, 2, 3, 7, 8 1/ * indicates PDA applies to subgroups 1 and 7 (see 4.2c). 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 shall consist of verifying the pattern specified. 4.4.2 Group B inspection. Group B inspection shall be in accordance with table II MIL-PRF-38535. 4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burnin test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MILSTD-883. c. For qualification inspection, at least 50 percent of the sample selected for testing in subgroup 1 shall be programmed (see 3.3.2). For quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the life tests. 4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535. Endpoint electrical parameters shall be as specified in table II herein. 17 TABLE III. Group A inspection for device types 01 and 03. Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage; inputs not designated are 2.0 V, low 0.8 V). Subgroup Symbol 1 TC = 25C VIC VOL 18 IIH1 IIH2 ICEX ICC 3007 " " " " " " " 3009 " " " " " 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3010 " " " " " 21 22 23 24 25 26 " " " " " " " " 3005 27 28 29 30 31 32 33 34 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O1 O2 O3 O4 O5 O6 O7 GND O8 A0 A1 A2 A3 A4 CE VCC -10mA 4.5V " " " " " GND " " " " " 16mA 16mA 16mA 16mA 16mA 16mA 16mA " " " " " " " " " " " " " " -10mA -10mA -10mA -10mA -10mA 1/ 2/ 3/ " " " " " " " 16mA 0.5V 5.2V 5.2V 5.2V 5.2V 5.2V 5.2V " " " " " " " " " 1/ 3/ " " " " " " " 1/ 2/ 3/ 4/ " " " " " " 0.5V " " " " " " " 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.2V GND 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. See footnotes at end of table. 1/ 3/ " " " " " " " 0.5V " " " " " " 5.2V 1/ 3/ " " " " " " " GND GND GND GND 4.5V 5/ " " " " " " " " GND " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " Measured terminal Test limits Unit Min A0 A1 A2 A3 A4 CE O1 O2 O3 O4 O5 O6 O7 O8 A0 A1 A2 A3 A4 CE A0 A1 A2 A3 A4 CE O1 O2 O3 O4 O5 O6 O7 O8 VCC -1.0 " " " " " Max -1.5 " " " " " V " " " " " 0.5 " " " " " " " -250 " " " " " " " " " " " " " A " " " " " 50 " " " " 100 " " " " " " " " " " " " " " 130 " " " " " " " " mA MIL-M-38510/207E IIL MIL- Cases E,F STD883 Test method no. 1 2 3 4 5 6 TABLE III. Group A inspection for device types 01 and 03 - Continued. Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage; inputs not designated are 2.0 V, low 0.8 V, or open). 9 10 11 12 13 14 15 16 O8 A0 A1 A2 A3 A4 CE VCC 7 TC = 25C 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " 6/ " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 6/ " " " " " " " 8 9 TC = 25C 7/ 8/ 8/ 8/ 8/ 8/ GND 8/ Outputs 9/ ns " 8/ 8/ 8/ 8/ 8/ GND 8/ " 9/ " " 10/ 10/ 10/ 10/ 10/ 10/ 10/ " 9/ " " 10/ 10/ 10/ 10/ 10/ 10/ 10/ " 9/ " 19 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. See footnotes at end of table. Measured terminal Test limits Unit Min Max MIL-M-38510/207E Cases MIL1 2 3 4 5 6 7 8 E,F STD883 Test GND O2 O3 O4 O5 O6 O7 O1 method no. Func6/ 36 6/ 6/ 6/ 6/ 6/ 6/ GND 6/ " " " " " " " " tional " " " " " " " " " " test " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and -55C. 37 7/ 7/ 7/ 7/ 7/ 7/ 7/ GND tPHL1 GALPAT Fig. 4 38 " " " " " " " " tPLH1 GALPAT Fig. 4 39 " " " " " " " " tPHL2 Sequential Fig. 4 40 " " " " " " " " tPLH2 Sequential Fig. 4 Subgroup Symbol TABLE III. Group A inspection for device types 02 and 04. Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage; inputs not designated are 2.0 V, low 0.8 V). Subgroup Symbol 1 TC = 25C VIC VOL VOH IIH1 IIH2 IOHZ 3007 " " " " " " " 3006 " " " " " " " 3009 " " " " " 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3010 " " " " " 29 30 31 32 33 34 35 36 37 38 39 40 41 42 See footnotes at end of table. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O1 O2 O3 O4 O5 O6 O7 GND O8 A0 A1 A2 A3 A4 CE VCC -10mA 4.5V " " " " " GND " " " " " 16mA 16mA 16mA 16mA 16mA 16mA 16mA -2.0mA -2.0mA -2.0mA -2.0mA -2.0mA -2.0mA -2.0mA " " " " " " " " " " " " " " " " " " " " " " -10mA -10mA -10mA -10mA -10mA 1/ 3/ 1/ 3/ 1/ 2/ 3/ 1/ 2/ 3/ 1/ 3/ " " " " 4/ " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 16mA 1/ 11/ 1/ 11/ 1/ 11/ 1/ 11/ 1/ 11/ 12/ 13/ 12/ 13/ 12/ 13/ 12/ 13/ 12/ 13/ " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " -2.0mA 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V " " " " " " 5.2V 5.2V 5.2V 5.2V 5.2V 5.2V 5.2V " " " " " " " " 0.5V " " " " " " " 1/ " " " " " " " 5.5V 5.5V 5.5V 5.5V 5.5V 5.2V 4.5V 4/ 5.5V " " " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " Measured terminal Test limits Unit Min A0 A1 A2 A3 A4 CE O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 A0 A1 A2 A3 A4 CE A0 A1 A2 A3 A4 CE O1 O2 O3 O4 O5 O6 O7 O8 2.4 " " " " " " " -1.0 " " " " " Max -1.5 " " " " " V " " " " " 0.5 " " " " " " " -250 " " " " " " " " " " " " " " " " " " " " " A " " " " " 50 " " " " 100 " " " " " " 40 " " " " " " " " " " " " " " " MIL-M-38510/207E 20 IIL MIL- Cases E,F STD883 Test method no. 1 2 3 4 5 6 TABLE III. Group A inspection for devices type 02 and 04 - Continued. Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage; inputs not designated are 2.0 V, low 0.8 V). Subgroup Symbol 1 TC = 25C MILSTD883 method IOLZ ICC 3005 Cases E,F Test no. 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O1 O2 O3 O4 O5 O6 O7 GND O8 A0 A1 A2 A3 A4 CE VCC 5.5V GND 5.5V " " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 VCC 0.5V " " " " " " " " " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V GND " " " " " " " " 0.5V GND GND GND GND GND 2 3011 52 GND " 1/ 11/ 1/ 11/ 1/ 11/ 1/ 11/ 1/ 11/ " 12/ 13/ 12/ 13/ 12/ 13/ 12/ 13/ 12/ 13/ 53 GND " " " " " " " 54 GND " " " " " " " 55 GND " " " " " " " 56 GND " " " " " " " 57 GND " " " " " " " 58 GND " " " " " " " 59 " GND Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. IOS 21 TC = 25C Functional tests 6/ 60 6/ 6/ 6/ 6/ 6/ 6/ 6/ GND 10 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and TC = -55C. 61 7/ 7/ 7/ 7/ 7/ 7/ 7/ GND tPHL1 GALPAT Fig. 4 62 " " " " " " " " tPLH1 GALPAT Fig. 4 63 " " " " " " " " tPHL2 Sequential Fig. 4 64 " " " " " " " " tPLH2 Sequential Fig. 4 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. 8 9 TC = 25C See footnotes at end of table. Test limits Unit Min -10 " " " " " " " Max -40 " " " " " " " 130 A " " " " " " " mA -100 " " " " " " " " " " " " " " " 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ Outputs 6/ 7/ 8/ 8/ 8/ 8/ 8/ GND 8/ Outputs 9/ ns " 8/ 8/ 8/ 8/ 8/ GND 8/ " 9/ " " 10/ 10/ 10/ 10/ 10/ 10/ 10/ " 9/ " " 10/ 10/ 10/ 10/ 10/ 10/ 10/ " 9/ " MIL-M-38510/207E 7 Measured terminal MIL-M-38510/207E TABLE III. Group A inspection - Continued. 1/ For programmed devices, select an appropriate address to acquire the desired output state, VIL = 0.8 V, VIH = 2.0 V. 2/ For unprogrammed devices, apply 11.0 V on pins 10 ( A0 ) and 14 ( A4 ) for circuit A devices. 3/ For unprogrammed 02 devices ( VOL test ), apply 0 V on pins 10 ( A0 ) through 14 ( A4 ) for circuit G. 4/ For unprogrammed devices, apply 12.0 V on pin 14 ( A4 ) for circuit B devices. 5/ This test may, at the manufacturer's option, be performed with VIH = 5.5 V (pin 15) and test limit of 50 A maximum. 6/ The functional tests shall verify that no fuses are blown for unprogrammed devices or that the truth table specified in the altered item drawing exists for programmed devices (see table II and 3.3.2.2). All bits shall be tested. Terminal conditions shall be as follows: a. b. c. Inputs: H = 3.0 V, L = 0.0 V. Outputs: Output voltage shall be: H 1.0 V and L < 1.0 V. The functional tests shall be performed with VCC = 4.5 V and VCC = 5.5 V. 7/ The outputs are loaded per figure 4. 8/ GALPAT (PROGRAMMED PROM). This program will test all bits in the array, the addressing and interaction between bits for ac performance tPHL1 and tPLH1 . Each bit in the pattern is fixed by being programmed with a "H" and "L". Description: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Word 0 is read. Word 1 is read. Word 0 is read Word 2 is read. Word 0 is read. The reading procedure continues back and forth between word 0 and the next higher numbered word until word 255 is reached, then increments to the next word and reads back and forth as in step 1 through step 6 and shall include all words. 2 Step 7. Pass execution time = ( n + n ) x cycle time. N = 256. Step 8. The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V. 9/ Device tPHL1 tPLH1 tPHL2 tPLH2 01, 02 80 ns 80 ns 50 ns 50 ns 03, 04 35 ns 35 ns 25 ns 25 ns 22 MIL-M-38510/207E TABLE III. Group A inspection - Continued. 10/ SEQUENTIAL (PROGRAMMED PROM). This program will test all bits in the array for tPHL2 and tPLH2. Description: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Each word in the pattern is tested from the enable lines to the output lines for recovery. Word 0 is addressed. Enable line is pulled high to low and low to high. tPHL2 and tPLH2 are read. Word 1 is addressed. Same enable sequence as above. The reading procedure continues until word 255 is reached. Pass execution time = 256 x cycle time. The sequential tests shall be performed with VCC = 4.5 V and 5.5 V. 11/ For unprogrammed 01, 02 devices (with date codes before 8601), apply 10.0 V to pin 10 ( A0 ), apply 0.5 V to pin 11 ( A1 ), and other 5.0 V on all other addresses for circuit C. 12/ For unprogrammed 02 devices ( VOH test ), with date codes before 8713, apply 0 V to pins 10 ( A0 ) through 13 ( A3 ), and 11.5 V to pin 14 ( A4 ), with date codes of 8713 or later apply 3.0 V to pins 10 ( A0 ) through 13 ( A3 ), and 10.5 V to pin 14 ( A4 ) for circuit G. 13/ For unprogrammed devices 01, 02 (with date codes of 8601 or later), 03 and 04, apply 10.0 V to pin 10 ( A0 ), 0.5 V to pins 12, 13, 14, ( A2, A3, A4 ) and 5.0 V to all other addresses for circuit C. 23 MIL-M-38510/207E 4.5 Methods of inspection. Methods of inspection shall be specified and as follows: 4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal. 4.6 Programming procedure identification. The programming procedure to be utilized shall be identified by the manufacturer's circuit designator. The circuit designator is cross referenced in paragraph 6.6 herein with the manufacturer's symbol or CAGE number. 4.7 Programming procedure for circuit A. The programming characteristics in table IVA and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5A and the programming characteristics in table IVA shall apply to these procedures. b. Address the PROM with the binary address of the word to be programmed. Address inputs are TTL compatible. An open circuit shall not be used to address the PROM. c. Apply VPL voltage to VCC. d. Bring the CE X inputs high and the CE X inputs low to disable the device. The chip enables are TTL compatible. An open circuit shall not be used to disable the device. e. Disable the programming circuitry by applying a voltage of VOPD to the outputs of the PROM. f. Raise VCC to VPH with rise time less than or equal to tTLH. g. After a delay equal to or greater than tD1 apply only one pulse with amplitude of VOPE and duration of tp to the output selected for programming. Note that the PROM is supplied with fuses intact, which generates an output high. Programming a fuse will cause the output to go low. h. Lower VCC to VPL following a delay to tD2 from programming enable pulse applied to an output. i. Enable the PROM for verification by applying VIL to CE X and VIH to CE X . j. Apply VPHV to VCC and verify bit is programmed. k. Repeat steps a through j for all other bits to be programmed in the PROM. l. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 24 MIL-M-38510/207E TABLE IVA. Programming characteristics for circuit A. Parameter Limits 1/ Symbol Unit Min Recommended Max VIH 2.4 5.0 5.0 V VIL 0.0 0.4 0.5 " VPH 3/ 10.75 11.0 11.25 V VPL 0.0 0.0 1.5 V Program verify VPHV --- 5.5 --- V Verify voltage VR 4/ 4.5 5.0 5.5 V IILP --- -300 -600 A tTLH 1 5 10 s tTHL 1 5 10 " tD1 10 10 20 s tD2 1 5 5 " Programming pulse width tP 5/ 90 100 110 s Programming duty cycle PDC 6/ --- 30 60 % Output voltage Enable VOPE 7/ 10.5 10.5 11.0 V Output voltage Disable VOPD 7/ 0.0 5.0 5.5 V Address input voltage 2/ Programming Voltage to VCC low Programming input low current at VPH Programmed voltage (VCC) transition time Programming delay During the programming the chip must be disabled for proper operation. 1/ TC = +25C. 2/ No inputs should be left open for VIH. 3/ VPH source must be capable of supplying one ampere. 4/ It is recommended that post programming dual verification be made at VR minimum and VR maximum. 5/ Note step j in programming procedure. 6/ Programming duty cycle applies to DIPs only. 7/ VOPE source must be capable of supplying 10 mA minimum. 25 MIL-M-38510/207E 4.8 Programming procedure for circuit B. The programming characteristics in table IVB and the following procedures shall be used for programming the devices: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5B and the programming characteristics of table IVB shall apply to these procedures. b. Raise VCC to 5.5 volts. c. Address the PROM with binary address of the selected word to be programmed. Address inputs are TTL compatible. d. Disable the chip by applying VIH to the CE input. CE input is TTL compatible. e. Apply the VPP pulse to the CE pin. In order to insure that the output transistor is off before increasing the voltage on the output pin, the program pin's voltage pulse shall precede the output pin's programming pulse by tD1 and leave after the output pin's programming pulse by tD2 (see figure 5B). f. Apply the VOUT pulse with duration of tP to the output selected for programming (see table IVB). The outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially applying VOUT pulses to each output to be programmed. h. Repeat 4.8b through 4.8g for all bits to be programmed. i. Enable the chip by applying VIL to the CE input and verify the program. Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at TC = 25C. j. For classes S and B devices, if any bit does not verify as programmed it shall be considered a programming reject. 26 MIL-M-38510/207E TABLE IVB. Programming characteristics for circuit B. Parameter Symbol Limits 1/ Conditions Min Current into output during programming before the fuse has programmed IOUT1 Current into output during programming after the fuse has programmed IOUT2 Rise time of program pulse applied to the data out from 10% to 90% tTLH Chip enable ( CE ) pin pulse width tPP Pulse width of programming voltage tP Fall time of the pulse applied to the CE from 90% to 10% tTHL Required time delay between disabling memory output and application of output programming pulse Required time delay between removal of programming pulse and enabling memory output 35 VCC = 5.5 V, VOUT = 20 V 3 DC s Chip disabled VCC = 5.5 V 80 95 110 s Chip disabled VCC = 5.5 V 1 40 s 50 1000 ns 90 s 80 ns 5.40 5.50 5.60 V TC = 25C, VCC = 4.20 V chip enabled 11 12 13 mA TC = 25C, VCC = 6.0 V chip enabled 0.19 0.2 0.21 mA 25 % 26 V T P / TC 20 VOUT IL mA 70 100 IOLV2 mA 60 Measured at 1.5 V levels Output current required during verification Max 50 tD2 IOLV1 Required current limit of the power supply feeding the output during programming VCC = 5.5 V, VOUT = 25 V 70 Output current required during verification Required programming voltage on the output pin 0.1 Measured at 1.5 V levels VCCP Maximum duty cycle during automatic programming of enable and output pin VCC = 5.5 V, VOUT = 9.0 V tD1 VCC required during programming Recommended Unit VOUT = 25 V, VCC = 5.5 0 V 1/ TC = +25C. 27 150 20 mA MIL-M-38510/207E 4.9 Programming procedure for circuit C. The programming characteristics in table IVC and the following procedures shall apply for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5C and the programming characteristics in table IVC shall apply for programming to these procedures. b. Terminate all device outputs with a 10 k resistor to VCC. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10 s), apply only one VOUT pulse to the output to be programmed. Program one output at a time. e. After a tD delay (10 s), pulse CE input to logic "0" for a duration of tP. f. After a tD delay (10 s), remove the VOUT pulse from the programmed output. Note that the PROM is supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a high-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay of tD between pulses as shown on figure 5C. h. Repeat 4.9b through 4.9g for all other bits to be programmed. i. To verify programming after tD (10 s) delay, lower VCC to VCCH and apply a logic "0" level to both CE input. The programmed output should remain in the "1" state. Again lower VCC and VCCL and verify that the programmed output remains in the "1" state. j. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 28 MIL-M-38510/207E TABLE IVC. Programming characteristics for circuit C. Parameter Programming voltage to VCC Symbol VCCP 1/ Limits 1/ Conditions ICCP = 375 75 mA; transient or steady-state Unit Min Recommended Max 9.5 10.0 10.5 V Verification upper limit VCCH 5.3 5.5 5.7 V Verification lower limit VCCL 4.3 4.5 4.7 V Verify threshold VS 2/ 0.9 1.0 1.1 V 200 250 300 mA 5.5 V 0.8 V Programming supply current Input voltage high level "1" Input voltage low level "0" ICCP VCCP = +8.75 0.25 V VIH 2.4 VIL 0 0.4 Input current IIH VIH = +5.5 V 50 A Input current IIL VIL = +0.4 V -500 A Output programming voltage Output programming current Programming voltage transition time VOUT 3/ IOUT IOUT = 65 3 mA, transient or steady-state VOUT = +17 1 V 15.0 15.5 16.0 V 62 65 68 mA 50 s 500 s tTLH 10 CE programming pulse width tP 300 Pulse sequence delay tD 10 Programming duty cycle tPR / 400 s 50 tPR + tPS 1/ Bypass VCC to GND with a 0.01 F capacitor to reduce voltage spikes. 2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt. 3/ Care should be taken to insure the 17 1 V output voltage is maintained during the entire fusing cycle. The recommended supply is a constant current source clamped at the specified voltage limit. 29 % MIL-M-38510/207E 4.10 Programming procedure for circuit G. The programming characteristics on table IVG and the following procedures shall be used for programming. a. Connect the device in the electrical configuration of programming. The waveforms on figure 5D and the programming characteristics of table IVG shall apply to these procedures. b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to one or more active low chip enable inputs. NOTE: Address and enable inputs must be driven with TTL logic levels during programming and verification. c. Increase VCC from nominal to VCCP (10.5 0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/s). Since VCC is the source of the current required to program the fuse, as well as the ICC for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0 volts. d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 0.5 V). Limit the slew rate to IRR (1.0 to 10.0 V/s). This voltage change may occur simultaneously with the VCC increase to VCCP, but must precede it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20 k minimum (remember that the outputs of the device are disabled at this time). e. Enable the device by taking the chip enable(s) to a low level. This is done with a pulse PWE for 10 s. The 10 s duration refers to the time that the circuit (device) is enabled. Normal input levels are used and rise and fall times are not critical. f. Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing VCC to 5.0 V (0.25 V). The device must be enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits. g. If the device is not to be tested for VOH over the entire operating range subsequent to programming, the verification of step f is to be performed at a VCC level of 4.0 volt ( 0.2 V ). VOH, during the 4 volt verification, must be at least 2.0 volts. The 4 volt VCC verification assures minimum VOH levels over the entire operating range. h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified. i. For class S and B devices, if any bit does not verify as programmed it shall be considered a programming reject. 30 MIL-M-38510/207E TABLE IVG. Programming characteristics for circuit G. Parameter Required VCC for programming ICC during programming Required output voltage for programming Output current while programming Rate of voltage change of VCC or output Programming pulse width (enabled) Required VCC for verification Maximum duty cycle for VCC at VCCP Symbol VCCP ICCP Unit Min Recommended Max 10.0 10.5 11.0 V 750 mA 11.0 V 20 mA 10.0 V/s VCC = 11 V 10.0 VOP IOP Limits 1/ Conditions 10.5 VOUT = 11 V IRR 1.0 PWE 9 10 11 s VCCV 3.8 4.0 4.2 V 25 25 % MDC Address set-up time t1 100 ns VCCP set-up time t2 5 s VCCP hold time t5 100 ns VOP set-up time t3 100 ns VOP hold time t4 100 ns 2/ 1/ TC = +25C. 2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or faster than VOP. 31 MIL-M-38510/207E 4.11 Programming procedure for circuit H. The programming characteristics in table IVH and the following procedures shall apply for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5E and the programming characteristics in table IVH shall apply for programming to these procedures. b. Terminate all device outputs with a 10 k resistor to VCC. The 10 k is the pullup resistor for open collector devices. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10 s), apply VOPF output to be programmed. Program one output at a time. Note leading edge rise time restrictions. e. After a tD delay (10 s), pulse CE input to logic "0" for a duration of tP. f. After a tD delay (10 s), remove the VOPF pulse from the programmed output. Note that the PROM is supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a high-level logic in the verify mode. g. Repeat 4.11d through 4.11f to program other bits at the same address. h. To verify programming of all bits at the same address, after tD delay lower VCC to VCCVL and apply a logic low level to the CE X input. All programmed outputs should remain in the same logic high state. i. After tD delay, repeat steps 4.11c through 4.11h to program and verify all other address locations. j. After tD delay, raise VCC to VCCVH and verify all memory locations by applying a logic low level to CE and cycling through all device addresses. k. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 32 MIL-M-38510/207E TABLE IVH. Programming characteristics for circuit H. Parameter Symbol Limits Conditions Unit Min Recommended Max 8.5 8.75 9.0 V Programming voltage to VCC VCCP 1/ Verification upper limit VCCVH 5.3 5.5 5.7 V Verification normal limit VCCVN 4.75 5.0 5.25 V Verification lower limit VCCVL 4.3 4.5 4.7 V Verify threshold VS 2/ 1.4 1.5 1.6 V 350 500 mA VIH 2.4 5.5 V VIL 0 0.8 V Programming supply current Input voltage high level "1" Input voltage low level "0" ICCP ICCP = 425 75 mA; transient or steady-state VCCP = +8.75 0.25 V Input current IIH VIH = +5.5 V 50 A Input current IIL VIL = +0.4 V -500 A 18.0 V 220 mA Forced output voltage (program) Forced output current (program) VOPF 3/ IOPF IOUT = 200 20 mA, transient or steady-state 17 VOPF = +17 1 V 180 17.5 Output pulse rise time tRZ 17 20 25 s CE programming pulse width tP 10 10 25 s Pulse sequence delay tD 5 10 Address program verify cycle tPVA 1 ms Memory program verify time (continuous) tPVM 20 sec Fusing attempts per link FL 1 cycle s 1/ Bypass VCC to GND with a 0.01 F capacitor to reduce voltage spikes. 2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt. 3/ The voltage should be maintained within specified limits during the entire fusing cycle. For a transient current of 150 mA, limit voltage spikes to a maximum slew rate of 2 V/s and 10 s maximum recovery. 33 MIL-M-38510/207E 5. PACKAGING 5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see 6.2). When packaging of materiel is to be performed by DoD or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. Packaging requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense Agency, or within the military service's system command. Packaging data retrieval is available from the managing Military Department's or Defense Agency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity. 6. NOTES (This section contains information of a general or explanatory nature which may be helpful, but is not mandatory.) 6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing equipment. 6.2 Acquisition requirements. Acquisition documents should specify the following: a. Title, number, and date of the specification. b. PIN and compliance identifier, if applicable (see 1.2). c. Requirements for delivery of one copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. Requirements for certificate of compliance, if applicable. e. Requirements for notification of change of product or process to contracting activity in addition to notification to the qualifying activity, if applicable. f. Requirements for failure analysis (including required test condition of method 5003 of MIL-STD-883), corrective action, and reporting of results, if applicable. g. Requirements for product assurance options. h. Requirements for special lead lengths, or lead forming, if applicable. Unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the Government. i. Requirement for programming the device, including processing option. j. Requirements for "JAN" marking. k. Packaging Requirements (see 5.1) 6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990. 34 MIL-M-38510/207E 6.4 Superseding information. The requirements of MIL-M-38510 have been superseded to take advantage of the available Qualified Manufacturer Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M38510 in this document have been replaced by appropriate references to MIL-PRF-38535. All technical requirements now consist of this specification and MIL-PRF-38535. The MIL-M-38510 specification sheet number and PIN have been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows: GND ............................................ Electrical ground (common terminal). IIN ............................................... Current flowing into an input terminal. VIC .............................................. Input clamp voltage. VIN .............................................. Voltage level at an input terminal. 6.6 Logistic support. Lead materials and finishes (see 3.4) are interchangeable. Unless otherwise specified, microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material and finish A (see 3.4). Longer length leads and lead forming should not affect the part number. It is intended that spare devices for logistic support be acquired in the unprogrammed condition (see 3.8.1) and programmed by the maintenance activity, except where use quantities for devices with a specific program or pattern justify stocking of preprogrammed devices. 6.7 Substitutability. The cross-reference information below is presented for the convenience of users. Microcircuits covered by this specification will functionally replace the listed generic-industry type. Generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation to case size. The presence of this information should not be deemed as permitting substitution of generic-industry types for MIL-M-38510 types or as a waiver of any of the provisions of MIL-PRF-38535. 1/ 2/ Military device type Generic-industry type Circuit designator Fusible links 01 1/ 7602 / Harris Semiconductor, CAGE 34371 A NiCr 01 1/ 5330 / Monolithic Memories, CAGE 56364 B NiCr 02 DM54S288 / National Semiconductor, CAGE 27014 G TiW / W 02 1/ 7603 / Harris Semiconductor, CAGE 34371 A NiCr 02 1/ 5331 / Monolithic Memories, CAGE 56364 B NiCr 01, 03 82S23A / Signetics Corporation, CAGE 18324 C NiCr 02, 04 82S123A / Signetics Corporation, CAGE 18324 C NiCr 01, 03 82S23A / Signetics Corporation, CAGE 18324 H 2/ NiCr 01, 03 82S23A/QP Semiconductor H 2/ ZVE 02, 04 82S123A / Signetics Corporation, CAGE 18324 H 2/ NiCr 02, 04 82S123A/QP Semiconductor H 2/ ZVE This generic industry type is no longer manufactured. Updated circuit C to circuit H to reflect the current programming method. Contact the manufacturer for the correct programming method being used. 35 MIL-M-38510/207E 6.8 Change from previous issue. Marginal notations are used in this revision to identify changes with respect to the previous issue. Custodians: Army - CR Navy - EC Air Force - 11 DLA - CC Preparing activity: DLA - CC Review activities: Army - SM, MI Navy - AS, CG, MC, SH TD Air Force - 03, 19, 99 (Project 5962-2007-008) NOTE: The activities listed above were interested in this document as of the date of this document. Since organization and responsibilities can change, you should verify the currency of the information above using the ASSIST Online database at http://assist.daps.dla.mil. 36