INCH-POUND
MIL-M-38510/207E
5 October 2007
SUPERSEDING
MIL-M-38510/207D
16 February 2007
MILITARY SPECIFICATION
MICROCIRCUIT, DIGITAL, 256-BIT, SCHOTT KY, BIPOLAR,
PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON
This specification is approved for use by all Departments and Agencies of the Department of Defense.
The requirements for acquiring the prod uct herein shall consist of this specification sheet and MIL-PRF 385 35.
1. SCOPE
1.1 Scope. This specification covers the det ail requirements for monolithic silicon, PROM microcircuits which employ
thin film nichrome (NiCr) resistors, tungsten (W), titanium tungsten (TiW), or zapped vertic al emitter (Z VE) as the fusible link
or programming element. Two product assurance classes and a choice of case outlines and lead material and finishes are
provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-3851 0
have been superseded by MIL-PRF-38535, (see 6.4).
1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein.
1.2.1 Device types. The device types are as follows:
Device type Circuit
01, 03 32 word / 8 bits per word PROM with open collector
02, 04 32 word / 8 bits per word PROM with tri-state output
1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535.
1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as foll ows:
Outline letter Descriptive designator Terminals Package style
E GDIP1-T16 or CDIP2-T16 16 Dual-in-line
F GDFP2-F16 or CDFP3-F16 16 Flat pack
Comments, suggestions, or questions on this document should be addressed to: Commander, Defense
Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to
memory@dscc.dla.mil. Since contact information ca n change, you may want to verify the currenc y of this
address information using the ASSIST Online database at http://assist.daps.dla.mil
AMSC N/A FSC 5962
Inactive for new design after 24 July 1995
MIL-M-38510/207E
2
1.3 Absolute maximum ratings.
Supply voltage range .................................................................... -0.5 V dc to +7.0 V dc
Input voltage range ....................................................................... -1.5 V dc at -10 mA to +5.5 V dc
Storage temperature range ........................................................... -65° to +150°C
Lead temperature (soldering, 10 seconds) .................................... +300°C
Thermal resistance, junction to case (θJC):
Cases E and F ........................................................................ See MIL-STD-1835 1/
Output voltage applied .................................................................. -0.5 V dc to +VCC
Output sink current ........................................................................ 100 mA
Maximum power dissipation (PD) .................................................. 739 mW dc 2/
Maximum junction temperature (TJ) .............................................. +175°C 3/
1.4 Recommended operating conditions.
Supply voltage range (VCC) .......................................................... +4.5 V dc minimum to
+5.5 V dc maximum
Minimum high-level input voltage (VIH) ......................................... 2.0 V dc
Maximum low-level input voltage (VIL) .......................................... 0.8 V dc
Normalized fanout (each output) ................................................... 16 mA
Case operating temperature rang e (TC) ........................................ -55 °C to +125 °C
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This
section does not include documents cited in other sections of this specification or recommend ed for additional
information or as examples. While every effort has been made to ensure the completeness of this list, document
users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of
this specification, whether or not they are listed.
2.2 Government documents.
2.2.1 Specifications and Standards. The following specifications and standards form a part of this
specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those
cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONS
MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard for Microelectronics.
MIL-STD-1835 - Interface Standard Electronic Component Case Outline
(Copies of these documents ar e available online at http://assist.daps.dla.mil/quicksearch/ or
http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Bu ilding 4D,
Philadelphia, PA 19111-5094.)
____
1/ Heat sinking is recommended to reduce th e junction temperature.
2/ Must withstand the added PD due to short circuit test (e.g. IOS).
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in
screening cond itions per method 5004 of MIL-STD-883.
MIL-M-38510/207E
3
2.3 Order of precedence. In the event of a conflict between the text of this specification and the references
cited herein, the text of this document takes precedence. Nothing i n this do cument, however, supersedes
applicable la ws and regulations unless a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Qualification. Microcircuits furnished under this spec ification shall be products that are manufactur ed by
a manufacturer authorized b y the qualifying activity for listing on the applica ble qualified manufacturers list before
contract award (see 4.3 and 6.3).
3.2 Item requirements. The individual item requirements shall be in accordanc e with MIL-PRF-38535 and
as specified herein or as modi fied in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.3 Design, construction, and physical dime nsions. The design, construction, and physi c al dimensions shall
be as specified in MIL-PRF-38 535 and herein.
3.3.1 Terminal connections. The terminal connections shall be as specified on figure 1.
3.3.2 Truth tables.
3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involvi ng no altered
item drawing shall be as specified on figure 2. When required in groups A, B, or C inspection (see 4.4), the
devices shall be programmed by the manufacturer prior to test in a checkerboar d pattern (a minimum of 50
percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25
percent of the total number of bits programmed.
3.3.2.2 Programmed devices. T he truth table for programmed devices shall be as specified by the altered
item drawing.
3.3.3 Functional bloc k diagram. The functional block diagram shall be as specified on figure 3.
3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3.
3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see
6.6).
3.5 Electrical performance characteristics . Unless otherwise specified, the electrical performance
characteristics are as specified in table I, and apply over the full recommended case operating temperature
range.
3.6 Electrical test requirements. The electrical test requirements for each device class shall be the
subgroups specified in table II. The electrical tests for each subgroup are described in table III.
3.7 Marking. Marking shall be in accorda nce with MIL-PRF-38535.
3.8 Processing options. Since the PROM is an unpr ogrammed device capable of being pro grammed by
either the manufacturer or the user to result in a wide variety of PROM configurations, two processing options are
provided for selection in the contract, using an altered item drawing.
3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verifie d throu gh group A testing as
defined in 3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after
programming to verify the specific program configuration.
3.8.2 Manufacture-programmed PROM delivered to the user. All testing requirements and quality assurance
provisions herein, including th e requirements of the altered item drawing, shall be satisfied by the manufacturer
prior to delivery.
3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group
number 14 (see Appendix A MIL-PRF-3853 5.)
MIL-M-38510/207E
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TABLE I. Electrical performance characteristics.
Limits
Test Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless other wise specified
Device
type Min Max Units
High-level output voltage VOH VCC = 4.5 V, IOH = -2 mA,
VIL = 0.8 V, VIH = 2.0 V 02, 04 2.4 V
Low-level output voltage VOL VCC = 4.5 V, IOL = 16 mA,
VIL = 0.8 V, VIH = 2.0 V 01, 02,
03, 04 0.5 V
Input clamp voltage VIC VCC = 4.5 V, IIN= -10 mA,
TC = +25ºC 01, 02,
03, 04 -1.5 V
Maximum collector cut-off
current ICEX1 V
CC = 5.5 V, VOH = 5.2 V 01, 03 100 μA
High impedance (off-state)
output high current IOHZ V
CC = 5.5 V, VOH = 5.2 V 02, 04 40 μA
High impedance (off-state)
output low current IOLZ V
CC = 5.5 V, VOL = 0.5 V 02, 04 -40 μA
High level input current IIH1 V
CC = 5.5 V, VIN = 5.5 V 01, 02,
03, 04
50 μA
IIH2 VCC = 5.5 V, VIN = 4.5 V ,
special programming pin
100
Low level input current IIL V
CC = 5.5 V, VIN = 0.5 V 01, 02,
03, 04 -1.0 -250 μA
Short circuit output current IOS VCC = 5.5 V, 2/
VO = 0.0 V 02, 04 -10 -100 mA
Supply current ICC VCC = 5.5 V, VIN = 0 V,
outputs = open 01, 02,
03, 04 130 mA
tPHL1 01, 02 80 ns
Propagation delay time, high to
low level logic, address to
output
VCC = 4.5 V and 5.5 V,
CL = 30 pF, see figure 4 03, 04 35
tPLH1 01, 02 80 ns
Propagation delay time, low to
high level logic, address to
output
VCC = 4.5 V and 5.5 V,
CL = 30 pF, see figure 4 03, 04 35
Propagation delay time, high to
low level logic, enable to output tPHL2 VCC = 4.5 V and 5.5 V,
CL = 30 pF, see figure 4 01, 02 50 ns
03, 04 25
Propagation delay time, low to
high level logic, enable to
output tPLH2 VCC = 4.5 V and 5.5 V,
CL = 30 pF, see figure 4 01, 02 50 ns
03, 04 25
1/ Complete terminal conditions shall be specified in table III.
2/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test.
MIL-M-38510/207E
5
Device types 01, 02, 03, and 04
Case outlines E and F
Terminal number Terminal symbol
1 O1
2 O2
3 O3
4 O4
5 O5
6 O6
7 O7
8 GND
9 O8
10 A0
11 A1
12 A2
13 A3
14 A4
15 CE
16 VCC
FIGURE 1. Terminal connections.
MIL-M-38510/207E
6
Word Address
number CE A4 A
3 A
2 A
1 A
0
NA L X X X X X
NA H X X X X X
Word DATA
number CE O1 O
2 O
3 O
4 O
5 O
6 O
7 O
8
NA L 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/
NA H OC OC OC OC OC OC OC OC
NOTES:
1. NA = Not applicable.
2. X = Input may be high level, low level or open circuit.
3. OC = Open circuit (high resistance output).
4. Program readout can only be accomplished with enable input at low level.
5. The outputs for an unprogr ammed device shall be high for circuits A and B;
and shall be low for circuits C, G, and H.
FIGURE 2. Truth table (unprogrammed).
MIL-M-38510/207E
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FIGURE 3. Functional block diagrams.
MIL-M-38510/207E
8
NOTE: This circuit is also used as circuit H.
FIGURE 3. Functional block diagrams – Continued.
MIL-M-38510/207E
9
FIGURE 3. Functional block diagrams – Continued.
MIL-M-38510/207E
10
NOTES:
1. Test table for devices programmed in accordance with an altered item drawing may be replaced b y the
equivalent tests which apply to the specific program configuration for the resulting read-onl y memor y.
2. CL = 30 pF minimum, including jig and probe capacitance; R1 = 330 Ω ±25% and R2 = 680 Ω ±20 %.
3. Outputs may be under load simultaneously.
FIGURE 4. Switching time test circuit.
MIL-M-38510/207E
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NOTE: All other waveform characteristics shall be as spec ified in table IVA.
FIGURE 5A. Typical programming vo ltage waveforms during programming for circuit A.
MIL-M-38510/207E
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NOTES:
1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check respectively.
2. All other waveform characteristi cs shall be as specified in table IVB.
FIGURE 5B. Typical programming vo ltage waveforms during programming for circuit B.
MIL-M-38510/207E
13
NOTE: All other waveform characteristics shall be as specified in tables IVC.
FIGURE 5C. Typical programming voltage waveforms during programming for circuit C.
MIL-M-38510/207E
14
FIGURE 5D. Typical programming voltage waveforms during programming for circuit G.
MIL-M-38510/207E
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NOTES:
1. All other waveform characteristics shall b e a s specified in tables IVH.
2. Programming verification at both high and low VCC margins is optional. For convenience, verificati on
can also be executed at the operating VCC limits specified in the dc characteristics.
FIGURE 5E. Typical programming vo ltage waveforms during programming for circuit H.
MIL-M-38510/207E
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4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-
38535 or as modified in the d evice ma nufacturer's Quality Management (QM) plan. The modification in the QM
plan shall not affect the form, fit, or function as described her ein.
4.2 Screening. Screening shall b e in accordance with MIL-PRF-38535 and shall be conducted on all devices
prior to qualification and quality conformance inspection. The following additional criteria shall apply:
a. The burn-in test duration, test condition, and test temperature, or approved altern atives shall be as
specified in the device manufacturer' s QM plan in accordance with MIL-PRF-38535. The burn-in test
circuit shall be maintained under document control by the device manuf acturer's Technology Review
Board (TRB) in accordance with MIL-PRF-38535 and shall be made availab le to the acquiring or
preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power
dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-
883.
b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical
parameters test prior to burn-in is optional at the discretion of the manufacturer.
c. Additional screening for space level product shall be as specified in MIL-PRF - 38535, appendix B.
d. Class B devices processed to an altered item drawing may b e programmed either before or after
burn-in at the manufacturer’s discretion. T he required electrical testing shall include, as a
minimum, the final electrical tests for programmed devices as specified in table II herein.
Class S devices processed by the manufactu rer to an altered item drawing shall be programmed
prior to burn-in.
4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535.
Qualification data for subgroups 7 throug h 11 shall be by attributes only.
4.3.1 Qualification extension. When authorized by the qualifying activity, for qualification inspection, if a
manufacturer qualifies faster device type which is manufactured identically to slower device types on this
specification, then the slower device types may be qualified by conductin g only group A electrical tests and
any electrical specified as additional group C subgroups and submitting data in accordance with MIL-PRF-
38535 (for example, groups B, C, and D tests are not required).
4.4 Technology Conformance inspection (TCI). Technology conformance inspection sha ll be in accordance
with MIL-PRF-38535 and as specifi ed herein for groups A, B, C, and D inspections (see 4.4.1 through 4 . 4.4).
4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as
follows:
a. Electrical test requirements shall be as specified in table II herein.
b. Subgroups 4, 5, and 6 shall be omitted.
c. For unprogrammed devices, a sample shall be selected to satisfy programmability requirem ents prior
to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to programming (see
3.3.2.1). If more than 2 devices fail to program, the lot shall be rejected. At the manufacturer’s
option, the sample may be increase d to 24 total devices with no more than 4 total device failures
allowed.
d. For unprogrammed devices, 10 devices from the programmability sample shall be su bjected to the
requirements of group A, subgroups 9, 10, and 11. If more than t wo total devices fail in all three
subgroups, the lot shall be rejected. At the manufacturer’s option, the sample may be increased to 20
total devices with no more than 4 total device failures allowable.
MIL-M-38510/207E
17
TABLE II. Electrical test requirements.
MIL-PRF-38535 Subgroups (see table III)
1/, 2/, 3/
test requirements Class S
devices Class B
devices
Interim electrical parameters 1 1
Final electrical test parameters
for unprogrammed devices 1*, 2, 3, 7*,
8 1*, 2, 3,
7*, 8
Final electrical test parameters
for programmed devices 1*, 2, 3, 7*
8, 9, 10, 11 1*, 2, 3, 7*,
8, 9,
Group A test requirements 1, 2, 3, 7, 8,
9, 10, 11 1, 2, 3, 7, 8
9, 10, 11
Group B end-point electrical parameters
when using the method 5005 QCI option 1, 2, 3, 7, 8,
9, 10, 11 N/A
Group C end-point electrical
parameters 1, 2, 3, 7, 8,
9, 10, 11 1, 2, 3, 7, 8
Group D test requirements 1, 2, 3, 7, 8 1, 2, 3, 7, 8
1
/ * indicates PDA applies to subgroups 1 and 7 (see 4.2c).
2
/ Any or all subgroups may be combined when using high-spee d testers.
3
/ Subgroups 7 and 8 shall consist of verifying the pattern specified.
4.4.2 Group B inspection. Group B inspection shall be in accordance with table II MIL-PRF-38535.
4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as
follows:
a. End-point electrical parameters shall be as specified in tabl e II herein.
b. The steady-state life test duration, test condition, and test temperatur e, or approved alternatives shall
be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-
in test circuit shall be maintained under document control by the device manufacturer's Technology
Review Board (TRB) in accordance with MIL-PRF-38535 and sha ll be made available to the acquiring
or preparing activity upon requ est. The test circuit shall specify the inputs, outputs, biases, and
power dissipation, as applicable, in accordance with the inte nt specified in test method 1005 of MIL-
STD-883.
c. For qualification inspection, at least 50 percent of the sample selected for testing in subgroup 1 shall
be programmed (see 3.3.2). For quality conformance inspection, the programmability sample (see
4.4.1c) shall be included in the life tests.
4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535. End-
point electrical parameters shall be as specified in table II herein.
TABLE III. Group A inspection for device types 01 and 03.
Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage;
inputs not designated are ≥ 2.0 V, low ≤ 0.8 V).
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Test limits
Subgroup Symbol
MIL-
STD-
883
method Test
no. O1 O
2 O
3 O
4 O
5 O
6 O
7 GND O8 A
0 A
1 A
2 A
3 A
4 CE VCC
Measured
terminal Min Max Unit
VIC 1
2
3
4
5
6
GND
“
“
“
“
“
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
“
“
“
“
“
A0
A1
A2
A3
A4
CE
-1.5
“
“
“
“
“
V
“
“
“
“
“
VOL 3007
“
“
“
“
“
“
“
7
8
9
10
11
12
13
14
16mA
16mA
16mA
16mA
16mA
16mA
16mA
“
“
“
“
“
“
“
“
16mA
1/ 2/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 2/ 3/
4/
“
“
“
“
“
“
0.5V
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
0.5
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
IIL 3009
“
“
“
“
“
15
16
17
18
19
20
“
“
“
“
“
“
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
“
“
“
“
“
A0
A1
A2
A3
A4
CE
-1.0
“
“
“
“
“
-250
“
“
“
“
“
μA
“
“
“
“
“
IIH1 3010
“
“
“
“
21
22
23
24
25
“
“
“
“
“
5.5V
5.5V
5.5V
5.5V
5.5V
“
“
“
“
“
A0
A1
A2
A3
A4
50
“
“
“
“
“
“
“
“
“
IIH2 “ 26 “ 4.5V
5/ “ CE 100 “
ICEX “
“
“
“
“
“
“
“
27
28
29
30
31
32
33
34
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
“
“
“
“
“
“
“
“
5.2V
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
1
TC =
25°C
ICC 3005 35 “ GND GND GND GND GND GND “ VCC 130 mA
2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC tests are omitted.
3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
See footnotes at end of table.
18
MIL-M-38510/207E
TABLE III. Group A inspection for device types 01 and 03 – Continued.
Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage;
inputs not designated are ≥ 2.0 V, low ≤ 0.8 V, or open).
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Test limits
Subgroup Symbol
MIL-
STD-
883
method Test
no. O1 O
2 O
3 O
4 O
5 O
6 O
7 GND O8 A
0 A
1 A
2 A
3 A
4 CE VCC
Measured
terminal Min Max Unit
7
TC =
25°C
Func-
tional
test
6/
“
“
“
“
“
“
“
36
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
GND
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
6/
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
6
/
“
“
“
“
“
“
“
8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and -55°C.
tPHL1 GALPAT
Fig. 4 37 7/ 7/ 7/ 7/ 7/ 7/ 7/ GND 7/ 8/ 8/ 8/ 8/ 8/ GND 8/ Outputs 9/ ns
tPLH1 GALPAT
Fig. 4 38 “ “ “ “ “ “ “ “ “ 8/ 8/ 8/ 8/ 8/ GND 8/ “ 9/ “
tPHL2 Sequen-
tial
Fig. 4
39 “ “ “ “ “ “ “ “ “ 10/ 10/ 10/ 10/ 10/ 10/ 10/ “ 9/ “
9
TC =
25°C
tPLH2 Sequen-
tial
Fig. 4
40 “ “ “ “ “ “ “ “ “ 10/ 10/ 10/ 10/ 10/ 10/ 10/ “ 9/ “
10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
19
MIL-M-38510/207E
TABLE III. Group A inspection for device types 02 and 04.
Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage;
inputs not designated are ≥ 2.0 V, low ≤ 0.8 V).
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Test limits
Subgroup Symbol
MIL-
STD-
883
method Test
no. O1 O
2 O
3 O
4 O
5 O
6 O
7 GND O8 A
0 A
1 A
2 A
3 A
4 CE VCC
Measured
terminal Min Max Unit
VIC 1
2
3
4
5
6
GND
“
“
“
“
“
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
“
“
“
“
“
A0
A1
A2
A3
A4
CE
-1.5
“
“
“
“
“
V
“
“
“
“
“
VOL 3007
“
“
“
“
“
“
“
7
8
9
10
11
12
13
14
16mA
16mA
16mA
16mA
16mA
16mA
16mA
“
“
“
“
“
“
“
“
16mA
1/ 2/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 3/
“
“
“
“
“
“
“
1/ 2/ 3/
4/
“
“
“
“
“
“
0.5V
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
0.5
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
VOH 3006
“
“
“
“
“
“
“
15
16
17
18
19
20
21
22
-2.0mA
-2.0mA
-2.0mA
-2.0mA
-2.0mA
-2.0mA
-2.0mA
“
“
“
“
“
“
“
“
-2.0mA
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
2.4
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
IIL 3009
“
“
“
“
“
23
24
25
26
27
28
“
“
“
“
“
“
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
“
“
“
“
“
A0
A1
A2
A3
A4
CE
-1.0
“
“
“
“
“
-250
“
“
“
“
“
μA
“
“
“
“
“
IIH1 3010
“
“
“
“
29
30
31
32
33
“
“
“
“
“
5.5V
5.5V
5.5V
5.5V
5.5V
“
“
“
“
“
A0
A1
A2
A3
A4
50
“
“
“
“
“
“
“
“
“
IIH2 “ 34 “ 4.5V
4/ “ CE 100 “
1
TC =
25°C
IOHZ 35
36
37
38
39
40
41
42
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
“
“
“
“
“
“
“
“
5.2V
5.5V
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
40
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
See footnotes at end of table.
20
MIL-M-38510/207E
TABLE III. Group A inspection for devices type 02 and 04 – Continued.
Terminal conditions (outputs not designated are open or resistive coupled to GND or voltage;
inputs not designated are ≥ 2.0 V, low ≤ 0.8 V).
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Test limits
Subgroup Symbol
MIL-
STD-
883
method Test
no. O1 O2 O3 O
4 O
5 O
6 O
7 GND O8 A
0 A
1 A
2 A
3 A
4 CE VCC
Measured
terminal Min Max Unit
IOLZ 43
44
45
46
47
48
49
50
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
GND
“
“
“
“
“
“
“
0.5V
5.5V 5.5V
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
-40
“
“
“
“
“
“
“
μA
“
“
“
“
“
“
“
ICC 3005 51 “ GND GND GND GND GND GND “ VCC 130 mA
1
TC =
25°C
IOS 3011
“
“
“
“
“
“
“
52
53
54
55
56
57
58
59
GND
GND
GND
GND
GND
GND
GND
“
“
“
“
“
“
“
“
GND
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
1/ 11/
12/ 13/
“
“
“
“
“
“
0.5V
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
O1
O2
O3
O4
O5
O6
O7
O8
-10
“
“
“
“
“
“
“
-100
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC tests are omitted.
3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC =
25°C
Func-
tional
tests
6/ 60 6/ 6/ 6/ 6/ 6/ 6/ 6/ GND 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ Outputs 6/
8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and TC = -55°C.
tPHL1 GALPAT
Fig. 4 61 7/ 7/ 7/ 7/ 7/ 7/ 7/ GND 7/ 8/ 8/ 8/ 8/ 8/ GND 8/ Outputs 9/ ns
tPLH1 GALPAT
Fig. 4 62 “ “ “ “ “ “ “ “ “ 8/ 8/ 8/ 8/ 8/ GND 8/ “ 9/ “
tPHL2 Sequen-
tial
Fig. 4
63 “ “ “ “ “ “ “ “ “ 10/ 10/ 10/ 10/ 10/ 10/ 10/ “ 9/ “
9
TC =
25°C
tPLH2 Sequen-
tial
Fig. 4
64 “ “ “ “ “ “ “ “ “ 10/ 10/ 10/ 10/ 10/ 10/ 10/ “ 9/ “
10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
21
MIL-M-38510/207E
MIL-M-38510/207E
22
TABLE III. Group A inspection – Continued.
1/ For programmed devices, select an appropriate address to acquire the desired output state, VIL = 0.8 V,
V
IH = 2.0 V.
2/ For unprogrammed devices, apply 11.0 V on pins 10 ( A0 ) and 14 ( A4 ) for circuit A devices.
3/ For unprogrammed 02 devices ( VOL test ), apply 0 V on pins 10 ( A0 ) through 14 ( A4 ) for circuit G.
4/ For unprogrammed devices, apply 12.0 V on pin 14 ( A4 ) for circuit B devices.
5/ This test may, at the manufacturer’s option, be performed with VIH = 5.5 V (pin 15) and test limit of
50 μA maximum.
6/ The functional tests shall verify that no fuses are blown for unprogrammed devices or that the truth table
specified in the altered item drawing exists for programmed devices (see table II and 3.3.2.2).
All bits shall be tested. Terminal conditions shall be as follows:
a. Inputs: H = 3.0 V, L = 0.0 V.
b. Outputs: Output voltage shall be: H ≥ 1.0 V and L < 1.0 V.
c. The functional tests shall be performed with VCC = 4.5 V and VCC = 5.5 V.
7/ The outputs are loaded per figure 4.
8/ GALPAT (PROGRAMMED PROM).
This program will test all bits in the array, the addressing and interaction between bits for ac performance
t
PHL1 and tPLH1 . Each bit in the pattern is fixed by being programmed with a “H” and “L”.
Description:
Step 1. Word 0 is read.
Step 2. Word 1 is read.
Step 3. Word 0 is read
Step 4. Word 2 is read.
Step 5. Word 0 is read.
Step 6. The reading procedure continues back and forth between word 0 and the n ext higher numbered word
until word 255 is reached, then increments to the next word and reads back and forth as in step 1
through step 6 and shall include all words.
Step 7. Pass execution time = ( n2 + n ) x cycle time. N = 256.
Step 8. The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V.
9/
Device tPHL1 tPLH1 tPHL2 tPLH2
01, 02 80 ns 80 ns 50 ns 50 ns
03, 04 35 ns 35 ns 25 ns 25 ns
MIL-M-38510/207E
23
TABLE III. Group A inspection – Continued.
10/ SEQUENTIAL (PROGRAMMED PROM).
This program will test all bits in the array for tPHL2 and tPLH2.
Description:
Step 1. Each word in the pattern is tested from the enable lines to the output lines for recovery.
Step 2. Word 0 is addressed. Enable line is pulled high to low and low to high. tPHL2 and tPLH2 are read.
Step 3. Word 1 is addressed. Same enable sequence as abov e.
Step 4. The reading procedure continues unti l word 255 is reached.
Step 5. Pass execution time = 256 x cycle time.
Step 6. The sequential tests shall be performed with VCC = 4.5 V and 5.5 V.
11/ For unprogrammed 01, 02 devices (with date codes before 8601), apply 1 0.0 V to pin 10 ( A0 ), apply 0.5 V to
pin 11 ( A1 ), and other 5.0 V on al l other addresses for circuit C.
12/ For unprogrammed 02 devices ( VOH test ), with date codes before 8713, apply 0 V to pins 10 ( A0 ) through
13 ( A3 ), and 11.5 V to pin 14 ( A4 ), with date codes of 8713 or later apply 3.0 V to pins 10 ( A0 ) through
13 ( A3 ), and 10.5 V to pin 14 ( A4 ) for circuit G.
13/ For unprogrammed dev ices 01, 02 (with date codes of 8601 or later), 03 and 04, apply 10.0 V to pin 10 ( A0 ),
0.5 V to pins 12, 13, 14, ( A2, A3, A4 ) and 5.0 V to all other addresses for circuit C.
MIL-M-38510/207E
24
4.5 Methods of inspectio n. Methods of inspe c tion shall be specified and as follows:
4.5.1 Voltage and current. All voltages give n are referenced to the microcircuit ground terminal. Currents given
are conventional and positive when flowing into the referenc ed terminal.
4.6 Programming procedure identification. The programming procedure to be utilize d shall be identified by the
manufacturer’s circuit designator. T he circuit designator is cross referenced in paragraph 6.6 herein with the
manufacturer’s symbol or CAGE number.
4.7 Programming procedure for circuit A. The programming characteristics in table IVA and the following
procedures shall be used for programmin g the device.
a. Con nect the device in the electrical configuration for programming. The waveforms on figure 5A and the
programming characteristics in table IVA shall apply to these procedures.
b. Address the PROM with the binary address of the word to be programmed. Address inputs are TTL
compatible. An open circuit shall not be us ed to address the PROM.
c. Apply VPL voltage to VCC.
d. Bring the CE X inputs high and the CE X inputs low to disable the device. The chip enables are TTL
compatible. An open circuit shall not be used to disable the device.
e. Disab le the programming circuitry by appl ying a voltage of VOPD to the outputs of the PROM.
f. Raise VCC to VPH with rise time less than or equal to tTLH.
g. After a delay equal to or great er than tD1 ap ply only one pulse with amplitude of VOPE and duration of tp to
the output selected for programming. Note that the PROM is supplied with fuses intact, which generates an
output high. Programming a fuse will cause the output to go low.
h. Lower VCC to VPL following a delay to tD2 from programming enable puls e applied to an output.
i. Enable the PROM for verification by applying VIL to CEX and VIH to CE X .
j. Apply VPHV to VCC and verify bit is programmed.
k. Repeat steps a through j for all other bits to be programmed in the PROM.
l. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming
reject.
MIL-M-38510/207E
25
TABLE IVA. Programming characteristics for circuit A.
Limits 1/ Parameter Symbol
Min Recommended Max
Unit
Address input voltage 2/ VIH 2.4 5.0 5.0 V
VIL 0.0 0.4 0.5 “
Programming VPH 3/ 10.75 11.0 11.25 V
Voltage to VCC low VPL 0.0 0.0 1.5 V
Program verify VPHV --- 5.5 --- V
Verify voltage VR 4/ 4.5 5.0 5.5 V
Programming input low
current at VPH IILP --- -300 -600
μA
Programmed voltage
(VCC) transition time tTLH 1 5 10
μs
tTHL 1 5 10 “
Programming delay tD1 10 10 20
μs
tD2 1 5 5 “
Programming pulse width tP 5/ 90 100 110
μs
Programming duty cycle PDC 6/ --- 30 60 %
Output voltage
Enable VOPE 7/ 10.5 10.5 11.0 V
Output voltage
Disable VOPD 7/ 0.0 5.0 5.5 V
During the programming the chip must be disabled for pro per operation.
1/ TC = +25°C.
2/ No inputs should be left open for VIH.
3/ VPH source must be capable of supplyin g one ampere.
4/ It is recommended that post programming dual verification be made at VR minimum and VR maximum.
5/ Note step j in programming procedure.
6/ Programming duty cycle applies to DIPs only.
7/ VOPE source must be capable of supplying 10 mA minimum.
MIL-M-38510/207E
26
4.8 Programming procedure for circuit B. The programming characteristics in table IVB and the following
procedures shall be used for programmin g the devices:
a. Connect the device in the electrical configuration for programm ing. The waveforms on figure 5B and
the programming characteristics of tabl e IVB shall apply to these procedur es.
b. Raise VCC to 5.5 volts.
c. Address the PROM with binary address of the selected word to be programmed.
Address inputs are TTL compatible.
d. Disable the chip by applying VIH to the CE input. CE input is TTL compatible.
e. Apply the VPP pulse to the CE pin. In order to insure that the output transistor is off before increasing
the voltage on the output pin, the program pin’s voltage pulse shall precede the outp ut pin’s programming
pulse by tD1 and leave after the output pin’s programming pulse by tD2 (see figure 5B).
f. Apply the VOUT pulse with duration of tP to the output selected for progra mming (see table IVB).
The outputs shall be programmed one outp ut at a time, since internal decoding circuitry is capable of
sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses
generating a high-level logic o utput. Progra mming a fuse will cause the output to go to a low-level logic
in the verify mode.
g. Other bits in the same word may be programmed sequentially applying VOUT pulses to each output to be
programmed.
h. Repeat 4.8b through 4.8g for all bits to be programmed.
i. Enable the chip by app lying VIL to the CE input and verify the program.
Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.0 V and
0.2 mA at VCC = 7.0 V at TC = 25°C.
j. For classes S and B devices, if any bit does not verify as programmed it shall be considered a
programming reject.
MIL-M-38510/207E
27
TABLE IVB. Programming characteristics for circuit B.
Limits 1/
Parameter Symbol Conditions
Min Recommended Max
Unit
Current into output during
programming before the fuse
has programmed IOUT1 VCC = 5.5 V, VOUT = 9.0 V 0.1 mA
VCC = 5.5 V, VOUT = 25 V 35
Current into output during
programming after the fuse
has programmed IOUT2 VCC = 5.5 V, VOUT = 20 V 3 mA
Rise time of program pulse
applied to the data out from
10% to 90% tTLH 50 60 70
μs
Chip enable (CE ) pin pulse
width tPP Chip disabled
VCC = 5.5 V 80 95 110
μs
Pulse width of programming
voltage tP Chip disabled
VCC = 5.5 V 1 40
μs
Fall time of the pulse applied
to the CE from 90% to 10% tTHL 50 1000 ns
Required time delay between
disabling memory output and
application of output
programming pulse tD1 Measured at 1.5 V levels 70 80 90 μs
Required time delay between
removal of programming
pulse and enabling memory
output tD2 Measured at 1.5 V levels 100 ns
VCC required during
programming VCCP 5.40 5.50 5.60 V
Output current required
during verification IOLV1 TC = 25°C, VCC = 4.20 V
chip enabled 11 12 13 mA
Output current required
during verification IOLV2 TC = 25°C, VCC = 6.0 V
chip enabled 0.19 0.2 0.21 mA
Maximum duty cycle during
automatic programming of
enable and out put pin DC TP / TC 25 %
Required programming
voltage on the output pin VOUT 20 20 26 V
Required current limit of the
power supply feeding the
output during programming IL VOUT = 25 V,
VCC = 5.5 0 V 150 mA
1/ TC = +25°C.
MIL-M-38510/207E
28
4.9 Programming procedure for circuit C. The programmi ng characteristics in table IVC and the following
procedures shall apply for programming the device:
a. Connect the device in the elec trical configuration for programming. The waveforms on figure 5C and the
programming characteristics in table IVC shall apply for programming to these pr ocedures.
b. Terminate all device outputs with a 10 kΩ resistor to VCC.
c. Address the PROM with the binary address of the selected word to be programme d. Raise VCC to VCCP.
d. After a tD delay (10 μs), apply only one VOUT pulse to the output to be programmed.
Program one output at a time.
e. After a tD delay (10 μs), pulse CE input to logic “0” for a duration of tP.
f. After a tD delay (10 μs), remove the VOUT pulse from the programmed outp ut. Note that the PROM is
supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a
high-level logic in the verify mode.
g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by
applying VOUT pulses to each output to be programmed allowing a delay of tD between pulses as shown
on figure 5C.
h. Repeat 4.9b through 4.9g for all other bits to be programmed.
i. To verify programming after tD (10 μs) delay, lo wer VCC to VCCH and ap ply a logic “0” level to both CE
input. The programmed output should remain in the “1” state. Again lower VCC and VCCL and verify that
the programmed output remains in the “1” state.
j. For class S and B devices, if any bit does not verify as programmed, it shall be considered a pro gramming
reject.
MIL-M-38510/207E
29
TABLE IVC. Programming characteristics for circuit C.
Limits 1/
Parameter Symbol Conditions Min Recommended Max
Unit
Programming voltage to
VCC VCCP 1/ ICCP = 375 ±75 mA;
transient or steady-state 9.5 10.0 10.5 V
Verification upper limit VCCH 5.3 5.5 5.7 V
Verification lower limit VCCL 4.3 4.5 4.7 V
Verify threshold VS 2/ 0.9 1.0 1.1 V
Programming supply
current ICCP V
CCP = +8.75 ±0.25 V 200 250 300 mA
Input voltage high level
“1” VIH 2.4 5.5 V
Input voltage low level
“0” VIL 0 0.4 0.8 V
Input current IIH V
IH = +5.5 V 50
μA
Input current IIL V
IL = +0.4 V -500
μA
Output programming
voltage VOUT 3/ IOUT = 65 ±3 mA,
transient or steady-state 15.0 15.5 16.0 V
Output programming
current IOUT V
OUT = +17 ±1 V 62 65 68 mA
Programming voltage
transition time tTLH 10 50
μs
CE programming pulse
width tP 300 400 500
μs
Pulse sequence delay tD 10
μs
Programming duty cycle tPR /
tPR + tPS 50 %
1/ Bypass VCC to GND with a 0.01 μF capacitor to reduce voltage spikes.
2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the
reference voltage applied to a comparator ci rcuit to verify a successful fusing attempt.
3/ Care should be taken to insure the 17 ±1 V output voltage is maintained during the e ntire fusing cycle.
The recommended supply is a constant current source clamped at the specified voltage limit.
MIL-M-38510/207E
30
4.10 Programming procedure for circuit G. The programming ch aracteristics on table IVG and the following
procedures shall be used for programming.
a. Connect the device in the elec trical configuration of programming. The waveforms on figure 5D and the
programming characteristics of table IVG shall ap ply to these procedures.
b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the
device by applying a high level to one or more active low chip enable inputs. NOTE: Address and enable
inputs must be driven with TTL logic levels during progr amming and verification.
c. Increase VCC from nominal to VCCP (10.5 ±0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/μs). Since
VCC is the source of the current required to program the fuse, as well as the ICC for the device at the
programming voltage, it must be capable of supplying 75 0 mA at 11.0 volts.
d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 ±0.5 V). Limit
the slew rate to IRR (1.0 to 10.0 V/μs). This voltage change may occur simultaneously with the VCC
increase to VCCP, but must precede it. It is critical that only one output at a time be programmed since the
internal circuits can only supply programming current to one bit at a time. Outputs not being programmed
must be left open or connected to a high impedance source of 20 kΩ minimum (remember that the outputs
of the device are disabled at this time).
e. Enable the device b y taking th e chip enable(s) to a low level. This is done with a pulse P WE for 10 μs.
The 10 μs duration refers to the time that the circuit (device) is enable d. No rmal input levels are used and
rise and fall times are not critical.
f. Verify that the bit has been programmed b y first removing the programming voltage from the output and
then reducing VCC to 5.0 V (±0.25 V). T he device must be enabled to sense the state of the outputs.
During verification, the loading of the output must be within specified IOL and IOH limits.
g. If the device is not to be tested for VOH over the entire oper ating range subsequent to programming, th e
verification of step f is to be performed at a VCC level of 4.0 volt ( ±0.2 V ). VOH, during the 4 volt
verification, must be at least 2.0 volts. The 4 volt VCC verification assures minimum VOH levels over the
entire operating range.
h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is
performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited
to a maximum of 25%. This is necessary to minimize device juncti on temperatures. After all selected bits
are programmed, the entire contents of the memory should be verified.
i. For class S and B devices, if any bit does no t verif y as programmed it shall be considered a programming
reject.
MIL-M-38510/207E
31
TABLE IVG. Programming characteristics for circuit G.
Limits 1/
Parameter Symbol Conditions Min Recommended Max
Unit
Required VCC for
programming VCCP
10.0 10.5 11.0 V
ICC during programming ICCP
VCC = 11 V 750 mA
Required output voltage
for programming VOP 10.0 10.5 11.0 V
Output current while
programming IOP
VOUT = 11 V 20 mA
Rate of voltage change
of VCC or output IRR 1.0 10.0
V/μs
Programming pulse
width (enabled) PWE 9 10 11
μs
Required VCC for
verification VCCV
3.8 4.0 4.2 V
Maximum duty cycle for
VCC at VCCP MDC 25 25 %
Address set-up time t1 100 ns
VCCP set-up time t2 2/ 5
μs
VCCP hold time t5 100 ns
VOP set-up time t3 100 ns
VOP hold time t4 100 ns
1/ TC = +25°C.
2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or faster than VOP.
MIL-M-38510/207E
32
4.11 Programming procedure for circuit H. The programming characteristics in table IVH and the following
procedures shall apply for programming the device:
a. Connect the device in the elec trical configuration for programming. The waveforms on figure 5E and the
programming characteristics in table IVH shall apply for programming to these pr ocedures.
b. Terminate all device outputs with a 10 kΩ resistor to VCC. The 10 kΩ is the pullup resistor for open
collector devices.
c. Address the PROM with the binary address of the selected word to be programme d. Raise VCC to VCCP.
d. After a tD delay (10 μs), apply VOPF output to be programmed. Program one o utput at a time.
Note leading edge rise time restrictions.
e. After a tD delay (10 μs), pulse CE input to logic “0” for a duration of tP.
f. After a tD delay (10 μs), remove the VOPF pulse from the programmed output. Note that the PROM is
supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to
a high-level logic in the verify mode.
g. Repeat 4.11d through 4.1 1f to program oth er bits at the same address.
h. To verify programming of all bits at the same address, after tD delay lower VCC to VCCVL and apply a
logic low level to the CE X input. All programmed outputs should remain in the same logic high state.
i. After tD delay, repeat steps 4.11c through 4.11h to program and verify all other addr ess locations.
j. After tD delay, raise VCC to VCCVH and verify all memory locations by applying a l ogic low level to
CE and cycling throug h all device addresses.
k. For class S and B devic es, if any bit does not verify as programmed, it shall be consider ed a programming
reject.
MIL-M-38510/207E
33
TABLE IVH. Programming characteristics for circuit H.
Limits
Parameter Symbol Conditions Min Recommended Max
Unit
Programming voltage
to VCC VCCP 1/ ICCP = 425 ±75 mA;
transient or steady-state 8.5 8.75 9.0 V
Verification upper limit VCCVH 5.3 5.5 5.7 V
Verification normal limit VCCVN 4.75 5.0 5.25 V
Verification lower limit VCCVL 4.3 4.5 4.7 V
Verify threshold VS 2/ 1.4 1.5 1.6 V
Programming supply
current ICCP V
CCP = +8.75 ±0.25 V 350 500 mA
Input voltage high level
“1” VIH 2.4 5.5 V
Input voltage low level
“0” VIL 0 0.8 V
Input current IIH V
IH = +5.5 V 50
μA
Input current IIL V
IL = +0.4 V -500
μA
Forced output voltage
(program) VOPF 3/ IOUT = 200 ±20 mA,
transient or steady-state 17 17.5 18.0 V
Forced output current
(program) IOPF V
OPF = +17 ±1 V 180 220 mA
Output pulse rise time tRZ 17 20 25
μs
CE programming pulse
width tP 10 10 25
μs
Pulse sequence delay tD 5 10
μs
Address program verify
cycle tPVA 1 ms
Memory program verify
time (continuous) tPVM 20 sec
Fusing attempts per link FL 1 cycle
1/ Bypass VCC to GND with a 0.01 μF capacitor to reduce voltage spikes.
2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the
reference voltage applied to a comparator circuit to verify a successful fusing attempt.
3/ The voltage should be maintained within s pecified limits during the entire f usin g cycle. For a transient current of
150 mA, limit voltage spikes to a maximum slew rate of 2 V/μs and 10 μs maximum recovery.
MIL-M-38510/207E
34
5. PACKAGING
5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the
contract or order (see 6.2). When packaging of materiel is to be performed b y DoD or in-house contractor personnel,
these personnel need to contact the responsible packagi ng activity to ascertain packaging requirements. Packaging
requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense
Agency, or within the military service's system command. Packaging data retrieval is available from the managing
Military Department's or Defe nse Agency's automated packaging files, CD -ROM products, or by contacting the
responsible packaging activity.
6. NOTES
(This section contains information of a g eneral or explanatory nature which may be helpful, but is not mandatory.)
6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing
equipment.
6.2 Acquisition requirements. Acquisition documents should specify the following:
a. Title, number, and date of the specification.
b. PIN and compliance i de ntifier, if applicable (see 1.2).
c. Requirements for delivery of one copy of the conformance inspection data pertin ent to the device
inspection lot to be supplied with eac h shipment by the device manufacturer, if applicable.
d. Requirements for certificate of compliance, if applicable.
e. Requirements for notificati on of change of product or process to contracting activity in addition to
notification to the qualifying activity, if applicable.
f. Requirements for failure analysis (inclu ding required test condition of method 5003 of MIL-STD-883),
corrective action, and reporting of results, if applicable.
g. Requirements for prod uct assurance options.
h. Requirements for special lead lengths, or lead forming, if applicable. Unless otherwise specified, these
requirements will not apply to direct purchase by or direct shipment to the Government.
i. Requirement for programming the device, including processing option.
j. Requirements for "JAN" marking.
k. Packaging Requirements (see 5.1)
6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which
are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not
such products have actually been so listed b y that date. The attention of the contractors is called to these
requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal
Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for
the products covered by this specification. Information pertaining to qual ification of products may be obtained from
DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990.
MIL-M-38510/207E
35
6.4 Superseding information. The requirements of MIL-M-38510 have been superseded to take advantage of the
available Qualified Manufactur er Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M-
38510 in this document have been replaced by appropriate referenc es to MIL-PRF - 38535. All technical requirements
now consist of this specification and MIL-PRF-385 35. The MIL-M-38510 specification sheet number a nd PIN have
been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined
in MIL-PRF-38535, MIL-HDBK-1331, and as follows:
GND ............................................ Electrical ground (common terminal).
I
IN ............................................... Current flowing into an input terminal.
V
IC .............................................. Input clamp voltage.
V
IN .............................................. Voltage level at an input terminal.
6.6 Logistic support. Lead materials and fini shes (see 3.4) are interchangeable. Unless otherwise specified,
microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material
and finish A (see 3.4). Longer length leads and lead forming should not affect the part number. It is intended that
spare devices for logistic support be acquired in the unprogrammed conditi on (see 3.8.1) and programmed by the
maintenance activit y, except where use q ua ntities for devices with a specific program or pattern justify stocking of
preprogrammed devices.
6.7 Substitutability. T he cross-reference information below is presented for the convenience of users.
Microcircuits covered by this specification will functio nally replace the listed generic-industry type. Generic-industry
microcircuit types may not have equivalent op erational performance characteristics across military temperature
ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation
to case size. The presence of this information should not be deemed as p ermitting su bstitution of generic-industry
types for MIL-M-38510 types or as a waiver of any of the provisio ns of MIL-PRF-38535.
Military
device type Generic-industry type Circuit
designator Fusible
links
01 1/ 7602 / Harris Semiconductor, CAGE 3437 1 A NiCr
01 1/ 5330 / Monol ithic Memories, CAGE 56364 B NiCr
02 DM54S288 / National Semiconductor, CAGE 27014 G TiW / W
02 1/ 7603 / Harris Semiconductor, CAGE 3437 1 A NiCr
02 1/ 5331 / Monol ithic Memories, CAGE 56364 B NiCr
01, 03 82S23A / Signetics Corporation, CAGE 18324 C NiCr
02, 04 82S123A / Signetics Corporation, CAGE 18324 C NiCr
01, 03 82S23A / Signetics Corporation, CAGE 18324 H 2/ NiCr
01, 03 82S23A/QP Semiconductor H 2/ ZVE
02, 04 82S123A / Sig netics Corporation, CAGE 18324 H 2/ NiCr
02, 04 82S123A/QP Semiconductor H 2/ ZVE
1/ This generic industry type is no longer manufactured.
2/ Updated circuit C to circuit H to reflect the current programming method.
Contact the manufacturer for the correct progr amming method being used.
MIL-M-38510/207E
36
6.8 Change from previous issue. Marginal n otations are used in this revision to identify changes with respect to the
previous issue.
Custodians: Preparing activity:
Army - CR DLA - CC
Navy - EC
Air Force - 11
DLA - CC
Review activities: (Project 5962-2007-008)
Army – SM, MI
Navy - AS, CG, MC, SH TD
Air Force – 03, 19, 99
NOTE: The activities listed above were inte rested in this docume nt as of the date of this document. Since
organization and responsi bilities can change, you should verify the currency of the information above using the
ASSIST Online database at http://assist.daps.dla.mil.
