AS8C803625A-7.5QCCN - Alliance Memory, Inc.

NOVEMBER 2010

256K X 36, 512K X 18

3.3V Synchronous ZBTTM SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

AS8C803625A

AS8C801825A

Features

 256K x 36, 512K x 18 memory configuration

 Supports high performance system speed –

100MHz (7.5ns Clock-To-Data Access)

 ZBTTM Feature – No dead cycles between write

and read cycles

 Internally synchronized output buffer enable

eliminates the need to control OE

 Single R/W (READ/WRITE) control pin

 4-word burst capability (Interleaved or linear)

 Individual byte write (BW1 – BW4) control

(May tie active)

 Three chip enables for simple depth expansion

 3.3V power supply (±5%)

 3.3V (±5%) I/O Supply (VDDQ)

 Power down controlled by ZZ input

 Packaged in a JEDEC standard 100-pin plastic

thin quad flatpack (TQFP)

in and control signal registers. The outputs are

flow-through (no output data register). Output

enable is the only asynchronous signal and can be

used to disable the outputs at any given time.

A clock Enable (CEN) pin allows operation of

the 803625A/801825A to be suspended as long

as necessary. All synchronous inputs are ignored

when CEN is high and the internal device

registers will hold their previous values.

There are three chip enable pins (CE1, CE2,

CE2) that allow the user to deselect the device

when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory

operation can be initiated. However, any pending

data transfers (reads or writes) will be

completed. The data bus will tri-state one cycle

after the chip is deselected or a write is initiated.

The 803625A/801825A have an on-chip burst

counter. In the burst mode, the 803625A /

801825A can provide four cycles of data for a

single address presented to the SRAM. The order

of the burst sequence is defined by the LBO input

pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is

used to load a new external address

(ADV/LD=LOW) or increment the internal burst

counter (ADV/LD=HIGH).

The 803625A/801825A SRAMs utilize

Alliance’s latest high-performance CMOS process

and are packaged in a JEDEC Standard 14mm x

20mm 100-pin plastic thin quad flatpack (TQFP).

Description

The 803625A/801825A are 3.3V high-speed

9,437,184-bit (9 Megabit) synchronous SRAMs

organized as 256K x 36/512K x 18. They are

designed to eliminate dead bus cycles when

turning the bus around between reads and writes,

or writes and reads. Thus they have been given

the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the

SRAM during one clock cycle, and on the next

clock cycle the associated data cycle occurs, be it

read or write.

The 803625A/801825A contain address, data-

Pin Description Summary

A0 – A18

Address Inputs

Input

Synchronous

CE1, CE2, CE2

Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

R/W

Read/Write Signal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

BW1, BW2, BW3, BW4

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/LD

Advance Burst Address/Load New Address

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

Static

Sleep Mode

Input

Asynchronous

I/O0 – I/O31, I/OP1 – I/OP4

Data Input / Output

I/O

Synchronous

VDD, VDDQ

Core Power, I/O Power

Supply

Static

VSS

Ground

Supply

Static

5298 tbl 01

AS8C803625A, AS8C801825A, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS