October 1990 Edition 1.0 DATA SHEET MB86260 D/A CONVERTER (4CH, 4BIT) WITH LOOK UP TABLE CMOS DIGITAL TO ANALOG CONVERTER (4CH 4-BIT) WITH LOOK UP TABLE The MB86260 contains four 4-bit D/A converters, which can handle either monochrome or color, and a 256 word Look Up Table (LUT). It can simultaneously display 256 colors out of a total color palette of 4096 colors. It is also equipped with a text data overlay function, and operates with a 50 MHz cycle time. * 50 MHz, 4-bit precision D/A converters * Contains RGB color D/A converters and monochrome D/A converter * Simultaneously display of 256 colors out of a total palette of 4096 colors * Text overlay display PLASTIC PACKAGE (DIP-42P-MO1) * Text brightness control * Asynchronous writing to and reading from LUT * Flicker prevention function using dual port RAM * Current driven analog output with 75 Ohm external termination (Each terminal 37.5 Ohms) * Fine control of analog output level ABSOLUTE MAXIMUM RATINGS (see Note) Rating Symbol Pin Name Value Unit Power supply voltage VDD VDD, VDA -0.3 to 6.0 V ITD VDA -10 to 200 mA ITP VDD -10 to 50 mA ITS VSA -200 to 10 mA ITO OUTY, OUTR, OUTG, OUTB -10 to 35 mA ITA PEDA, FULA, VREF -10 to 10 mA Pin voltage VT Other than power supply pin. -0.3 to VDD +0.3 V Storage temperature Vstg - -40 to 125 C TA - 0 to 70 C Pin current Operating temperature Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright 1990 by FUJITSU LIMITED PLASTIC PACKAGE (FTP-64P-MO1) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. MB86260 PIN ASSIGNMENT 2 (TOP VIEW) (TOP VIEW) (DIP-42P-M01) (FPT-64P-M01) MB86260 INPUT/OUTPUT SIGNALS AND THEIR FUNCTIONS Pin No. Category Clock DIP QFP Pin Name I/O Explanation of Functions 37 3 PCLK I This is the pixel clock. Text data and V-RAM data are loaded in accordance with this clock. 35 62 XRD I This is the LUT read clock. It loads the select data for either R, G, or B at the falling edge. (The read address is set by the XWD signal.) 36 63 XWD I This is the LUT write clock. It loads the address, R, G, and B select data at the falling edge. It also writes the address, R, G, and B data at the rising edge. 27 to 34 49, 53, to 55, 57, 59 to 61 A7 to A0 I V-RAM data (LUT address) signals, load using the PCLK signal. 17 to 20 22 to 25 36 to 38, 40, 43, 45 to 47 D7 to D0 I/O Interface bus to the CPU. Loads address and R G B select data with D6 and D7. Performs input and output of R G B data with D0 to D3, and LUT address data input with D0 to D7. 41 8 LMSK I This signal masks the LUT output. LUT data is output when LMSK = 1. When LMSK = 0, mask mode is turned on, and the LUT output is set to blanking level. 2 13 TXOL I This signal is for overlaying text data. When TXOL = 0 the LUT output signal is output, and when TXOL = 1 the text data output signal is output. 3 14 TXMS I The text data display mode can be selected with the TXMS signal. The white balance mode is selected when TXMS = 1, and the enhancement mode is selected when TXMS = 0. D t Data The intensity of the white in white balance mode, and the enhanced color in enhancement changing mode, are selected using these two bits. 39 5 TXW1 TXW2 TXW1 I Control 42 9 TXW2 Intensity (Weight) 0 0 0 0 1 1 1 0 2 1 1 3 4 15 TXB I This is the data signal for BLUE text in the color signal. 1 11 TXR I This is the data signal for RED text in the color signal. 40 6 TXG I This is the data signal for GREEN text in the color signal. 5 16 TXI I This is the brightness signal for text data. 38 4 DST I This signal controls the display period. When DST = display is not performed (the output is set to blanking level); display is possible when DST = 1. 10 24 FULA O The pedestal level current is regulated with external resistance connected between this pin and VSA. 12 27 PEDA O The synchronous level current is regulated with external resistance connected between this pin and VSA. 11 25 VREF I This is the reference voltage input pin for bias setting. 3 MB86260 INPUT/OUTPUT SIGNALS AND THEIR FUNCTIONS (continued) Pin No. Category DIP QFP Pin Name I/O Explanation of Functions 6 23 OUTB O Analog output signal for BLUE signal. 16 33 OUTR O Analog output signal for RED signal. 13 28 OUTG O Analog output signal for GREEN signal. Output Power Supply S l Others 4 6 19 OUTY O Analog output signal for monochrome. 8, 14 22, 29 VSA - Ground pin for analog section. 7, 15 21, 30 VDA - Power supply for analog section. 26 48 VDD - Power supply for digital section. 21 41 VSS - Ground pin for digital section. - 1, 2, 7, 10, 12, 17, 18, 20, 26, 31, 32, 34, 35, 39, 42, 44, 50, 51, 52, 56, 58, 64 NC - No connection. Must be kept open. MB86260 BLOCK DIAGRAM RECOMMENDED OPERATING CONDITIONS Parameter Symbol Pin name Minimum Typical Maximum Unit Power supply voltage VDD VDD, VDA 4.75 5.0 5.25 V Reference voltage VREF VREF 2.0 2.5 3.0 V Load resistance RL OUTY, OUTR OUTG, OUTB - 37.5 - Resistance for setting current RR FULA, PEDA - 5.22 - k Output voltage VOC OUTY, OUTR OUTG, OUTB 0 - 0.8 V TA - - 25 - C Operating temperature Note: RL: Composite load resistance at each pin. 5 MB86260 ELECTRICAL CHARACTERISTICS VREF = 2.5 V, RPR = RFR = 5.22 K RBL = RRL = RGL = RYL = 75 Parameter Symbol Pin name Minimum Typical Maximum Unit DAC full scale current IF OUTY, OUTR OUTG, OUTB 18 20 22 mA Offset current for pedestal level IP OUTY, OUTR OUTG, OUTB 1.2 1.33 1.5 mA DAC non-linearity LE OUTY, OUTR OUTG, OUTB -3 - 3 %FSR DAC full scale current error between channels IF Definition: Maximum (IF) - Minimum (IF) - - 6 %FSR DAC pedestal current error between channels IP Definition: Maximum (IP) - Minimum (IP) - - 6 %FSR Bias setting pin current VB FULA, PEDA 2.4 - 2.6 V Power supply current IDA VDD, VDA - 120 160 mA Symbol Minimum Typical Maximum Unit PCLK low clock width tLCW 10.0 - - ns PLCK high clock width tHCW 10.0 - - ns Maximum operating frequency - - - 50 MHz LUT data set up time for PCLK tSTA 3.1 - - ns LUT data hold time for PCLK tHTA 11.2 - - ns Text data set up time for PCLK tSTD 3.1 - - ns Text data hold time for PCLK tHTD 11.2 - - ns XWD low clock width tWLCW 75.7 - - ns XWD high clock width tWHCW 32.7 - - ns Select data set up time tSDST 13.7 - - ns Select data hold time tSDHT 4.5 - - ns Address set up time tWAST 14.7 - - ns Address hold time tWAHT 3.7 - - ns Write data set up time tWDST 60.0 - - ns Write data hold time tWDHT 3.7 - - ns LUT data out delay tOD 32.7 - - ns LUT data hold time tOHD 4.5 - - ns Effective output time for PCLK tV 1.9 - - ns Output settling time for PCLK tS - - 22.4 ns Effective output time for PCLK tVP1 0 - - ns Output settling time for PCLK tSP1 - - 50.0 ns Effective output time for PCLK tVP2 0 - - ns OUtput settling time for PCLK tSP2 - - 22.4 ns Figure Figure 1 Parameter Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 *See timing charts on pages 6 and 7. 6 MB86260 TIMING CHARTS Figure 1. Clock input timing Figure 2. LUT data input timing Figure 3. Text data input timing Figure 4. LUT update/read timing 7 MB86260 Figure 5. Color signal output timing Figure 6. Blanking output timing 8 MB86260 EXPLANATION OF FUNCTIONS 1. INTERFACE WITH CPU An 8-bit data bus (D0 to D7), and two read/write signals (XRD/XWD) are used for the interface with the CPU. 1.1 Timing * Demarcations between the LUT buffer R, G, B and LUT addresses are input according to D7 to D0 at the falling edge of XRD/ XWD. * Data input or output is performed according to D7 to D0, at the rising edge of XRD/XWD. * In the LUT read, first the LUT address is read from D7 to D0 by XWD (the LUT address is selected from D7, D6 at the falling edge at this time). At the next XRD falling edge, the demarcations between R, G and B are loaded by D7, D6, and data is output. * To rewrite LUT, first the LUT address is read by XWD from D7 to D0 (the LUT address is selected from D7, D6 at the falling edge at this time). Then at the next XWD falling edge, the demarcations between R, G and B are loaded by D7, D6, and data is written. 1.2 LUT Buffer and Address An address is selected according to D7 or D6 values. D7 D6 Contents 0 0 LUT address 0 1 B LUT 1 0 R LUT 1 1 G LUT The procedure is as follows: 1.2.1 LUT update 1 XWD Select LUT address. (D7 = 0, D6 = 0) 2 XWD Input LUT address. 3 XWD Input R, G, B demarcations. 4 XWD Input data. 9 MB86260 1.2.2 LUT read 1 XWD Select LUT address. (D7 = 0, D6 = 0) 2 XWD Input LUT address. 3 XRD Input R, G, B demarcations. 4 Output data. (D4 to D7 clipped to low.) 5 XRD Data loaded externally. 2. LUT MASK MODE The LMSK signal masks the LOT output signal. LMSK = 1 : LUT data is output. = 0 : Sets to mask mode, LUT output is set to blanking level. LUT data input is synchronized with PCLK. The data is reflected to the analog output via the same number of pipeline steps as the A0 to A7 signals within the lC. 3. TEXT DATA OVERLAY FUNCTION The TXOL signal is provided for overlaying the LUT data with the text data. TXOL = 0 : Select LUT. = 1 : Select the text data signal of TXB, TXR, TXG, or TXl. The TXOL signal and the text data signal inputs are synchronized with PCLK. The data is reflected to the analog output via the same number of pipeline steps as the A0 to A7 signals within the IC. 3.1 Text Data Display Mode The text data display mode can be selected using the TXMS signal. TXMS = 1 : White balance mode = 0 : Enhancement mode The enhanced color in the enhancement change mode, and the intensity of the white in the white balance mode can be selected by using the TXW1 signal and the TXW2 signal. (The TXMS signal, TXW1 signal and TXW2 signal input cannot be synchronized with the PCLK signal, and so it is necessary to be careful.) 10 TXW2 TXW1 Intensity (Enhancement) 0 0 0 0 1 1 1 0 2 1 1 3 MB86260 EXPLANATION OF FUNCTIONS 3.2 White Balance Mode As shown in the clock diagram below, with the white-balance method, the output determinations according to the values of TXB, TXR and TXG, together with the TXI input signal, affect the text output without regard to other inputs. 3.3 Enhancement Change Mode As shown in the clock diagram below, with the enhancement change mode, the output determinations according to the values of TXB, TXR and TXG, together with the TXl input signal, affect the text output according to whether input is TXB, TXR or TXG input values. 11 MB86260 4. DISPLAY TIMING * Analog output and DST timing PCLK and the following signals are output in synchronized timing. A0 to 7, TXB, TXR, TXG, TXI TXOL, LMSK, DST OUTR, OUTG, OUTB, OUTY There are six pipeline steps. 5. MONOCHROME COMPILATION Compilation is performed by fetching 4-bits from one of the 4-bit digital signals making up the OUTG, OUTR, OUTB output. The monochrome 4 bits are compiled in the following order: MSB of G, 2nd bit of G, MSB of R, MSB of B. 12 MB86260 EXPLANATION OF FUNCTIONS 6. ANALOG OUTPUT OPERATION The analog segment is made up of a 4 channel D/A converter (DAC) and its bias. The input data for each channel is input independently at 4-bit intervals. The input data is read on a rising edge of the PCLK clock. DAC output is also performed on a rising edge of the PCLK. DAC output is obtained by electric current, and electric voltage can be obtained through the connection of load resistance. The output current is set by external resistance. Adjustment segments at different resistances are shown below. The relationship between the output voltage and these resistances is as follows: VO RL X: RK F X FR Input code (0 to 15), P: KP P R PR V REF 0 when X = 0, 1 when X 0 Usually: Note: KF = 2.784 R = 37.5, KP = 2.784 RFR = RPR = 5.22, VREF = 2.5 V RL: Load resistance at both terminals after composition. 13 MB86260 EXAMPLE OF EXTERNAL CONNECTION INTERFACE CIRCUITS 1. CPU INTERFACE CIRCUIT EXAMPLE 2. VRAM INTERFACE CIRCUIT EXAMPLE 14 MB86260 EXAMPLE OF EXTERNAL CONNECTION 3. ANALOG CIRCUIT INTERFACE EXAMPLE 15 MB86260 TEXT DISPLAY DATA As explained in the section entitled "Explanation of Functions," the text display data is decided after the display is determined using the TXMS, TXW2 and TXW1 signals (not synchronized with the PCLK signal). There are eight display modes, each one of which is set by TX1, TXB, TXR and TXG signals input in synchronized timing with the PCLK signal, and the output OUTR, OUTG, OUTB and OUTY signals determined. The following table shows which mode is set by each fixed input signal, and also how the output signal changes in accordance with the synchronous input signal, in decimal form. Concerning the output voltage, please refer to the decimal values in the table and the section entitled "6. Analog Output Operation" in "Explanation of Functions." 1. WHITE BALANCE MODES 1.1 White Balance Mode 1 1.2 White Balance Mode 2 TXMS = 1 TXW2 = 0 TXW1 = 0 TXMS = 1 TXW2 = 0 TXW1 = 1 T X I T X B T X R T X G O U T B O U T R O U T G O U T Y T X I T X B T X R T X G O U T B O U T R O U T G O U T Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 12 0 0 0 1 8 8 15 15 0 1 0 8 15 8 11 0 0 1 0 0 15 0 2 0 0 0 1 1 0 15 15 14 0 0 1 1 8 15 15 15 0 1 0 0 15 0 0 1 0 1 0 0 15 8 8 11 0 1 0 1 15 0 15 13 0 1 0 1 15 8 15 15 0 1 1 0 15 15 0 3 0 1 1 0 15 15 8 11 0 1 1 1 15 15 15 15 0 1 1 1 15 15 15 15 0 0 1 0 0 15 12 1 0 0 0 8 8 8 11 1 1 0 0 1 8 8 15 15 1 0 0 1 0 0 15 12 1 0 1 0 8 15 8 11 1 0 1 0 0 15 0 2 1 0 1 1 8 15 15 15 1 0 1 1 0 15 15 14 1 1 0 0 15 8 8 11 1 1 0 0 15 0 0 1 1 1 0 1 15 8 15 15 1 1 0 1 15 0 15 13 1 1 0 15 15 0 3 1 1 1 15 15 15 15 1 1 1 0 15 15 8 11 1 1 1 1 1 15 15 15 15 1 16 MB86260 TEXT DISPLAY DATA (continued) 1.3 White Balance Mode 3 TXMS = 1 TXW2 = 1 TXW1 = 0 1.4 White Balance Mode 4 TXMS = 1 TXW2 = 1 O U T R O U T G O U T Y T X I T X B T X R 0 0 0 0 0 TXW1 = 1 T X I T X B T X R T X G O U T B T X G O U T B O U T R O U T G O U T Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 12 0 0 0 1 4 4 15 12 0 0 1 0 0 15 0 2 0 0 1 0 4 15 4 6 0 0 1 1 0 15 15 14 0 0 1 1 4 15 15 14 0 1 0 0 15 0 0 1 0 1 0 0 15 4 4 5 0 1 0 1 15 0 15 13 0 1 0 1 15 4 15 13 0 1 1 0 15 15 0 3 0 1 1 0 15 15 4 7 0 1 1 1 15 15 15 15 0 1 1 1 15 15 15 15 1 0 0 0 4 4 4 4 1 0 0 0 4 4 4 4 1 0 0 1 4 4 15 12 1 0 0 1 0 0 15 12 1 0 1 0 4 15 4 6 1 0 1 0 0 15 0 2 1 0 1 1 4 15 15 14 1 0 1 1 0 15 15 14 1 1 0 0 15 4 4 5 1 1 0 0 15 0 0 1 1 1 0 1 15 4 15 13 1 1 0 1 15 0 15 13 1 1 1 0 15 15 4 7 1 1 1 0 15 15 0 3 1 1 1 1 15 15 15 15 1 1 1 1 15 15 15 15 2. ENHANCEMENT CHANGE MODES 2.1 Enhancement Change Mode 1 TXMS = 0 TXW2 = 0 TXW1 = 0 2.2 Enhancement Change Mode 2 TXMS = 0 TXW2 = 0 TXW1 = 1 T X I T X B T X R T X G O U T B O U T R O U T G O U T Y T X I T X B T X R T X G O U T B O U T R O U T G O U T Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 13 12 0 0 0 1 0 0 15 12 0 0 1 0 0 13 0 2 0 0 1 0 0 15 0 2 0 0 1 1 0 13 13 14 0 0 1 1 0 15 15 14 0 1 0 0 13 0 0 1 0 1 0 0 15 0 0 1 0 1 0 1 13 0 13 13 0 1 0 1 15 0 15 13 0 1 1 0 13 13 0 3 0 1 1 0 15 15 0 3 0 1 1 1 13 13 13 15 0 1 1 1 15 15 15 15 1 0 0 0 8 8 8 11 1 0 0 0 8 8 8 11 1 0 0 1 0 0 15 12 1 0 0 1 0 0 13 12 1 0 1 0 0 15 0 2 1 0 1 0 0 13 0 2 1 0 1 1 0 15 15 14 1 0 1 1 0 13 13 14 1 1 0 0 15 0 0 1 1 1 0 0 13 0 0 1 1 1 0 1 15 0 15 13 1 1 0 1 13 0 13 13 1 1 1 0 15 15 0 3 1 1 1 0 13 13 0 3 1 1 1 1 15 15 15 15 1 1 1 1 13 13 13 15 17 MB86260 2. ENHANCEMENT CHANGE MODES (continued) 2.3 Enhancement Change Mode 3 TXMS = 0 TXW2 = 1 TXW1 = 0 2.4 Enhancement Change Mode 4 TXMS = 0 TXW2 = 1 TXW1 = 1 T X I T X B T X R T X G O U T B O U T R O U T G O U T Y T X I T X B T X R T X G O U T B O U T R O U T G O U T Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 11 8 0 0 0 1 0 0 15 12 0 0 1 0 0 11 0 2 0 0 1 0 0 15 0 2 0 0 1 1 0 11 11 10 0 0 1 1 0 15 15 14 0 1 0 0 11 0 0 1 0 1 0 0 15 0 0 1 0 1 0 1 11 0 11 9 0 1 0 1 15 0 15 13 0 1 1 0 11 11 0 3 0 1 1 0 15 15 0 3 0 1 1 1 11 11 11 11 0 1 1 1 15 15 15 15 1 0 0 0 8 8 8 11 1 0 0 0 8 8 8 11 1 0 0 1 0 0 15 12 1 0 0 1 0 0 11 6 1 0 1 0 0 15 0 2 1 0 1 0 0 11 0 2 1 0 1 1 0 15 15 14 1 0 1 1 0 11 11 10 1 1 0 0 15 0 0 1 1 1 0 0 11 0 0 1 1 1 0 1 15 0 15 13 1 1 0 1 11 0 11 9 1 1 1 0 15 15 0 3 1 1 1 0 11 11 0 3 1 1 1 1 15 15 15 15 1 1 1 1 11 11 11 11 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. 18 MB86260 PACKAGE DIMENSIONS 42-LEAD PLASTIC DUAL IN-LINE PACKAGE (Case No.: DIP-42P-M01) Dimensions in inches (millimeters) 1988 FUJITSU LIMITED D42006S-3C 64-LEAD PLASTIC FLAT PACKAGE (Case No.: FPT-64P-M01) 1990 FUJITSU LIMITED F64005S-7C Dimensions in inches (millimeters) 19 MB86260 For further information please contact: Japan FUJITSU LIMITED Integrated Circuits and Semiconductor Marketing Furukawa Sogo Bldg., 6-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 Japan Tel: (03) 216-3211 Telex: 781-2224361 Fax: (03) 321 6-9771 North and South America FUJITSU MICROELECTRONlCS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804 USA Tel: 408-922-9000 Fax: 408-432-9044 Europe FUJITSU MIKROELEKTRONIK GmbH Arabella Centre 9. OG Lyoner Strasse 44-48 D-6000 Frankfurt 71 Federal Republic of Germany Tel: (069) 66320 Telex: 441963 Fax: (069) 6632122 Asia FUJITSU MICROELECTRONICS ASIA PTE LIMITED #06-04 to #06-07 Plaza By The Park No. 51 Bras Basah Road Singapore 0718 Tel: 336-1600 Telex: 55573 Fax: 336-1609 FUJITSU LIMITED 1990 20 Printed in Japan JV0093-90XA1