HEF4541BT,512 - NXP - Datasheet.Live

1. General description

The HEF4541B is a programmable timer which consists of a 16-stage binary counter, an

integrated oscillator to be used with external timing components, an automatic power-on

reset and output control logic. The frequency of the oscillator is determined by the external

component s RTC and CTC within the frequency range 1 Hz to 100 kHz. This oscillator may

be replaced by an external clock signal at input RS, the timer advances on the

positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the

master reset input (MR) enables the internal power-on reset. A HIGH level at input MR

resets the counter independent on all other inputs. Resetting disables the oscillator to

provide no active power dissipation.

A HIGH at input AR turns off the power-on reset to provide a low quiescent power

dissipation of the timer. The 16-stage counter divides the oscillator frequency by 28, 210,

213 or 216 depending on the state of the address inputs (A0, A1). The divided oscillator

frequency is available at outpu t O. The phase input (PH) features a complement ary output

signal. When the mode select input (MODE) is LOW the timer is a single transition timer

and when HIGH the timer is a 2n frequency divider.

It operates over a recommended VDD power supply r ange of 3 V to 1 5 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the automotive temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4541B

Programmable timer

Rev. 4 — 25 June 2012 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4541BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4541BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 4 — 25 June 2012 2 of 17

NXP Semiconductors HEF4541B

Programmable timer

4. Functional diagram

Fig 1. Functional di agram

001aai581

CTC

RTC

MODE

CONTROL INPUTS

BINARY

COUNTER

POWER-ON

RESET

OUTPUT

STAGE

Fig 2. Logic diag ram

001aai583

MODE

PH O

LATCH

RTC

CTC

POWER-ON

RESET

MUX

RESET

CP 28 COUNTER

222528

RESET

CP 28 COUNTER

Product data sheet Rev. 4 — 25 June 2012 3 of 17

NXP Semiconductors HEF4541B

Programmable timer

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 3. Pin configuratio n

HEF4541B

RTC VDD

CTC A1

RS A0

n.c. n.c.

AR MODE

MR PH

VSS O

001aai582

Table 2. Pin description

Symbol Pin Description

RTC 1 external resistor connection

CTC 2 external capacitor connection

RS 3 external resistor connection (RS) or external clock input

nc 4, 11 not connected

AR 5 auto reset input (active low)

MR 6 master reset input

VSS 7 ground (0 V)

O 8 timer output

PH 9 phase input

MODE 10 mode select input

A0, A1 12, 13 address inputs

VDD 14 supply voltage

Product data sheet Rev. 4 — 25 June 2012 4 of 17

NXP Semiconductors HEF4541B

Programmable timer

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

[2] For correct power-on reset, the supply voltage should be above 8.5 V. For VDD < 8.5 V, disable the autoreset and connect AR to VDD.

[3] The timer is initialized on a reset pulse and the output changes state after 2n-1 counts and remains in that state (latched). Reset of this

latch is obtained by master reset or by a LOW to HIGH transition on the MODE input.

7. Limiting values

[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.

Table 3. Function table[1]

Input MODE

AR MR PH MODE

HLXXauto reset disabled

LLXXauto reset enabled[2]

XHXXmaster reset active

XLXHnormal operation selected division to output

XLXLsingle-cycle mode[3]

XLLXoutput initially LOW after reset

XLHXoutput initially HIGH, after reset

Table 4. Frequency selection table

A0 A1 Number of counter stages n

LL13 8192

L H 10 1024

H L 8 256

HH16 65536

fOSC

----------2n

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current O output - ±10 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot total power dissipation Tamb = −40 °C to +85 °C

DIP14 package [1] -750mW

SO14 package [2] -500mW

P power dissipation - 100 mW

Product data sheet Rev. 4 — 25 June 2012 5 of 17

NXP Semiconductors HEF4541B

Programmable timer

8. Recommended operating conditions

9. Static characteristics

Table 6. Recommended operating con ditions

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 3 15 V

VIinput voltage 0 VDD V

Tamb ambient temperature in free air −40 +85 °C

Δt/ΔV input transition rise and fall rate VDD = 5 V - 3.7 5 μs/V

VDD = 10 V - 0.5 μs/V

VDD = 15 V - 0.08 μs/V

Table 7. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level

input voltage |IO|<1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage |IO|<1 μA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level

output voltage |IO|<1 μA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage |IO|<1 μA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level

output current CTC, RTC;

VO = 2.5 V 5 V - −1.4 - −1.2 - −0.95 mA

VO= 4.6 V 5 V - −0.5 - −0.4 - −0.3 mA

VO = 9.5 V 10 V - −1.4 - −1.2 - −0.95 mA

VO = 13.5 V 15 V - −4.8 - −4.0 - −3.2 mA

O;VO = 2.5 V 5 V - −1.7 - −1.4 - −1.1 mA

VO= 4.6 V 5 V - −0.64 - −0.5 - −0.36 mA

VO = 9.5 V 10 V - −1.6 - −1.3 - −0.9 mA

VO = 13.5 V 15 V - −4.2 - −3.4 - −2.4 mA

Product data sheet Rev. 4 — 25 June 2012 6 of 17

NXP Semiconductors HEF4541B

Programmable timer

IOL LOW-level

output current CTC, RTC;

VO = 0.4 V 5 V 0.33 - 0.27 - 0.20 - mA

VO = 0.5 V 10 V 1.0 - 0.85 - 0.68 - mA

VO = 1.5 V 15 V 3.2 - 2.7 - 2.3 - mA

O;VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.2 - 2.4 - mA

IIinput leakage

current 15 V - ±0.1 - ±0.1 - ±1.0 μA

IDD supply current IO = 0 A 5 V - 5 - 5 - 150 μA

10 V - 10 - 10 - 300 μA

15 V - 20 - 20 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Table 7. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

Table 8. Reset characteristics

VSS = 0 V; VI = VSS or VDD; see Table 12 for test conditions; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = +25 °C Tamb = +85 °CUnit

Min Max Min Typ Max Min Max

IDD supply current supply current for

power-on reset

enable;

AR = MR = 0 V; Other

inputs at 0 V or VDD

5 V - 80 - 20 80 - 230 μA

10 V - 750 - 250 600 - 700 μA

15 V - 1.6 - 0.5 1.3 - 1.5 mA

VDD supply voltage supply voltage for

automatic reset

initialization;

AR = MR = 0 V; Other

inputs at 0 V or VDD

---8.55---V

Product data sheet Rev. 4 — 25 June 2012 7 of 17

NXP Semiconductors HEF4541B

Programmable timer

10. Dynamic characteristics

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

[2] tpd is the same as tPHL and tPLH.

[3] tW is the same as tWL(min) and tWH(min).

Table 9. Dynamic characteristics

VSS = 0 V; Tamb = 25

C unless otherwise specified. For test circuit, see Figure 5.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ[1] Max Unit

tpd propagation delay RS to O;

28selected;

see Figure 4

5 V [2] 348 ns + (0.55 ns/p F)CL- 375 750 ns

10 V 139 ns + (0.2 3 ns/pF)CL- 150 300 ns

15 V 102 ns + (0.1 6 ns/pF)CL- 110 220 ns

RS to O;

210 selected;

see Figure 4

5 V 398 ns + (0.55 ns/pF)CL- 425 850 ns

10 V 154 ns + (0.2 3 ns/pF)CL- 165 330 ns

15 V 112 ns + (0.16 ns/pF)CL- 120 240 ns

RS to O;

213 selected;

see Figure 4

5 V 483 ns + (0.55 ns/pF)CL- 510 1020 ns

10 V 179 ns + (0.2 3 ns/pF)CL- 190 380 ns

15 V 127 ns + (0.1 6 ns/pF)CL- 135 270 ns

RS to O;

216 selected;

see Figure 4

5 V 548 ns + (0.55 ns/pF)CL- 575 1150 ns

10 V 199 ns + (0.2 3 ns/pF)CL- 210 420 ns

15 V 142 ns + (0.1 6 ns/pF)CL- 150 300 ns

tWpulse width RS LOW;

MR HIGH;

see Figure 4

5 V [3] 60 30 - ns

10 V 30 15 - ns

15 V 24 12 - ns

fclk(max) maximum clock

frequency RS; see Figure 4 5 V 8 16 - MHz

10 V 15 30 - MHz

15 V 18 36 - MHz

fosc oscillator frequency Rt = 5 kΩ;

Ct=1nF;

RS=10kΩ;

see Figure 6

5 V - 90 - kHz

10 V - 90 - kHz

15 V - 90 - kHz

Rt = 56 kΩ;

Ct=1nF;

RS= 120 kΩ;

see Figure 6

5 V - 8 - kHz

10 V - 8 - kHz

15 V - 8 - kHz

Product data sheet Rev. 4 — 25 June 2012 8 of 17

NXP Semiconductors HEF4541B

Programmable timer

[1] fi= input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V;

fosc = oscillator frequency in MHz; CTC = timing capacitance in pF.

11. Waveforms

Table 10. Dynamic power dissipation

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula

Per package

PDdynamic power dissipation 5 V PD = 1300 × fi + (fo × CL × VDD2) μW

10 V PD = 5300 × fi + (fo × CL × VDD2)μW

15 V PD = 12000 × fi + (fo × CL × VDD2) μW

Using the on-chip o scillator

PD(Tot) Total dynamic power dissipation 5 V PD = 1300 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 10VDD μW

10 V PD = 5300 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 100VDD μW

15 V PD = 12000 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 400VDD μW

VOL and VOH are typical output voltage levels that occur with the output load.

Measurement are points given in Table 11, the test circuit in Figure 5 and the test data in Table 12

(1) 2n pulses as selected by address inputs (A0, A1).

Fig 4. Propagation delay clock (RS) to output (O), clock pulse width and maximum clock frequency

aaa-003391

RS input

VSS

O output

VOH

VOL

MR input

VSS

tWH(min)

1/fclk(max)

tWH(min)

tWL(min)

tPLH tPHL

(1)

Table 11. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 4 — 25 June 2012 9 of 17

NXP Semiconductors HEF4541B

Programmable timer

Test data is given in Table 12.

Definitions for test circuit:

DUT - Device Under Test.

RL = Load resistance.

CL = load capacitance.

RT = Termination resistance should be equal to output impedance of Zo of the pulse generator.

Fig 5. Test circuit for measuring switching times

VDD

VIVO

001aag182

DUT

Table 12. Test data

Supply Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

Product data sheet Rev. 4 — 25 June 2012 10 of 17

NXP Semiconductors HEF4541B

Programmable timer

12. Application information

RC oscillator timing component limitations

The oscillator frequency is mainly determined by RTCCTC, provided RTC << RS and

RSC2<< RTCCTC. The function of RS is to minimize the influence of the forward voltage

across the input protection diodes on the frequency. The stray capacitance C2 should be

kept as small as possible. In consideration of accuracy, CTC must be larger than the

inherent stray capacitance. RTC must be larger than the LOCMOS ‘ON’ resistance in

series with it, which typically is 500 Ω at VDD = 5 V, 300 Ω at VDD = 10 V and 200 Ω at

VDD =15V.

The recommended values for these components to maintain agreement with the typical

oscillation formula are: CTC ≥ 100 pF, up to any typical value, 10 kΩ ≤ RTC ≤ 1 MΩ.

Typical formula for oscillator frequency: .

Fig 6. Externa l component connection for RC oscillator; RS ≈ RTC

001aai584

C2 RSCTC RTC

CTC

RTC

clock to

counter

reset

from logic

fosc 1

2.3 RTC

×CTC

----------------------------------------

a. CTC curve at RTC = 56 kΩ; RS = 120 kΩ.b.R

TC curve at CTC = 1 nF; RS = 2 RTC.

Fig 7. RC oscillator frequency as a fun cti on of RTC and CTC at VDD = 5 to 15 V; Tamb = 25 °C

001aai586

(μF)

-4

-1

-2

-3

osc

(Hz)

001aai585

(Ω)

osc

(Hz)

Product data sheet Rev. 4 — 25 June 2012 11 of 17

NXP Semiconductors HEF4541B

Programmable timer

a. RTC = 56 kΩ; CTC = 1 nF; RS = 0 Ω.b.R

TC = 56 kΩ; CTC = 1 nF; RS = 120 kΩ.

Fig 8. Frequency de v ia tion (Δf) as a function of ambient temperature

Tamb (°C)

-75 12575-25 25

001aai587

-5

∆f

(%)

-10

VDD = 15 V

10 V

5 V

Tamb (°C)

-75 12575-25 25

001aai588

-5

∆f

(%)

-10

VDD = 15 V

10 V

5 V

Product data sheet Rev. 4 — 25 June 2012 12 of 17

NXP Semiconductors HEF4541B

Programmable timer

13. Package outline

Fig 9. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 4 — 25 June 2012 13 of 17

NXP Semiconductors HEF4541B

Programmable timer

Fig 10. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 4 — 25 June 2012 14 of 17

NXP Semiconductors HEF4541B

Programmable timer

14. Abbreviations

15. Revision history

Table 13. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4541B v.4 20120625 Product data sheet - HEF4541B_CNV v.3

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guideline s

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 2 “Features and benefits” added.

HEF4541B_CNV v.3 19950101 Product specification - HEF4541B_CNV v.2

HEF4541B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 4 — 25 June 2012 15 of 17

NXP Semiconductors HEF4541B

Programmable timer

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Product data sheet Rev. 4 — 25 June 2012 16 of 17

NXP Semiconductors HEF4541B

Programmable timer

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Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4541B

Programmable timer

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 June 2012

Document iden tifier: HEF4541B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

12 Application information. . . . . . . . . . . . . . . . . . 10

RC oscillator timing compon ent limitations. . . .10

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

17 Contact information. . . . . . . . . . . . . . . . . . . . . 16

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17