KSZ8091MNX/KSZ8091RNB
10Base-T/100Base-TX
Physical Layer Transceiver
Data Sheet Rev. 1.0
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 2013 M9999-021513-1.0
General Description
The KSZ8091 is a single-supply 10Base-T/100Base-TX
Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted
pair (UTP) cable.
The KSZ8091 is a highly-integrated PHY solution. It reduces
board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs, by integrating a
low-noise regulator to supply the 1.2V core, and by offering a
flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091MNX offers the Media Independent Interface
(MII) and the KSZ8091RNB offers the Reduced Media
Independent Interface (RMII) for direct connection with
MII/RMII-compliant Ethernet MAC processors and switches.
Energy Efficient Ethernet (EEE) provides further power
saving during idle traffic periods and Wake-on-LAN (WOL)
provides a mechanism for the KSZ8091 to wake up a
system that is in standby power mode.
The KSZ8091 provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ8091 I/Os and the
board. Micrel LinkMD® TDR-based cable diagnostics
identify faulty copper cabling.
The KSZ8091MNX and KSZ8091RNB are available in 32-
pin, lead-free QFN packages (see “Ordering Information”).
Features
• Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• MII interface support (KSZ8091MNX)
• RMII v1.2 Interface support with a 50MHz reference
clock output to MAC, and an option to input a 50MHz
reference clock (KSZ8091RNB)
• Back-to-back mode support for a 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link and activity status indication, plus
speed indication for KSZ8091RNB
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and enable option
• Auto-negotiation to automatically select the highest link-
up speed (10/100Mbps) and duplex (half/full)
• Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode and clock stoppage (MII version only)
for 100Base-TX and transmit amplitude reduction with
10Base-Te option
• Wake-on-LAN (WOL) support with either magic packet,
link status change, or robust custom-packet detection
Functional Diagram
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
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Features (Continued)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty
copper cabling
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for
1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5mm x 5mm) QFN package
Applications
• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer
Ordering Information
Part Number Temperature
Range Package Lead
Finish Wire
Bonding Description
KSZ8091MNXCA 0°C to 70°C 32-Pin QFN Pb-Free Gold MII, EEE and WOL Support, Commercial
Temperature, Gold Wire Bonding
KSZ8091MNXIA(1) −40°C to 85°C 32-Pin QFN Pb-Free Gold MII, EEE and WOL Support, Industrial
Temperature, Gold Wire Bonding
KSZ8091RNBCA 0°C to 70°C 32-Pin QFN Pb-Free Gold
RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output (power-up default),
EEE and WOL Support, Commercial
Temperature, Gold Wire Bonding
KSZ8091RNBIA(1) −40°C to 85°C 32-Pin QFN Pb-Free Gold
RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output (power-up default),
EEE and WOL Support, Industrial Temperature,
Gold Wire Bonding
KSZ8091MNX-EVAL 0°C to 70°C 32-Pin QFN Pb-Free
KSZ8091MNX Evaluation Board
(Mounted with KSZ8091MNX device in
commercial temperature)
KSZ8091RNB-EVAL 0°C to 70°C 32-Pin QFN Pb-Free
KSZ8091RNB Evaluation Board
(Mounted with KSZ8091RNB device in
commercial temperature)
Note:
1. Contact factory for lead time.
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 3 M9999-021513-1.0
Revision History
Revision Date Summary of Changes
1.0 2/15/13 Data sheet created
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 4 M9999-021513-1.0
Contents
General Description ................................................................................................................................................................ 1
Features .................................................................................................................................................................................. 1
Functional Diagram ................................................................................................................................................................. 1
Features (Continued) .............................................................................................................................................................. 2
Applications ............................................................................................................................................................................. 2
Ordering Information ............................................................................................................................................................... 2
Revision History ...................................................................................................................................................................... 3
Contents .................................................................................................................................................................................. 4
List of Figures.......................................................................................................................................................................... 7
List of Tables ........................................................................................................................................................................... 8
Pin Configuration– KSZ8091MNX .......................................................................................................................................... 9
Pin Description– KSZ8091MNX............................................................................................................................................ 10
Strapping Options – KSZ8091MNX ...................................................................................................................................... 13
Pin Configuration – KSZ8091RNB........................................................................................................................................ 14
Pin Description– KSZ8091RNB ............................................................................................................................................ 15
Strapping Options – KSZ8091RNB....................................................................................................................................... 19
Functional Description: 10Base-T/100Base-TX Transceiver................................................................................................ 20
100Base-TX Transmit.......................................................................................................................................................................... 20
100Base-TX Receive........................................................................................................................................................................... 20
Scrambler/De-Scrambler (100Base-TX Only)...................................................................................................................................... 20
10Base-T Transmit .............................................................................................................................................................................. 21
10Base-T Receive ............................................................................................................................................................................... 21
SQE and Jabber Function (10Base-T Only) ........................................................................................................................................ 21
PLL Clock Synthesizer ........................................................................................................................................................................ 21
Auto-Negotiation.................................................................................................................................................................................. 21
MII Interface (KSZ8091MNX only) ........................................................................................................................................ 22
MII Signal Definition............................................................................................................................................................................. 22
Transmit Clock (TXC) .......................................................................................................................................................................... 23
Transmit Enable (TXEN) ..................................................................................................................................................................... 23
Transmit Data[3:0] (TXD[3:0]).............................................................................................................................................................. 23
Transmit Error (TXER)......................................................................................................................................................................... 23
Receive Clock (RXC)........................................................................................................................................................................... 23
Receive Data Valid (RXDV)................................................................................................................................................................. 24
Receive Data[3:0] (RXD[3:0]) .............................................................................................................................................................. 24
Receive Error (RXER) ......................................................................................................................................................................... 24
Carrier Sense (CRS) ........................................................................................................................................................................... 24
Collision (COL) .................................................................................................................................................................................... 24
MII Signal Diagram .............................................................................................................................................................................. 24
RMII Data Interface (KSZ8091RNB only) ............................................................................................................................. 25
RMII – 25MHz Clock Mode.................................................................................................................................................................. 25
RMII – 50MHz Clock Mode.................................................................................................................................................................. 25
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RMII Signal Definition .......................................................................................................................................................................... 25
Reference Clock (REF_CLK)............................................................................................................................................................... 26
Transmit Enable (TXEN) ..................................................................................................................................................................... 26
Transmit Data[1:0] (TXD[1:0]).............................................................................................................................................................. 26
Carrier Sense / Receive Data Valid (CRS_DV) ................................................................................................................................... 26
Receive Data[1:0] (RXD[1:0]) .............................................................................................................................................................. 26
Receive Error (RXER) ......................................................................................................................................................................... 27
Collision Detection (COL) .................................................................................................................................................................... 27
RMII Signal Diagram ........................................................................................................................................................................... 27
Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 28
MII Back-to-Back Mode (KSZ8091MNX only)...................................................................................................................................... 28
RMII Back-to-Back Mode (KSZ8091RNB only) ................................................................................................................................... 29
MII Management (MIIM) Interface......................................................................................................................................... 30
Interrupt (INTRP)................................................................................................................................................................... 30
HP Auto MDI/MDI-X .............................................................................................................................................................. 30
Straight Cable...................................................................................................................................................................................... 31
Crossover Cable.................................................................................................................................................................................. 32
Loopback Mode..................................................................................................................................................................... 32
Local (Digital) Loopback ...................................................................................................................................................................... 32
Remote (Analog) Loopback ................................................................................................................................................................. 33
LinkMD® Cable Diagnostic .................................................................................................................................................... 34
NAND Tree Support .............................................................................................................................................................. 34
NAND Tree I/O Testing ....................................................................................................................................................................... 35
Power Management .............................................................................................................................................................. 35
Power-Saving Mode ............................................................................................................................................................................ 36
Energy-Detect Power-Down Mode ...................................................................................................................................................... 36
Power-Down Mode .............................................................................................................................................................................. 36
Slow-Oscillator Mode........................................................................................................................................................................... 36
Energy Efficient Ethernet (EEE)............................................................................................................................................ 36
Transmit Direction Control (MAC-to-PHY) ........................................................................................................................................... 37
Receive Direction Control (PHY-to-MAC) ............................................................................................................................................ 38
Registers Associated with EEE ........................................................................................................................................................... 39
Wake-On-LAN ....................................................................................................................................................................... 39
Magic-Packet Detection....................................................................................................................................................................... 40
Customized-Packet Detection ............................................................................................................................................................. 40
Link Status Change Detection ............................................................................................................................................................. 40
Reference Circuit for Power and Ground Connections......................................................................................................... 41
Typical Current/Power Consumption .................................................................................................................................... 42
Transceiver (3.3V), Digital I/Os (3.3V)................................................................................................................................................. 42
Transceiver (3.3V), Digital I/Os (2.5V)................................................................................................................................................. 42
Transceiver (3.3V), Digital I/Os (1.8V)................................................................................................................................................. 43
Register Map......................................................................................................................................................................... 44
Standard Registers ............................................................................................................................................................... 46
IEEE-Defined Registers – Descriptions ............................................................................................................................................... 46
Vendor-Specific Registers – Descriptions ........................................................................................................................................... 50
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MMD Registers...................................................................................................................................................................... 56
MMD Registers – Descriptions ............................................................................................................................................................ 57
Absolute Maximum Ratings(1) ............................................................................................................................................... 63
Operating Ratings(2) .............................................................................................................................................................. 63
Electrical Characteristics(3) .................................................................................................................................................... 63
Timing Diagrams ................................................................................................................................................................... 65
MII SQE Timing (10Base-T) ................................................................................................................................................................ 65
MII Transmit Timing (10Base-T) .......................................................................................................................................................... 66
MII Receive Timing (10Base-T) ........................................................................................................................................................... 67
MII Transmit Timing (100Base-TX)...................................................................................................................................................... 68
MII Receive Timing (100Base-TX)....................................................................................................................................................... 69
RMII Timing ......................................................................................................................................................................................... 70
Auto-Negotiation Timing ...................................................................................................................................................................... 71
MDC/MDIO Timing .............................................................................................................................................................................. 72
Power-Up/Reset Timing ...................................................................................................................................................................... 73
Reset Circuit.......................................................................................................................................................................... 74
Reference Circuits – LED Strap-In Pins................................................................................................................................ 75
Reference Clock – Connection and Selection ...................................................................................................................... 76
Magnetic – Connection and Selection .................................................................................................................................. 77
Recommended Land Pattern ................................................................................................................................................ 79
Package Information(1) .......................................................................................................................................................... 80
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List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 22
Figure 2. KSZ8091MNX MII Interface.................................................................................................................................. 25
Figure 3. KSZ8091RNB RMII Interface (25MHz Clock Mode)............................................................................................. 27
Figure 4. KSZ8091RNB RMII Interface (50MHz Clock Mode)............................................................................................. 28
Figure 5. KSZ8091MNX/RNB to KSZ8091MNX/RNB Back-to-Back Copper Repeater ...................................................... 28
Figure 6. Typical Straight Cable Connection ....................................................................................................................... 31
Figure 7. Typical Crossover Cable Connection ................................................................................................................... 32
Figure 8. Local (Digital) Loopback ....................................................................................................................................... 32
Figure 9. Remote (Analog) Loopback .................................................................................................................................. 33
Figure 10. LPI Mode (Refresh Transmissions and Quiet Periods) ...................................................................................... 37
Figure 11. LPI Transition – MII (100Mbps) Transmit ........................................................................................................... 37
Figure 12. LPI Transition – RMII (100Mbps) Transmit......................................................................................................... 38
Figure 13. LPI Transition – MII (100Mbps) Receive ............................................................................................................ 38
Figure 14. LPI Transition – RMII (100Mbps) Receive.......................................................................................................... 39
Figure 15. KSZ8091MNX/RNB Power and Ground Connections........................................................................................ 41
Figure 16. MII SQE Timing (10Base-T) ............................................................................................................................... 65
Figure 17. MII Transmit Timing (10Base-T) ......................................................................................................................... 66
Figure 18. MII Receive Timing (10Base-T) .......................................................................................................................... 67
Figure 19. MII Transmit Timing (100Base-TX)..................................................................................................................... 68
Figure 20. MII Receive Timing (100Base-TX)...................................................................................................................... 69
Figure 21. RMII Timing – Data Received from RMII ............................................................................................................ 70
Figure 22. RMII Timing – Data Input to RMII ....................................................................................................................... 70
Figure 23. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 71
Figure 24. MDC/MDIO Timing.............................................................................................................................................. 72
Figure 25. Power-Up/Reset Timing...................................................................................................................................... 73
Figure 26. Recommended Reset Circuit.............................................................................................................................. 74
Figure 27. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 74
Figure 28. Reference Circuits for LED Strapping Pins......................................................................................................... 75
Figure 29. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 76
Figure 30. 50MHz Oscillator Reference Clock Connection ................................................................................................. 76
Figure 31. Typical Magnetic Interface Circuit....................................................................................................................... 77
Figure 32. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN ................................................................................. 79
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List of Tables
Table 1. MII Signal Definition ............................................................................................................................................... 23
Table 2. RMII Signal Definition............................................................................................................................................. 26
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)............................................ 29
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ...................................... 29
Table 5. MII Management Frame Format for the KSZ8091MNX/RNB ................................................................................ 30
Table 6. MDI/MDI-X Pin Definition ....................................................................................................................................... 31
Table 7. NAND Tree Test Pin Order for KSZ8091MNX....................................................................................................... 34
Table 8. NAND Tree Test Pin Order for KSZ8091RNB ....................................................................................................... 35
Table 9. KSZ8091MNX/RNB Power Pin Description........................................................................................................... 41
Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) .......................................................... 42
Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) .......................................................... 42
Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) .......................................................... 43
Table 13. Standard Registers Supported by KSZ8091MNX/RNB ....................................................................................... 44
Table 14. MMD Registers Supported by KSZ8091MNX/RNB ............................................................................................. 45
Table 15. Portal Registers (Access to Indirect MMD Registers).......................................................................................... 56
Table 16. MII SQE Timing (10Base-T) Parameters ............................................................................................................. 65
Table 17. MII Transmit Timing (10Base-T) Parameters ...................................................................................................... 66
Table 18. MII Receive Timing (10Base-T) Parameters ....................................................................................................... 67
Table 19. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 68
Table 20. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 69
Table 21. RMII Timing Parameters – KSZ8091RNB (25MHz input to XI pin, 50MHz output from REF_CLK pin) ............. 70
Table 22. RMII Timing Parameters – KSZ8091RNB (50MHz input to XI pin) ..................................................................... 70
Table 23. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters............................................................................... 71
Table 24. MDC/MDIO Timing Parameters ........................................................................................................................... 72
Table 25. Power-Up/Reset Timing Parameters ................................................................................................................... 73
Table 26. 25MHz Crystal / Reference Clock Selection Criteria ........................................................................................... 76
Table 27. 50MHz Oscillator / Reference Clock Selection Criteria ....................................................................................... 76
Table 28. Magnetics Selection Criteria ................................................................................................................................ 78
Table 29. Compatible Single-Port 10/100 Magnetics........................................................................................................... 78
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Pin Configuration– KSZ8091MNX
32-Pin (5mm x 5mm) QFN
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 10 M9999-021513-1.0
Pin Description– KSZ8091MNX
Pin Number Pin Name Type(1) Pin Function
1 GND Gnd Ground
2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091MNX)
Decouple with 2.2µF and 0.1µF capacitors to ground.
3 VDDA_3.3 P 3.3V analog VDD
4 RXM I/O
Physical receive or transmit signal (− differential)
5 RXP I/O Physical receive or transmit signal (+ differential)
6 TXM I/O
Physical transmit or receive signal (− differential)
7 TXP I/O Physical transmit or receive signal (+ differential)
8 XO O Crystal feedback for 25MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9 XI I Crystal / Oscillator / External Clock input
25MHz ±50ppm
10 REXT I Set PHY transmit output current
Connect a 6.49k resistor to ground on this pin.
11 MDIO Ipu/Opu Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain, and requires an external 1.0k
pull-up resistor.
12 MDC Ipu Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
13 RXD3/
PHYAD0
Ipu/O MII mode: MII Receive Data Output[3](2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
14 RXD2/
PHYAD1
Ipd/O MII mode: MII Receive Data Output[2](2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
15 RXD1/
PHYAD2
Ipd/O MII mode: MII Receive Data Output[1](2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
16 RXD0/
DUPLEX
Ipu/O MII mode: MII Receive Data Output[0](2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD
18 RXDV/
CONFIG2
Ipd/O MII mode: MII Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
19 RXC/
B-CAST_OFF
Ipd/O MII mode: MII Receive Clock output
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
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Pin Number Pin Name Type(1) Pin Function
20 RXER/
ISO
Ipd/O MII mode: MII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
21 INTRP/
PME_N2/
NAND_Tree#
Ipu/Opu Interrupt output: Programmable interrupt output, with register 1Bh as the Interrupt
Control/Status register, for programming the interrupt conditions
and reading the interrupt status. Register 1Fh, bit [9] sets
the interrupt output to active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external
1.0k pull-up resistor to VDDIO (digital VDD).
22 TXC/
PME_EN
Ipd/O MII mode: MII Transmit Clock output
MII back-to-back mode: MII Transmit Clock input
Config mode: The pull-up/pull-down value is latched as PME_EN at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
23 TXEN I MII mode: MII Transmit Enable input
24 TXD0 I
MII mode: MII Transmit Data Input[0](3)
25 TXD1 I
MII mode: MII Transmit Data Input[1](3)
26 TXD2 I
MII mode: MII Transmit Data Input[2](3)
27 TXD3 I
MII Mode: MII Transmit Data Input[3](3)
28 COL/
CONFIG0
Ipd/O MII mode: MII Collision Detect output
Config mode: The pull-up/pull-down value is latched as CONFIG0 at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
29 CRS/
CONFIG1
Ipd/O MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
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Pin Number Pin Name Type(1) Pin Function
30 LED0/
PME_N1/
NWAYEN
Ipu/O LED output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an open-drain, and
requires an external 1.0K pull-up resistor to VDDIO (digital
V
DD).
Config mode: Latched as auto-negotiation enable (register 0h, bit [12]) at the
de-assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
The LED0 pin is programmable using register 1Fh bits [5:4], and is defined as
follows.
LED mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED mode = [10], [11] Reserved
31 TXER Ipd MII mode: MII Transmit Error input
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MNX
transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to
KSZ8091MNX and can be left as a no connect.
32 RST# Ipu Chip reset (active low)
PADDLE GND Gnd Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see “Electrical Characteristics” for value).
Ipd = Input with internal pull-down (see “Electrical Characteristics” for value).
Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see “Electrical Characteristics” for value) and output with internal pull-up (see “Electrical Characteristics” for
value).
2. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC.
3. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC.
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Strapping Options – KSZ8091MNX
Pin Number Pin Name Type(1) Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0
to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high
or writing a ‘1’ to register 16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
000 MII (default)
110 MII back-to-back
001 – 101, 111 Reserved – not used
22 PME_EN Ipd/O PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 16h, bit [15].
20 ISO Ipd/O Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h, bit [10].
16 DUPLEX Ipu/O Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into register 0h, bit [8].
30 NWAYEN Ipu/O Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into register 0h, bit [12].
19 B-CAST_OFF Ipd/O Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21 NAND_Tree# Ipu/Opu NAND tree mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1. Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see “Electrical Characteristics” for value) and output with internal pull-up (see “Electrical Characteristics” for value).
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7k) or pull-downs (1.0k) should be added on these PHY
strap-in pins to ensure that the intended values are strapped-in correctly.
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Pin Configuration – KSZ8091RNB
32-Pin (5mm x 5mm) QFN
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Pin Description– KSZ8091RNB
Pin Number Pin Name Type(1) Pin Function
1 GND Gnd Ground
2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091RNB)
Decouple with 2.2µF and 0.1µF capacitors to ground.
3 VDDA_3.3 P 3.3V analog VDD
4 RXM I/O
Physical receive or transmit signal (− differential)
5 RXP I/O Physical receive or transmit signal (+ differential)
6 TXM I/O
Physical transmit or receive signal (− differential)
7 TXP I/O Physical transmit or receive signal (+ differential)
8 XO O Crystal feedback for 25MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9 XI I 25MHz Mode: 25MHz ±50ppm Crystal / Oscillator / External Clock Input
50MHz Mode: 50MHz ±50ppm Oscillator / External Clock Input
10 REXT I Set PHY transmit output current
Connect a 6.49k resistor to ground on this pin.
11 MDIO Ipu/Opu Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain, and requires an external 1.0k
pull-up resistor.
12 MDC Ipu Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
13 PHYAD0 Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of
reset.
See the “Strapping Options – KSZ8091RNB” section for details.
14 PHYAD1 Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of
reset.
See the “Strapping Options – KSZ8091RNB” section for details.
15 RXD1/
PHYAD2
Ipd/O RMII mode: RMII Receive Data Output[1](2)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
16 RXD0/
DUPLEX
Ipu/O RMII mode: RMII Receive Data Output[0](2)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD
18 CRS_DV/
CONFIG2
Ipd/O RMII mode: RMII Carrier Sense/Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
19 REF_CLK/
B-CAST_OFF
Ipd/O RMII mode: 25MHz mode: This pin provides the 50MHz RMII reference clock
output to the MAC. See also XI (pin 9).
50MHz mode: This pin is a no connect. See also XI (pin 9).
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
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Pin Number Pin Name Type(1) Pin Function
20 RXER/
ISO
Ipd/O RMII mode: RMII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
21 INTRP/
PME_N2/
NAND_Tree#
Ipu/Opu Interrupt output: Programmable interrupt output, with register 1Bh as the Interrupt
Control/Status register, for programming the interrupt conditions
and reading the interrupt status. Register 1Fh, bit [9] sets
the interrupt output to active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external
1.0k pull-up resistor to VDDIO (digital VDD).
22 PME_EN Ipd/O The pull-up/pull-down value is latched as PME_EN at the de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
23 TXEN I RMII Transmit Enable input
24 TXD0 I
RMII Transmit Data Input[0](3)
25 TXD1 I
RMII Transmit Data Input[1](3)
26 NC NC No connect – This pin is not bonded and can be left floating.
27 NC NC No connect – This pin is not bonded and can be left floating.
28 CONFIG0 Ipd/O The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
29 CONFIG1 Ipd/O The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
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Pin Number Pin Name Type(1) Pin Function
30 LED0/
PME_N1/
NWAYEN
Ipu/O LED output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an open-drain, and
requires an external 1.0K pull-up resistor to VDDIO (digital
V
DD).
Config mode: Latched as auto-negotiation enable (register 0h, bit [12]) at the
de-assertion of reset.
See the “Strapping Options – KSZ8091RNB” section for details.
The LED0 pin is programmable using register 1Fh bits [5:4], and is defined as
follows.
LED mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED mode = [10], [11] Reserved
31 LED1/
SPEED
Ipu/O LED output: Programmable LED1 output
Config mode: Latched as Speed (register 0h, bit [13]) at the de-assertion of
reset.
See the “Strapping Options – KSZ8091RNB” section for details.
The LED1 pin is programmable using register 1Fh bits [5:4], and is defined as
follows.
LED mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED mode = [01]
Activity Pin State LED Definition
No activity High OFF
Activity Toggle Blinking
LED mode = [10], [11] Reserved
32 RST# Ipu Chip reset (active low)
PADDLE GND Gnd Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
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O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see “Electrical Characteristics” for value).
Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see “Electrical Characteristics” for value) and output with internal pull-up (see “Electrical Characteristics” for
value).
NC = Pin is not bonded to the die.
2. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted,
two bits of recovered data are sent by the PHY to the MAC.
3. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two
bits of data are received by the PHY from the MAC.
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Strapping Options – KSZ8091RNB
Pin Number Pin Name Type(1) Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0
to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high
or writing a ‘1’ to register 16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
001 RMII
101 RMII back-to-back
000, 010 – 100, 110, 111 Reserved – not used
22 PME_EN Ipd/O PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 16h, bit [15].
20 ISO Ipd/O Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h, bit [10].
31 SPEED Ipu/O Speed mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the
speed select, and also is latched into register 4h (auto-negotiation advertisement) as
the speed capability support.
16 DUPLEX Ipu/O Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into register 0h, bit [8].
30 NWAYEN Ipu/O Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into register 0h, bit [12].
19 B-CAST_OFF Ipd/O Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21 NAND_Tree# Ipu/Opu NAND tree mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1. Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.
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Ipu/Opu = Input with internal pull-up (see “Electrical Characteristics” for value) and output with internal pull-up (see “Electrical Characteristics” for value).
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7k) or pull-downs (1.0k) should be added on these PHY
strap-in pins to ensure that the intended values are strapped-in correctly.
Functional Description: 10Base-T/100Base-TX Transceiver
The KSZ8091 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8091 supports 10Base-T and 100Base-TX for transmission and reception of data over
a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for
straight-through and crossover cables.
On the MAC processor side, the KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB offers
the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC
processors and switches, respectively.
The MII management bus option gives the MAC processor complete access to the KSZ8091 control and status registers.
Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
The KSZ8091MNX/RNB is used to refer to both KSZ8091MNX and KSZ8091RNB versions in this data sheet.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII/RMII data from the MAC into a 125MHz
serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The
serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output
current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This
is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally,
the NRZ serial data is converted to MII/RMII format and provided as the input data to the MAC.
Scrambler/De-Scrambler (100Base-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
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10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of
2.5V peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te
signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones
Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8091MNX/RNB decodes a data frame. The receive clock is kept active during
idle periods between data receptions.
SQE and Jabber Function (10Base-T Only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to
test the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base-T
transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T
transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8091MNX/RNB generates all internal clocks and all external clocks for system timing from an external 25MHz
crystal, oscillator, or reference clock. For the KSZ8091RNB in RMII 50MHz clock mode, these clocks are generated from
an external 50MHz oscillator or system clock.
Auto-Negotiation
The KSZ8091MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8091MNX/RNB link partner is forced to bypass auto-negotiation, then the
KSZ8091MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8091MNX/RNB to establish a link by listening for a fixed signal protocol in the absence of the auto-
negotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (register 0h, bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is
set by register 0h, bit [8].
The auto-negotiation link-up process is shown in Figure 1.
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Figure 1. Auto-Negotiation Flow Chart
MII Interface (KSZ8091MNX only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8091MNX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
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MII Signal
Name
Direction
(with respect to PHY,
KSZ8091MNX signal)
Direction
(with respect to MAC) Description
TXC Output Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data[3:0]
TXER Input Output, or (not implemented)
Transmit Error
(KSZ8091MNX implements only the EEE function
for this pin. See Transmit Error description below for
details.)
RXC Output Input
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data[3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Carrier Sense
COL Output Input Collision Detection
Table 1. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0] and TXER.
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated
before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data[3:0] (TXD[ 3:0])
When TXEN is asserted, TXD[3:0] are the data nibbles presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the LPI
state (EEE mode).
TXD[3:0] transitions synchronously with respect to TXC.
Transmit Error (TXER)
TXER is implemented only for the EEE function.
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MNX transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to KSZ8091MNX and can be left as a no
connect.
TXER transitions synchronously with respect to TXC.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0] and RXER.
• In 10Mbps mode, RXC is recovered from the line while the carrier is active. When the line is idle or the link is
down, RXC is derived from the PHY’s reference clock.
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• In 100Mbps mode, RXC is recovered continuously from the line. If the link is down, RXC is derived from the
PHY’s reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains
asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data[3 :0] (RXD[3:0])
For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.
When RXDV is de-asserted, the PHY drives RXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the LPI
state (EEE mode).
RXD[3:0] transitions synchronously with respect to RXC.
Receive Error (RXER)
When RXDV is asserted, RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a
coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected somewhere in
the frame that is being transferred from the PHY to the MAC.
In EEE mode only, when RXDV is de-asserted, RXER is driven by the PHY to inform the MAC that the KSZ8091MNX
receive is in the LPI state.
RXER transitions synchronously with respect to RXC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on
the reception of an end-of-frame (EOF) marker.
• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-
asserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-
asserts CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
MII Signal Diagram
The KSZ8091MNX MII pin connections to the MAC are shown in Figure 2.
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Figure 2. KSZ8091MNX MII Interface
RMII Data Interface (KSZ8091RNB only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference
clock).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
RMII – 25MHz Clock Mode
The KSZ8091RNB is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 0 (default value) to select 25MHz clock mode.
RMII – 50MHz Clock Mode
The KSZ8091RNB is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:
• An external 50MHz clock source (oscillator) connected to XI (pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 1 to select 50MHz clock mode.
RMII Signal Definition
Table 2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
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RMII Signal
Name
Direction
(with respect to PHY,
KSZ8091RNB signal)
Direction
(with respect to MAC) Description
REF_CLK Output (25MHz clock mode) /
<no connect> (50MHz clock mode)
Input/
Input or <no connect>
Synchronous 50MHz reference clock for
receive, transmit, and control interface
TXEN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data[1:0]
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data[1:0]
RXER Output Input, or (not required) Receive Error
Table 2. RMII Signal Definition
Reference Clock (REF_C LK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0] and
RX_ER.
For 25MHz clock mode, the KSZ8091RNB generates and outputs the 50MHz RMII REF_CLK to the MAC at REF_CLK
(pin 19).
For 50MHz clock mode, the KSZ8091RNB takes in the 50MHz RMII REF_CLK from the MAC or system board at XI (pin
9) and leaves the REF_CLK (pin 19) as a no connect.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data[1:0] (TXD[ 1:0])
When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
TXD[1:0] transitions synchronously with respect to REF_CLK.
Carrier Sense / Receive Data Valid (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected.
This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame
through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is
considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to
REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
Receive Data[1 :0] (RXD[1:0])
For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.
When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
RXD[1:0] transitions synchronously with respect to REF_CLK.
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Receive Error (RXER)
When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for
example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected
somewhere in the frame that is being transferred from the PHY to the MAC.
RXER transitions synchronously with respect to REF_CLK.
Collision Detection (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
RMII Signal Diagram
The KSZ8091RNB RMII pin connections to the MAC for 25MHz clock mode are shown in Figure 3. The connections for
50MHz clock mode are shown in Figure 4 .
Figure 3. KSZ8091RNB RMII Interface (25MHz Clock Mode)
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Figure 4. KSZ8091RNB RMII Interface (50MHz Clock Mode)
Back-to-Back Mode – 100Mbps Copper Repeater
Two KSZ8091MNX/RNB devices can be connected back-to-back to form a 100Base-TX copper repeater.
Figure 5. KSZ8091MNX/RNB to KSZ8091MNX/RNB Back-to-Back Copper Repeater
MII Back-to-Back Mode (KSZ8091MNX only)
In MII back-to-back mode, a KSZ8091MNX interfaces with another KSZ8091MNX to provide a complete 100Mbps copper
repeater solution.
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The KSZ8091MNX devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to 110
• A common 25MHz reference clock connected to XI (pin 9) of both KSZ8091MNX devices
• MII signals connected as shown in Table 3
KSZ8091MNX (100Base-TX copper)
[Device 1] KSZ8091MNX (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
RXC 19 Output TXC 22 Input
RXDV 18 Output TXEN 23 Input
RXD3 13 Output TXD3 27 Input
RXD2 14 Output TXD2 26 Input
RXD1 15 Output TXD1 25 Input
RXD0 16 Output TXD0 24 Input
TXC 22 Input RXC 19 Output
TXEN 23 Input RXDV 18 Output
TXD3 27 Input RXD3 13 Output
TXD2 26 Input RXD2 14 Output
TXD1 25 Input RXD1 15 Output
TXD0 24 Input RXD0 16 Output
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
RMII Back-to-Back Mode (KSZ8091RNB only)
In RMII back-to-back mode, a KSZ8091RNB interfaces with another KSZ8091RNB to provide a complete 100Mbps
copper repeater solution.
The KSZ8091RNB devices are configured to RMII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to 101
• A common 50MHz reference clock connected to XI (pin 9) of both KSZ8091RNB devices
• RMII signals connected as shown in Table 4
KSZ8091RNB (100Base-TX copper)
[Device 1] KSZ8091RNB (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
CRSDV 18 Output TXEN 23 Input
RXD1 15 Output TXD1 25 Input
RXD0 16 Output TXD0 24 Input
TXEN 23 Input CRSDV 18 Output
TXD1 25 Input RXD1 15 Output
TXD0 24 Input RXD0 16 Output
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
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MII Management (MIIM) Interface
The KSZ8091MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8091MNX/RNB. An external device with MIIM capability is used to read the PHY status and/or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external
controller to communicate with one or more PHY devices.
• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for
indirect access to MMD addresses and registers. See the “Register Map” section.
As the default, the KSZ8091MNX/RNB supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter
is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8091MNX/RNB device, or write
to multiple KSZ8091MNX/RNB devices simultaneously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin
19) or software (register 16h, bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8091MNX/RNB
device.
Table 5 shows the MII management frame format for the KSZ8091MNX/RNB.
Preamble
Start of
Frame Read/Write
OP Code PHY Address
Bits [4:0] REG Address
Bits [4:0] TA Data
Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Table 5. MII Management Frame Format for the KSZ8091MNX/RNB
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8091MNX/RNB PHY register. Bits [15:8] of register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Bit [9] of register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8091MNX/RNB control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8091MNX/RNB and its link partner. This feature allows the KSZ8091MNX/RNB to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091MNX/RNB accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to register 1Fh, bit [13]. MDI and MDI-X mode is
selected by register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
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MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2 TX− 2 RX−
3 RX+ 3 TX+
6 RX− 6 TX−
Table 6. MDI/MDI-X Pin Definition
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 shows a
typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
Figure 6. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 7
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
Loopback Mode
The KSZ8091MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
Local (Digital) Loopback
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8091MNX/RNB and the
external MAC, and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data path is shown in Figure 8.
1. The MII/RMII MAC transmits frames to the KSZ8091MNX/RNB.
2. Frames are wrapped around inside the KSZ8091MNX/RNB.
3. The KSZ8091MNX/RNB transmits frames back to the MII/RMII MAC.
Figure 8. Local (Digital) Loopback
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The following programming action and register settings are used for local loopback mode.
For 10/100Mbps loopback,
Set register 0h,
• Bit [14] = 1 // Enable local loopback mode
• Bit [13] = 0/1 // Select 10Mbps/100Mbps speed
• Bit [12] = 0 // Disable auto-negotiation
• Bit [8] = 1 // Select full-duplex mode
Remote (Analog) Loopback
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive
data paths between the KSZ8091MNX/RNB and its link partner, and is supported for 100Base-TX full-duplex mode only.
The loopback data path is shown in Figure 9.
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8091MNX/RNB.
2. Frames are wrapped around inside the KSZ8091MNX/RNB.
3. The KSZ8091MNX/RNB transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.
Figure 9. Remote (Analog) Loopb ack
The following programming steps and register settings are used for remote loopback mode.
1. Set Register 0h,
• Bits [13] = 1 // Select 100Mbps speed
• Bit [12] = 0 // Disable auto-negotiation
• Bit [8] = 1 // Select full-duplex mode
Or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner.
2. Set Register 1Fh,
• Bit [2] = 1 // Enable remote loopback mode
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with register 1Fh, the
PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
NAND Tree Support
The KSZ8091MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8091MNX/RNB digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the
nested NAND gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree
input driven low
Table 7 and Table 8 list the NAND tree pin orders for KSZ8091MNX and KSZ8091RNB, respectively.
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
13 RXD3 Input
14 RXD2 Input
15 RXD1 Input
16 RXD0 Input
18 RXDV Input
19 RXC Input
20 RXER Input
21 INTRP Input
22 TXC Input
23 TXEN Input
24 TXD0 Input
25 TXD1 Input
26 TXD2 Input
27 TXD3 Input
30 LED0 Input
28 COL Input
29 CRS Output
Table 7. NAND Tree Test Pin Order for KSZ8091MNX
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Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
13 PHYAD0 Input
14 PHYAD1 Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
20 RXER Input
21 INTRP Input
22 PME_EN Input
23 TXEN Input
24 TXD0 Input
25 TXD1 Input
30 LED0 Input
31 LED1 Input
28 CONFIG0 Input
29 CONFIG1 Output
Table 8. NAND Tree Test Pin Order for KSZ8091RNB
NAND Tree I/O Testing
Use the following procedure to check for faults on the KSZ8091MNX/RNB digital I/O pin connections to the board:
1. Enable NAND tree mode using either hardware (NAND_Tree#, pin 21) or software (register 16h, bit [5]).
2. Use board logic to drive all KSZ8091MNX/RNB NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8091MNX/RNB NAND tree pin order, as follows:
a. Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to
low to indicate that the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low
to high to indicate that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin (RXD3/PHYAD0)) from high to low, and verify that the CRS/CONFIG1 pin switches
from high to low to indicate that the third pin is connected properly.
f. Continue with this sequence until all KSZ8091MNX/RNB NAND tree input pins have been toggled.
Each KSZ8091MNX/RNB NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or low-to-
high to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8091MNX/RNB input pin toggles
from high to low, the input pin has a fault.
Power Management
The KSZ8091MNX/RNB incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
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Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a ‘1’ to register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected
(no link).
In this mode, the KSZ8091MNX/RNB shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabled after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to register 18h, bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to register 10h, bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8091MNX/RNB transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091MNX/RNB and its
link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
Power-Down Mode
Power-down mode is used to power down the KSZ8091MNX/RNB device when it is not in use after power-up. It is
enabled by writing a ‘1’ to register 0h, bit [11].
In this mode, the KSZ8091MNX/RNB disables all internal functions except the MII management interface. The
KSZ8091MNX/RNB exits (disables) power-down mode after register 0h, bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow
oscillator when the KSZ8091MNX/RNB device is not in use after power-up. It is enabled by writing a ‘1’ to register 11h,
bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091MNX/RNB device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to register 11h, bit [5].
2. Disable power-down mode by writing a ‘0’ to register 0h, bit [11].
3. Initiate software reset by writing a ‘1’ to register 0h, bit [15].
Energy Efficient Ethernet (EEE)
The KSZ8091MNX implements Energy Efficient Ethernet (EEE) for the Media Independent Interface (MII) as described
per the IEEE Standard 802.3az. The Standard is defined around an EEE-compliant MAC on the host side and an EEE-
compliant Link Partner on the line side that support special signaling associated with EEE. EEE saves power by keeping
the AC signal on the copper Ethernet cable at approximately 0V peak-to-peak for as often as possible during periods of no
traffic activity, while maintaining the link-up status. This is referred to as Low Power Idle (LPI) mode or state.
Similarly, the KSZ8091RNB implements EEE for the Reduced Media Independent Interface (RMII) as described per the
IEEE Standard 802.3az for line signaling by the two differential pairs (analog side) and according to the multisource
agreement (MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). This agreement is based on the
IEEE Standard’s EEE implementation for MII (100Mbps).
During LPI mode, the copper link will respond automatically upon receiving traffic and resume normal PHY operation
immediately, without blockage of traffic or loss of packet – exiting LPI mode and returning to normal 100Mbps operating
mode. Wake-up time is <30us for 100Base-TX.
The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:
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• Transmit cable path only
• Receive cable path only
• Both transmit and receive cable paths
The KSZ8091MNX/RNB has the EEE function disabled as the power-up default setting. To enable the EEE function for
100Mbps mode, use the following programming sequence:
1. Enable 100Mbps EEE mode advertisement by writing a ‘1’ to MMD address 7h, register 3Ch, bit [1].
2. Restart auto-negotiation by writing a ‘1’ to standard register 0h, b [9].
For standard (non-EEE) 10Base-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are
used to maintain the link during the idle period when there is no traffic activity. To save more power, the
KSZ8091MNX/RNB provides the option to enable 10Base-Te mode, which saves additional power by reducing the
transmitted signal amplitude from 2.5V to 1.75V. To enable 10Base-Te mode, write a ‘1’ to standard register 13h, bit [4].
During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately
every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The refresh
transmissions and quiet periods are shown in Figure 10.
Figure 10. LPI Mode (Refresh Transmissions and Quiet Periods)
Transmit Direction Control (MAC-to-PHY)
The KSZ8091MNX enters LPI mode for the transmit direction when its attached EEE-compliant MII MAC de-asserts
TXEN, asserts TXER, and sets TXD[3:0] to 0001. The KSZ8091MNX remains in the LPI transmit state while the MAC
maintains the states of these signals. When the MAC changes any of the TXEN, TXER, or TX data signals from their LPI
state values, the KSZ8091MNX exits the LPI transmit state.
The TXC clock is not stopped, because it is sourced from the PHY and is used by the MAC for MII transmit.
Figure 11 shows the LPI transition for MII (100Mbps) transmit.
Figure 11. LPI Transition – MII (100Mbps) Transmit
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Similarly, the KSZ8091RNB enters LPI mode for the transmit direction when its attached EEE-compliant RMII MAC de-
asserts TXEN and sets TXD[1:0] to 01. The KSZ8091RNB remains in the LPI transmit state while the RMII MAC
maintains the states of these signals. When the RMII MAC changes any of the TXEN or TX data signals from their LPI
state values, the KSZ8091RNB exits the LPI transmit state.
Figure 12 shows the LPI transition for RMII (100Mbps) transmit.
Figure 12. LPI Transition – RMII (100Mbps) Transmit
Receive Direction Control (PHY-to-MAC)
The KSZ8091MNX enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/Refresh)
from its EEE-compliant link partner. It then de-asserts RXDV, asserts RXER, and drives RXD[3:0] to 0001. The
KSZ8091MNX remains in the LPI receive state while it continues to receive the refresh from its link partner, so it will
continue to maintain and drive the LPI output states for the MII receive signals to inform the attached EEE-compliant MII
MAC that it is in the LPI receive state. When the KSZ8091MNX receives a non /P/ code bit pattern (non-refresh), it exits
the LPI receive state and sets the RXDV, RXER, and RX data signals to set a normal frame or normal idle.
The KSZ8091MNX stops the RXC clock output to the MAC after nine or more RXC clock cycles have occurred in the LPI
receive state, to save more power. By default, RXC clock stoppage is enabled. It is disabled by writing a ‘0’ to MMD
address 3h, register 0h, bit [10].
Figure 13 shows the LPI transition for MII (100Mbps) receive.
RXC
RXDV
RXD[3:0]
RXER ENTER LOW
POWER STATE
EXIT LOW
POWER STATE
Figure 13. LPI Transition – MII (100Mbps) Receive
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Similarly, the KSZ8091RNB enters LPI mode for the receive direction when its attached EEE-compliant RMII MAC de-
asserts CRS_DV and sets RXD[1:0] to 01. The KSZ8091RNB remains in the LPI receive state while the RMII MAC
maintains the states of these signals. When the RMII MAC changes any of the CRS_DV or RX data signals from their LPI
state values, the KSZ8091RNB exits the LPI receive state.
Figure 14 shows the LPI transition for RMII (100Mbps) receive.
Figure 14. LPI Transition – RMII (100Mbps) Receive
Registers Associated with EEE
The following registers are provided for EEE configuration and management:
Standard register 13h - AFE Control 4 (to enable 10Base-Te mode)
MMD address 1h, register 0h - PMA/PMD Control 1 (to enable LPI)
MMD address 1h, register 1h - PMA/PMD Status 1 (for LPI status)
MMD address 3h, register 0h - EEE PCS Control 1 (to stop RXC clock for KSZ8091MNX only)
MMD address 7h, register 3Ch - EEE Advertisement
MMD address 7h, register 3Dh - EEE Link Partner Advertisement
Wake-On-LAN
Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end device,
such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ8091MNX/RNB can perform
the same WOL function if the MAC address of its associated MAC device is entered into the KSZ8091MNX/RNB PHY
registers for magic-packet detection. When the KSZ8091MNX/RNB detects the magic packet, it wakes up the host by
driving its power management event (PME) output pin low.
By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers
for the selected PME wake-up detection method.
The KSZ8091MNX/RNB provides three methods to trigger a PME wake-up:
Magic-packet detection
Customized-packet detection
Link status change detection
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Magic-Packet Detection
The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of its
associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ8091MNX/RNB asserts its PME output pin low.
The following MMD address 1Fh registers are provided for magic-packet detection:
Magic-packet detection is enabled by writing a ‘1’ to MMD address 1Fh, register 0h, bit [6]
The MAC address (for the local MAC device) is written to and stored in MMD address 1Fh, registers 19h – 1Bh
The KSZ8091MNX/RNB does not generate the magic packet. The magic packet must be provided by the external system.
Customized-Packet Detection
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ8091MNX/RNB receives the packet from its link partner, the selected bytes
for the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that
was previously written to and stored in the KSZ8091MNX/RNB PHY registers. If there is a match, the KSZ8091MNX/RNB
asserts its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used to
configure and enable each customized packet.
The following MMD registers are provided for customized-packet detection:
Each of the four customized packets is enabled via MMD address 1Fh, register 0h,
- Bit [2] // For customized packets, type 0
- Bit [3] // For customized packets, type 1
- Bit [4] // For customized packets, type 2
- Bit [5] // For customized packets, type 3
Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
- MMD address 1Fh, registers 1h – 4h // For customized packets, type 0
- MMD address 1Fh, registers 7h – Ah // For customized packets, type 1
- MMD address 1Fh, registers Dh – 10h // For customized packets, type 2
- MMD address 1Fh, registers 13h – 16h // For customized packets, type 3
32-bit expected CRCs are written to and stored in:
- MMD address 1Fh, registers 5h – 6h // For customized packets, type 0
- MMD address 1Fh, registers Bh – Ch // For customized packets, type 1
- MMD address 1Fh, registers 11h – 12h // For customized packets, type 2
- MMD address 1Fh, registers 17h – 18h // For customized packets, type 3
Link Status Change Detection
If link status change detection is enabled, the KSZ8091MNX/RNB asserts its PME output pin low whenever there is a link
status change, using the following MMD address 1Fh register bits and their enabled (1) or disabled (0) settings:
MMD address 1Fh, register 0h, bit [0] // For link-up detection
MMD address 1Fh, register 0h, bit [1] // For link-down detection
The PME output signal is available on either INTRP/PME_N2 (pin 21) or LED0/PME_N1 (pin 30), and is enabled using
standard register 16h, bit [15]. MMD address 1Fh, register 0h, bits [15:14] defines and selects the output functions for pins
21 and 30.
The PME output is active low and requires a 1k pull-up to the VDDIO supply. When asserted, the PME output is cleared
by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change).
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 41 M9999-021513-1.0
Reference Circuit for Power and Ground Connections
The KSZ8091MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 15 and Table 9 for 3.3V VDDIO.
Figure 15. KSZ8091MNX/RNB Power and Ground Connections
Power Pin Pin Number Description
VDD_1.2 2 Decouple with 2.2µF and 0.1µF capacitors to ground.
VDDA_3.3 3 Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22µF and 0.1µF capacitors to ground.
VDDIO 17 Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22µF and 0.1µF capacitors to ground.
Table 9. KSZ8091MNX/RNB Power Pin Description
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 42 M9999-021513-1.0
Typical Current/Power Consumption
Table 10 through Table 12 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O
(VDDIO) power pins and typical values for power consumption by the KSZ8091MNX/RNB device for the indicated nominal
operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator
current for the 1.2V core.
Transceiver (3.3V), Digital I/Os (3.3V)
3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
Condition mA mA mW
100Base-TX Link-up (no traffic) 34 12 152
100Base-TX Full-duplex @ 100% utilization 34 13 155
10Base-T Link-up (no traffic) 14 11 82.5
10Base-T Full-duplex @ 100% utilization 30 11 135
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic) 13 10 75.9
Power-saving mode (Reg. 1Fh, bit [10] = 1) 13 10 75.9
EDPD mode (Reg. 18h, bit [11] = 0) 10 10 66.0
EDPD mode (Reg. 18h, bit [11] = 0) and
PLL off (Reg. 10h, bit [4] = 1) 3.77 1.54 17.5
Software power-down mode (Reg. 0h, bit [11] =1) 2.59 1.51 13.5
Software power-down mode (Reg. 0h, bit [11] =1)
and slow-oscillator mode (Reg. 11h, bit [5] =1) 1.36 0.45 5.97
Table 10. Typical Current/Pow er Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Transceiver (3.3V), Digital I/Os (2.5V)
3.3V Transceiver
(VDDA_3.3) 2.5V Digital I/Os
(VDDIO) Total Chip Power
Condition mA mA mW
100Base-TX Link-up (no traffic) 34 11 140
100Base-TX Full-duplex @ 100% utilization 34 12 142
10Base-T Link-up (no traffic) 15 10 74.5
10Base-T Full-duplex @ 100% utilization 27 10 114
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic) 13 10 67.9
Power-saving mode (Reg. 1Fh, bit [10] = 1) 13 10 67.9
EDPD mode (Reg. 18h, bit [11] = 0) 11 10 61.3
EDPD mode (Reg. 18h, bit [11] = 0) and
PLL off (Reg. 10h, bit [4] = 1) 3.55 1.35 15.1
Software power-down mode (Reg. 0h, bit [11] =1) 2.29 1.34 10.9
Software power-down mode (Reg. 0h, bit [11] =1)
and slow-oscillator mode (Reg. 11h, bit [5] =1) 1.15 0.29 4.52
Table 11. Typical Current/Pow er Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 43 M9999-021513-1.0
Transceiver (3.3V), Digital I/Os (1.8V)
3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
Condition mA mA mW
100Base-TX Link-up (no traffic) 34 11 132
100Base-TX Full-duplex @ 100% utilization 34 12 134
10Base-T Link-up (no traffic) 15 9.0 65.7
10Base-T Full-duplex @ 100% utilization 27 9.0 105
EEE 100Mbps Link-up mode
(transmit and receive in LPI state with no traffic) 13 9.0 59.1
Power-saving mode (Reg. 1Fh, bit [10] = 1) 13 9.0 59.1
EDPD mode (Reg. 18h, bit [11] = 0) 11 9.0 52.5
EDPD mode (Reg. 18h, bit [11] = 0) and
PLL off (Reg. 10h, bit [4] = 1) 4.05 1.21 15.5
Software power-down mode (Reg. 0h, bit [11] =1) 2.79 1.21 11.4
Software power-down mode (Reg. 0h, bit [11] =1)
and slow-oscillator mode (Reg. 11h, bit [5] =1) 1.65 0.19 5.79
Table 12. Typical Current/Pow er Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 44 M9999-021513-1.0
Register Map
The register space within the KSZ8091MNX/RNB consists of two distinct areas.
Standard registers // Direct register access
MDIO manageable device (MMD) registers // Indirect register access
The KSZ8091MNX/RNB supports the following standard registers.
Register Number (Hex) Descrip t ion
IEEE-Defined Registers
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Link Partner Ability
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Auto-Negotiation Link Partner Next Page Ability
9h – Ch Reserved
Dh MMD Access – Control
Eh MMD Access – Register/Data
Fh Reserved
Vendor-Specific Registers
10h Digital Reserved Control
11h AFE Control 1
12h Reserved
13h AFE Control 4
14h Reserved
15h RXER Counter
16h Operation Mode Strap Override
17h Operation Mode Strap Status
18h Expanded Control
19h – 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD Cable Diagnostic
1Eh PHY Control 1
1Fh PHY Control 2
Table 13. Standard Registers Supported by KSZ8091MNX/RNB
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 45 M9999-021513-1.0
The KSZ8091MNX/RNB supports the following MMD device addresses and their associated register addresses, which
make up the indirect MMD registers.
Device Address (Hex) Register A ddress (Hex) Description
0h PMA/PMD Control 1 1h
1h PMA/PMD Status 1
3h 0h EEE PCS Control 1
3Ch EEE Advertisement 7h
3Dh EEE Link Partner Advertisement
0h Wake-On-LAN – Control
1h Wake-On-LAN – Customized Packet, Type 0, Mask 0
2h Wake-On-LAN – Customized Packet, Type 0, Mask 1
3h Wake-On-LAN – Customized Packet, Type 0, Mask 2
4h Wake-On-LAN – Customized Packet, Type 0, Mask 3
5h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
6h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
7h Wake-On-LAN – Customized Packet, Type 1, Mask 0
8h Wake-On-LAN – Customized Packet, Type 1, Mask 1
9h Wake-On-LAN – Customized Packet, Type 1, Mask 2
Ah Wake-On-LAN – Customized Packet, Type 1, Mask 3
Bh Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
Ch Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
Dh Wake-On-LAN – Customized Packet, Type 2, Mask 0
Eh Wake-On-LAN – Customized Packet, Type 2, Mask 1
Fh Wake-On-LAN – Customized Packet, Type 2, Mask 2
10h Wake-On-LAN – Customized Packet, Type 2, Mask 3
11h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
12h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
13h Wake-On-LAN – Customized Packet, Type 3, Mask 0
14h Wake-On-LAN – Customized Packet, Type 3, Mask 1
15h Wake-On-LAN – Customized Packet, Type 3, Mask 2
16h Wake-On-LAN – Customized Packet, Type 3, Mask 3
17h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
18h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
19h Wake-On-LAN – Magic Packet, MAC-DA-0
1Ah Wake-On-LAN – Magic Packet, MAC-DA-1
1Fh
1Bh Wake-On-LAN – Magic Packet, MAC-DA-2
Table 14. MMD Registers Su p po rted by KSZ8091MNX/RNB
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 46 M9999-021513-1.0
Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (registers 0h to Fh) are defined according to the IEEE
specification, while the remaining 16 registers (registers 10h to 1Fh) are defined specific to the PHY vendor.
IEEE-Defined Registers – Descriptions
Address Name Description Mode(1) Default
Register 0h – Basic Cont ro l
0.15 Reset 1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation
RW 0
0.13 Speed Select 1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
RW Set by the SPEED strapping pin
(KSZ8091RNB only).
See the “Strapping Options –
KSZ8091MNX
” section for details.
0.12 Auto-
Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, the auto-negotiation result overrides
the settings in registers 0.13 and 0.8.
RW Set by the NWAYEN strapping
pin.
See the “Strapping Options –
KSZ8091MNX
” section for details.
0.11 Power-Down 1 = Power-down mode
0 = Normal operation
If software reset (register 0.15) is used to exit
power-down mode (register 0.11 = 1), two
software reset writes (register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and re-
latches the pin strapping pin values.
RW 0
0.10 Isolate 1 = Electrical isolation of PHY from MII/RMII
0 = Normal operation
RW Set by the ISO strapping pin.
See the “Strapping Options –
KSZ8091MNX
” section for details.
0.9 Restart Auto-
Negotiation
1 = Restart auto-negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex
RW The inverse of the DUPLEX
strapping pin value.
See the “Strapping Options –
KSZ8091MNX
” section for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test
RW 0
0.6:0 Reserved Reserved RO 000_0000
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 47 M9999-021513-1.0
Address Name Description Mode(1) Default
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable
RO 0
1.14 100Base-TX
Full-Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex
RO 1
1.13 100Base-TX
Half-Duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex
RO 1
1.12 10Base-T
Full-Duplex
1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex
RO 1
1.11 10Base-T
Half-Duplex
1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex
RO 1
1.10:7 Reserved Reserved RO 000_0
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble
RO 1
1.5 Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault
RO/LH 0
1.3 Auto-
Negotiation
Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation
RO 1
1.2 Link Status 1 = Link is up
0 = Link is down
RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH 0
1.0 Extended
Capability
1 = Supports extended capability registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0022h
Register 3h – PHY Identifier 2
3.15:10 PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0001_01
3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision
Number
Four-bit manufacturer’s revision number RO Indicates silicon revision
Register 4h – Auto-Negotiatio n Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability
RW 0
4.14 Reserved Reserved RO 0
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 48 M9999-021513-1.0
Address Name Description Mode(1) Default
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault
RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause [00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100Base-T4 1 = T4 capable
0 = No T4 capability
RO 0
4.8 100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RW Set by the SPEED strapping pin
(KSZ8091RNB only).
See the “Strapping Options –
KSZ8091MNX
” section for details.
4.7 100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RW Set by the SPEED strapping pin
(KSZ8091RNB only).
See the “Strapping Options –
KSZ8091MNX
” section for details.
4.6 10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RW 1
4.5 10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RW 1
4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability
RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received
RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault
RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause [00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100Base-T4 1 = T4 capable
0 = No T4 capability
RO 0
5.8 100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RO 0
5.7 100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RO 0
5.6 10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RO 0
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 49 M9999-021513-1.0
Address Name Description Mode(1) Default
5.5 10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RO 0
5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4 Parallel
Detection Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
RO/LH 0
6.3 Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability
RO 0
6.2 Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability
RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet
RO/LH 0
6.0 Link Partner
Auto-
Negotiation
Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
RO 0
Register 7h – Auto-Negotiatio n Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page
RW 0
7.14 Reserved Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unformatted page
RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message
RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0
RO 0
7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001
Register 8h – Auto-Negotiation Link Partner Next Page Ability
8.15 Next Page 1 = Additional next pages will follow
0 = Last page
RO 0
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word
RO 0
8.13 Message Page 1 = Message page
0 = Unformatted page
RO 0
8.12 Acknowledge2 1 = Can act on the information
0 = Cannot act on the information
RO 0
8.11 Toggle 1 = Previous value of transmitted link code
word equal to logic 0
0 = Previous value of transmitted link code
word equal to logic 1
RO 0
8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 50 M9999-021513-1.0
Address Name Description Mode(1) Default
Register Dh – MMD Access – Control
D.15:14 MMD –
Operation
Mode
For the selected MMD device address (bits [4:0]
of this register), these two bits select one of the
following register or data operations and the
usage for MMD Access – Register/Data (Reg.
Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
D.4:0 MMD –
Device
Address
These five bits set the MMD device address. RW 0_0000
Register Eh – MMD Access – Register/Data
E.15:0 MMD –
Register/Data
For the selected MMD device address (Reg.
Dh, bits [4:0]),
When Reg. Dh, bits [15:14] = 00, this
register contains the read/write register
address for the MMD device address.
Otherwise, this register contains the
read/write data value for the MMD device
address and its selected register address.
See also Reg. Dh, bits [15:14], for descriptions
of post increment reads and writes of this
register for data operation.
RW 0000_0000_0000_0000
Note:
1. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
Vendor-Specific Registers – Descriptions
Address Name Description Mode(1) Default
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off 1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also register 18h, bit [11] for EDPD mode
RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
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February 2013 51 M9999-021513-1.0
Address Name Description Mode(1) Default
11.5 Slow-Oscillator
Mode Enable
Slow-oscillator mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8091MNX/RNB device is not in use after
power-up.
1 = Enable
0 = Disable
This bit automatically sets software power-down
to the analog side when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 13h – AFE Control 4
13.15:5 Reserved Reserved RW 0000_0000_000
13.4 10Base-Te
Mode
1 = EEE 10Base-Te (1.75V TX amplitude)
0 = Standard 10Base-T (2.5V TX amplitude)
RW 0
13.3:0 Reserved Reserved RW 0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h
Register 16h – Operation Mode Strap Override
16.15 PME Enable PME for Wake-on-LAN
1 = Enable
0 = Disable
This bit works in conjunction with MMD Address
1Fh, Reg. 0h, Bits [15:14] to define the output
for pins 21 and 30.
RW Set by the PME_EN strapping pin.
See the “Strapping Options –
KSZ8091MNX
” section for details.
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9 B-CAST_OFF
Override
1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast.
RW 0
16.8 Reserved Reserved RW 0
16.7 MII B-to-B
Override
1 = Override strap-in for MII back-to-back
mode (also set bit 0 of this register to ‘1’)
This bit applies only to KSZ8091MNX.
RW 0
16.6 RMII B-to-B
Override
1 = Override strap-in for RMII Back-to-Back
mode (also set bit 1 of this register to ‘1’)
This bit applies only to KSZ8091RNB.
RW 0
16.5 NAND Tree
Override
1 = Override strap-in for NAND tree mode RW 0
16.4:2 Reserved Reserved RW 0_00
16.1 RMII Override 1 = Override strap-in for RMII mode
This bit applies only to KSZ8091RNB.
RW 0
16.0 MII Override 1 = Override strap-in for MII mode
This bit applies only to KSZ8091MNX.
RW 1
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 52 M9999-021513-1.0
Address Name Description Mode(1) Default
Register 17h – Operation Mode Strap Status
17.15:13 PHYAD[2:0]
Strap-In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
RO
17.12:10 Reserved Reserved RO
17.9 B-CAST_OFF
Strap-In Status
1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast.
RO
17.8 Reserved Reserved RO
17.7 MII B-to-B
Strap-In Status
1 = Strap to MII back-to-back mode
This bit applies only to KSZ8091MNX.
RO
17.6 RMII B-to-B
Strap-In Status
1 = Strap to RMII Back-to-Back mode
This bit applies only to KSZ8091RNB.
RO
17.5 NAND Tree
Strap-In Status
1 = Strap to NAND tree mode RO
17.4:2 Reserved Reserved RO
17.1 RMII Strap-In
Status
1 = Strap to RMII mode
This bit applies only to KSZ8091RNB.
RO
17.0 MII Strap-In
Status
1 = Strap to MII mode
This bit applies only to KSZ8091MNX.
RO
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also register 10h, bit [4] for PLL off.
RW 1
18.10 100Base-TX
Latency
1 = MII output is random latency
0 = MII output is fixed latency
For both settings, all bytes of received preamble
are passed to the MII output.
This bit applies only to KSZ8091MNX.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6 10Base-T
Preamble
Restore
1 = Restore received preamble to MII output
0 = Remove all seven bytes of preamble before
sending frame (starting with SFD) to MII
output
This bit applies only to KSZ8091MNX
RW 0
18.5:0 Reserved Reserved RW 00_0001
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 53 M9999-021513-1.0
Address Name Description Mode(1) Default
Register 1Bh – Interrup t Con t rol/Status
1B.15 Jabber
Interrupt
Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
RW 0
1B.14 Receive Error
Interrupt
Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt
RW 0
1B.13 Page Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
RW 0
1B.12 Parallel Detect
Fault Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt
RW 0
1B.11 Link Partner
Acknowledge
Interrupt
Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge
interrupt
RW 0
1B.10 Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt
RW 0
1B.9 Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt
RW 0
1B.8 Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt
RW 0
1B.7 Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur
RO/SC 0
1B.6 Receive Error
Interrupt
1 = Receive error occurred
0 = Receive error did not occur
RO/SC 0
1B.5 Page Receive
Interrupt
1 = Page receive occurred
0 = Page receive did not occur
RO/SC 0
1B.4 Parallel Detect
Fault Interrupt
1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur
RO/SC 0
1B.3 Link Partner
Acknowledge
Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur
RO/SC 0
1B.2 Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur
RO/SC 0
1B.1 Remote Fault
Interrupt
1 = Remote fault occurred
0 = Remote fault did not occur
RO/SC 0
1B.0 Link-Up
Interrupt
1 = Link-up occurred
0 = Link-up did not occur
RO/SC 0
Register 1Dh – LinkMD Cable Diagnostic
1D.15 Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test
has completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the status information
is valid for read.
RW/SC 0
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Address Name Description Mode(1) Default
1D.14:13 Cable
Diagnostic
Test Result
[00] = Normal condition
[01] = Open condition has been detected in
cable
[10] = Short condition has been detected in
cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Indicator
1 = Short cable (<10 meter) has been detected
by LinkMD
RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter
Distance to fault RO 0_0000_0000
Register 1Eh – PHY Con t rol 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9 Enable Pause
(Flow Control)
1 = Flow control capable
0 = No flow control capability
RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down
RO 0
1E.7 Polarity Status 1 = Polarity is reversed
0 = Polarity is not reversed
RO
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X
State
1 = MDI-X
0 = MDI
RO
1E.4 Energy Detect
1 = Signal present on receive differential
pair
0 = No signal detected on receive differential
pair
RO 0
1E.3 PHY Isolate 1 = PHY in isolate mode
0 = PHY in normal operation
RW 0
1E.2:0 Operation
Mode
Indication
[000] = Still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = Reserved
RO 000
Register 1Fh – PHY Cont rol 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
RW 1
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 55 M9999-021513-1.0
Address Name Description Mode(1) Default
1F.14 MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM (pins 5, 4) and
Receive on TXP,TXM (pins 7, 6)
0 = MDI mode
Transmit on TXP,TXM (pins 7, 6) and
Receive on RXP,RXM (pins 5, 4)
RW 0
1F.13 Pair Swap
Disable
1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X
RW 0
1F.12 Reserved Reserved RW 0
1F.11 Force Link 1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving 1 = Enable power saving
0 = Disable power saving
RW 0
1F.9 Interrupt Level 1 = Interrupt pin active high
0 = Interrupt pin active low
RW 0
1F.8 Enable Jabber 1 = Enable jabber counter
0 = Disable jabber counter
RW 1
1F.7 RMII
Reference
Clock Select
1 = RMII 50MHz clock mode; clock input to XI
(pin 9) is 50MHz
0 = RMII 25MHz clock mode; clock input to XI
(pin 9) is 25MHz
This bit applies only to KSZ8091RNB.
RW 0
1F.6 Reserved Reserved RW 0
1F.5:4 LED Mode [00] = LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
[10], [11] = Reserved
The LED1 pin applies only to KSZ8091RNB.
RW 00
1F.3 Disable
Transmitter
1 = Disable transmitter
0 = Enable transmitter
RW 0
1F.2 Remote
Loopback
1 = Remote (analog) loopback is enabled
0 = Normal mode
RW 0
1F.1 Enable SQE
Test
1 = Enable SQE test
0 = Disable SQE test
RW 0
1F.0 Disable Data
Scrambling
1 = Disable scrambler
0 = Enable scrambler
RW 0
Note:
1. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 56 M9999-021513-1.0
MMD Registers
MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to
65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ8091MNX/RNB, however, uses
only a small fraction of the available registers. See the “Register Map” section for a list of supported MMD device
addresses and their associated register addresses.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
Standard register Dh – MMD Access – Control
Standard register Eh – MMD Access – Register/Data
Address Name Description Mode Default
Register Dh – MMD Access – Control
D.15:14 MMD –
Operation
Mode
For the selected MMD device address (bits [4:0]
of this register), these two bits select one of the
following register or data operations and the
usage for MMD Access – Register/Data (Reg.
Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
D.4:0 MMD –
Device
Address
These five bits set the MMD device address. RW 0_0000
Register Eh – MMD Access – Register/Data
E.15:0 MMD –
Register/Data
For the selected MMD device address (Reg.
Dh, bits [4:0]),
When Reg. Dh, bits [15:14] = 00, this
register contains the read/write register
address for the MMD device address.
Otherwise, this register contains the
read/write data value for the MMD device
address and its selected register address.
See also Register Dh, bits [15:14] descriptions
for post increment reads and writes of this
register for data operation.
RW 0000_0000_0000_0000
Table 15. Portal Registers (Access to Indirect MMD Registers)
Examples:
MMD Register Write
Write MMD – Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WOL.
1. Write register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write register Eh with 0000h // Select register 0h of MMD – Device Address 1Fh.
3. Write register Dh with 401Fh // Select register data for MMD – Device Address 1Fh, Register 0h.
4. Write register Eh with 0001h // Write value 0001h to MMD – Device Address 1Fh, Register 0h.
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February 2013 57 M9999-021513-1.0
MMD Register Read
Read MMD – Device Address 1Fh, Register 19h – 1Bh for the magic packet’s MAC address
1. Write register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write register Eh with 0019h // Select register 19h of MMD – Device Address 1Fh.
3. Write register Dh with 801Fh // Select register data for MMD – Device Address 1Fh, Register 19h
// with post increments
4. Read register Eh // Read data in MMD – Device Address 1Fh, Register 19h.
5. Read register Eh // Read data in MMD – Device Address 1Fh, Register 1Ah.
6. Read register Eh // Read data in MMD – Device Address 1Fh, Register 1Bh.
MMD Registers – Descriptions
Address Name Description Mode(1) Default
MMD Address 1h, Register 0h – PMA/PMD Control 1
1.0.15:13 Reserved Reserved RW 000
1.0.12 LPI enable Lower Power Idle enable RW 0
1.0.11:0 Reserved Reserved RW 0000_0000_0000
MMD Address 1h, Register 1h – PMA/PMD Status 1
1.1.15:9 Reserved Reserved RO 0000_000
1.1.8 LPI State
Entered
1 = PMA/PMD has entered LPI state
0 = PMA/PMD has not entered LPI state
RO/LH 0
1.1.7:4 Reserved Reserved RO 0000
1.1.3 LPI State
Indication
1 = PMA/PMD is currently in LPI state
0 = PMA/PMD is currently not in LPI state
RO 0
1.1.2:0 Reserved Reserved RO 000
MMD Address 3h, Register 0h – EEE PCS Control 1
3.0.15:12 Reserved Reserved RO 0000
3.0.11 Reserved Reserved RW 1
3.0.10 100Base-TX
RXC Clock
Stoppable
During receive lower-power idle mode,
1 = RXC clock is stoppable for 100Base-TX
0 = RXC clock is not stoppable for 100Base-TX
This bit applies only to KSZ8091MNX.
RW 1
3.0.9:4 Reserved Reserved RW 00_0001
3.0.3:2 Reserved Reserved RO 00
3.0.1:0 Reserved Reserved RW 00
MMD Address 7h, Register 3Ch – EEE Advertisement
7.3C.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3C.2 1000Base-T
EEE Capable
0 = 1000Mbps EEE is not supported RO 0
7.3C.1 100Base-TX
EEE Capable
1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability
This bit is set to ‘0’ as the default after power-up
or reset. Set this bit to ‘1’ to enable 100Mbps
EEE mode.
RW 0
7.3C.0 Reserved Reserved RO 0
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 58 M9999-021513-1.0
Address Name Description Mode(1) Default
MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement
7.3D.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3D.2 1000Base-T
EEE Capable
1 = 1000Mbps EEE capable
0 = No 1000Mbps EEE capability
RO 0
7.3D.1 100Base-TX
EEE Capable
1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability
RO 0
7.3D.0 Reserved Reserved RO 0
MMD Address 1Fh, Register 0h – Wake-On-LAN – Control
1F.0.15:14 PME Output
Select
These two bits work in conjunction with Reg.
16h, Bit [15] for PME enable to define the
output for pins 21 and 30.
INTRP/PME_N2 (pin 21)
00 = INTRP output
01 = PME_N2 output
10 = INTRP and PME_N2 output
11 = Reserved
LED0/PME_N1 (pin 30)
00 = PME_N1 output
01 = LED0 output
10 = LED0 output
11 = PME_N1 output
RW 00
1F.0.13:7 Reserved Reserved RO 00_0000_0
1F.0.6 Magic Packet
Detect Enable
1 = Enable magic-packet detection
0 = Disable magic-packet detection
RW 0
1F.0.5 Custom-
Packet Type 3
Detect Enable
1 = Enable custom-packet, Type 3 detection
0 = Disable custom-packet, Type 3 detection
RW 0
1F.0.4 Custom-
Packet Type 2
Detect Enable
1 = Enable custom-packet, Type 2 detection
0 = Disable custom-packet, Type 2 detection
RW 0
1F.0.3 Custom-
Packet Type 1
Detect Enable
1 = Enable custom-packet, Type 1 detection
0 = Disable custom-packet, Type 1 detection
RW 0
1F.0.2 Custom-
Packet Type 0
Detect Enable
1 = Enable custom-packet, Type 0 detection
0 = Disable custom-packet, Type 0 detection
RW 0
1F.0.1 Link-Down
Detect Enable
1 = Enable link-down detection
0 = Disable link-down detection
RW 0
1F.0.0 Link-Up Detect
Enable
1 = Enable link-up detection
0 = Disable link-up detection
RW 0
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 59 M9999-021513-1.0
Address Name Description Mode(1) Default
MMD Address 1Fh, Register 1h – W ake-On -LAN – Customized Packet, Type 0, Mask 0
MMD Address 1Fh, Register 7h – W ake-On -LAN – Customized Packet, Type 1, Mask 0
MMD Address 1Fh, Register Dh – W ake-On -LAN – Customized Packet, Type 2, Mask 0
MMD Address 1Fh, Register 13h – W ake-On-LAN – Customized Packet, Type 3, Mask 0
1F.1.15:0
1F.7.15:0
1F.D.15:0
1F.13.15:0
Custom Packet
Type X
Mask 0
This register selects the bytes in the first 16
bytes of the packet (bytes 1 thru 16) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-16
… : …
Bit [1] : byte-2
Bit [0] : byte-1
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 2h – W ake-On -LAN – Customized Packet, Type 0, Mask 1
MMD Address 1Fh, Register 8h – W ake-On -LAN – Customized Packet, Type 1, Mask 1
MMD Address 1Fh, Register Eh – Wake-On-LAN – Customized Packet, Type 2, Mask 1
MMD Address 1Fh, Register 14h – W ake-On-LAN – Customized Packet, Type 3, Mask 1
1F.2.15:0
1F.8.15:0
1F.E.15:0
1F.14.15:0
Custom Packet
Type X
Mask 1
This register selects the bytes in the second 16
bytes of the packet (bytes 17 thru 32) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-32
… : …
Bit [1] : byte-18
Bit [0] : byte-17
RW 0000_0000_0000_0000
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 60 M9999-021513-1.0
Address Name Description Mode(1) Default
MMD Address 1Fh, Register 3h – W ake-On -LAN – Customized Packet, Type 0, Mask 2
MMD Address 1Fh, Register 9h – W ake-On -LAN – Customized Packet, Type 1, Mask 2
MMD Address 1Fh, Register Fh – Wake-On-LAN – Customized Packet, Type 2, Mask 2
MMD Address 1Fh, Register 15h – W ake-On-LAN – Customized Packet, Type 3, Mask 2
1F.3.15:0
1F.9.15:0
1F.F.15:0
1F.15.15:0
Custom Packet
Type X
Mask 2
This register selects the bytes in the third 16
bytes of the packet (bytes 33 thru 48) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-48
… : …
Bit [1] : byte-34
Bit [0] : byte-33
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 4h – W ake-On -LAN – Customized Packet, Type 0, Mask 3
MMD Address 1Fh, Register Ah – Wake-On-LAN – Customized Packet, Type 1, Mask 3
MMD Address 1Fh, Register 10h – Wake-On-LAN – Customized Packet, Type 2, Mask 3
MMD Address 1Fh, Register 16h – W ake-On-LAN – Customized Packet, Type 3, Mask 3
1F.4.15:0
1F.A.15:0
1F.10.15:0
1F.16.15:0
Custom Packet
Type X
Mask 3
This register selects the bytes in the fourth 16
bytes of the packet (bytes 49 thru 64) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-64
… : …
Bit [1] : byte-50
Bit [0] : byte-49
RW 0000_0000_0000_0000
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 61 M9999-021513-1.0
Address Name Description Mode(1) Default
MMD Address 1Fh, Register 5h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 1Fh, Register Bh – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 1Fh, Register 11h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 1Fh, Register 17h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
1F.5.15:0
1F.B.15:0
1F.11.15:0
1F.17.15:0
Custom Packet
Type X
CRC 0
This register stores the lower two bytes for the
expected CRC.
Bit [15:8] = Byte 2 (CRC [15:8])
Bit [7:0] = Byte 1 (CRC [7:0])
The upper two bytes for the expected CRC are
stored in the following register.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 6h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 1Fh, Register Ch – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 1Fh, Register 12h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 1Fh, Register 18h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
1F.6.15:0
1F.C.15:0
1F.12.15:0
1F.18.15:0
Custom Packet
Type X
CRC 1
This register stores the upper two bytes for the
expected CRC.
Bit [15:8] = Byte 4 (CRC [31:24])
Bit [7:0] = Byte 3 (CRC [23:16])
The lower two bytes for the expected CRC are
stored in the previous register.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 19h – Wake-On-LAN – Magic Packet, MAC-D A-0
1F.19.15:0
Magic Packet
MAC-DA-0
This register stores the lower two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 2 (MAC Address [15:8])
Bit [7:0] = Byte 1 (MAC Address [7:0])
The upper four bytes of the destination MAC
address are stored in the following two
registers.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 1Ah – Wake-On-LAN – Magic Packet, MAC-DA-1
1F.1A.15:0
Magic Packet
MAC-DA-1
This register stores the middle two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Bit [7:0] = Byte 3 (MAC Address [23:16])
The lower two bytes and upper two bytes of the
destination MAC address are stored in the
previous and following registers, respectively.
RW 0000_0000_0000_0000
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 62 M9999-021513-1.0
Address Name Description Mode(1) Default
MMD Address 1Fh, Register 1Bh – Wake-On-LAN – Magic Packet, MAC-DA-2
1F.1B.15:0
Magic Packet
MAC-DA-2
This register stores the upper two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 6 (MAC Address [47:40])
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are stored in the previous two
registers.
RW 0000_0000_0000_0000
Note:
1. RW = Read/Write.
RO = Read only.
LH = Latch high.
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 63 M9999-021513-1.0
Absolute Maximum Ratings(1)
Supply Voltage (VIN)
(VDD_1.2) .................................................. −0.5V to +1.8V
(VDDIO, VDDA_3.3) ....................................... −0.5V to +5.0V
Input Voltage (all inputs) .............................. −0.5V to +5.0V
Output Voltage (all outputs) ......................... −0.5V to +5.0V
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (Ts) .........................–55°C to +150°C
Operating Ratings(2)
Supply Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
(VDDIO_2.5)........................................ +2.375V to +2.625V
(VDDIO_1.8)........................................ +1.710V to +1.890V
Ambient Temperature
(TA , Commercial)...................................... 0°C to +70°C
(TA , Industrial) ...................................... –40°C to +85°C
Maximum Junction Temperature (TJ max.) ................ 125°C
Thermal Resistance (θJA) .........................................34°C/W
Thermal Resistance (θJC) ...........................................6°C/W
Electrical Characteristics(3)
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(4)
IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA
IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA
IDD3_3.3V EEE (100Mbps) Mode TX and RX paths in LPI state with no traffic 23 mA
IDD4_3.3V EDPD Mode Ethernet cable disconnected (reg. 18h.11 = 0) 20 mA
IDD5_3.3V Power-Down Mode Software power-down (reg. 0h.11 = 1) 4 mA
CMOS Level Inputs
VDDIO = 3.3V 2.0 V
VDDIO = 2.5V 1.8 V
VIH Input High Voltage
VDDIO = 1.8V 1.3 V
VDDIO = 3.3V 0.8 V
VDDIO = 2.5V 0.7 V
VIL Input Low Voltage
VDDIO = 1.8V 0.5 V
|IIN| Input Current VIN = GND ~ VDDIO 10 µA
CMOS Level Outputs
VDDIO = 3.3V 2.4 V
VDDIO = 2.5V 2.0 V
VOH Output High Voltage
VDDIO = 1.8V 1.5 V
VDDIO = 3.3V 0.4 V
VDDIO = 2.5V 0.4 V
VOL Output Low Voltage
VDDIO = 1.8V 0.3 V
|Ioz| Output Tri-State Leakage 10 µA
LED Output
ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA
Notes:
2. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended periods may affect reliability.
3. The device is not guaranteed to function outside its operating rating.
4. TA = 25°C. Specification is for packaged product only.
5. Current consumption is for the single 3.3V supply KSZ8091MNX/RNB device only, and includes the transmit driver current and the 1.2V supply
voltage (VDD_1.2) that are supplied by the KSZ8091MNX/RNB.
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 64 M9999-021513-1.0
Symbol Parameter Condition Min. Typ. Max. Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
VDDIO = 3.3V 30 45 73 k
VDDIO = 2.5V 39 61 102 k
pu Internal Pull-Up Resistance
VDDIO = 1.8V 48 99 178 k
VDDIO = 3.3V 26 43 79 k
VDDIO = 2.5V 34 59 113 k
pd Internal Pull-Down Resistance
VDDIO = 1.8V 53 99 200 k
100Base-TX Transmit (me asured differentially after 1:1 t ran sformer)
VO Peak Differential Output Voltage 100 termination across differential output 0.95 1.05 V
VIMB Output Voltage Imbalance 100 termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall Time Imbalance 0 0.5 ns
Duty Cycle Distortion ±0.25 ns
Overshoot 5 %
Output Jitter Peak-to-peak 0.7 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output Voltage 100 termination across differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5 ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
Transmitter – Drive Setting
VSET Reference Voltage of ISET R(ISET) = 6.49k 0.65 V
REF_CLK Output
50MHz RMII Clock Output Jitter Peak-to-peak
(Applies only to KSZ8091RNB in RMII –
25MHz clock mode)
300 ps
100Mbps Mode – Industrial Applications Parameters
Clock Phase Delay – XI Input to
MII TXC Output
XI (25MHz clock input) to MII TXC (25MHz
clock output) delay, referenced to rising edges
of both clocks.
(Applies only to KSZ8091MNX in MII mode)
15 20 25 ns
tllr Link Loss Reaction (Indication)
Time
Link loss detected at receive differential inputs
to PHY signal indication time for each of the
following:
1. For LED mode 00 (KSZ8091RNB only),
Speed LED output changes from low
(100Mbps) to high (10Mbps, default state for
link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status
change.
4.4 µs
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
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Timing Diagrams
MII SQE Timing (10Base-T)
Figure 16. MII SQE Timing (10Base-T)
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs
tSQEP COL (SQE) pulse duration 1.0 µs
Table 16. MII SQE Timing (10Base-T) Parameters
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MII Transmit Timing (10Base-T)
Figure 17. MII Transmit Ti ming (10Base-T)
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSU1 TXD[3:0] setup to rising edge of TXC 120 ns
tSU2 TXEN setup to rising edge of TXC 120 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 600 ns
tCRS2 TXEN low to CRS de-asserted latency 1.0 µs
Table 17. MII Transmit Timing (10Base-T ) Parameters
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 67 M9999-021513-1.0
MII Receive Timing (10Base-T)
Figure 18. MII Receive Timing (10Base-T)
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXDV, RXD[3:0], RXER) output
delay from rising edge of RXC 205 ns
tRLAT CRS to (RXDV, RXD[3:0]) latency 7.2 µs
Table 18. MII Receive Timing (10Base-T) Parameters
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 68 M9999-021513-1.0
MII Transmit Timing (100Base-TX)
Figure 19. MII Transmit Ti ming (100Base-TX)
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 40 ns
tWL TXC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edge of TXC 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 72 ns
tCRS2 TXEN low to CRS de-asserted latency 72 ns
Table 19. MII Transmit Timing (100Base-TX) Parameter s
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 69 M9999-021513-1.0
MII Receive Timing (100Base-TX)
Figure 20. MII Receive Timing (100Base- TX)
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXDV, RXD[3:0], RXER) output
delay from rising edge of RXC 25 ns
tRLAT CRS to (RXDV, RXD[3:0] latency 170 ns
Table 20. MII Receive Timing (100Base-TX) Parameters
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 70 M9999-021513-1.0
RMII Timing
Figure 21. RMII Timing – Data Received from RMII
Figure 22. RMII Timing – Data Input to RMII
Timing Parameter Description Min. Typ. Max. Unit
tCYC Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tOD Output delay 7 10 13 ns
Table 21. RMII Timing Parameters – KSZ8091RNB (25MHz input to XI pin, 50MHz output from REF_CLK pin)
Timing Parameter Description Min. Typ. Max. Unit
tCYC Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tOD Output delay 8 11 13 ns
Table 22. RMII Timing Parameters – KSZ8091RNB (50MHz input to XI pin)
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 71 M9999-021513-1.0
Auto-Negotiation Timing
Figure 23. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter Description Min. Typ. Max. Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/Data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/data pulses per
FLP burst 17 33
Table 23. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 72 M9999-021513-1.0
MDC/MDIO Timing
Figure 24. MDC/MDIO Timing
Timing Parameter Description Min. Typ. Max. Unit
tP MDC period 400 ns
tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 5 ns
Table 24. MDC/MDIO Timing Parameters
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 73 M9999-021513-1.0
Power-Up/Reset Timing
The KSZ8091MNX/RNB reset timing requirement is summarized in Figure 25 and Table 25.
Figure 25. Pow er-Up/Reset Ti min g
Parameter Description Min. Max. Units
tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms
tCS Configuration setup time 5 ns
tCH Configuration hold time 5 ns
tRC Reset to strap-in pin output 6 ns
Table 25. Power-Up/Reset Timing Parameters
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
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Reset Circuit
Figure 26 shows a reset circuit recommended for powering up the KSZ8091MNX/RNB if reset is triggered by the power
supply.
KSZ8091MNX/RNB
VDDIO
D1
D1: 1N4148
R 10K
C 10uF
RST#
Figure 26. Recommended Reset Circuit
Figure 27 shows a reset circuit recommended for applications where reset is driven by another device (for example, the
CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8091MNX/RNB
device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.
KSZ8091MNX/RNB CPU/FPGA
VDDIO
C 10uF
R 10K
RST_OUT_N
D1
D2
D1, D2: 1N4148
RST#
Figure 27. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 75 M9999-021513-1.0
Reference Circuits – LED Strap-In Pins
The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/PME_N1/NWAYEN strapping pins are
shown in Figure 28 for 3.3V and 2.5V VDDIO.
Figure 28. Reference Circuits for LED Strapping Pins
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
SPEED and NWAYEN strapping pins are functional with a 4.7k pull-up to 1.8V VDDIO or float for a value of ‘1’, and with
a 1.0k pull-down to ground for a value of ‘0’.
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Reference Clock – Connection and S election
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091MNX/RNB.
For the KSZ8091MNX in all operating modes and for the KSZ8091RNB in RMII – 25MHz Clock Mode, the reference clock
is 25 MHz. The reference clock connections to XI (pin 9) and XO (pin 8), and the reference clock selection criteria, are
provided in Figure 29 and Table 26.
Figure 29. 25MHz Crystal/Oscillator Reference Clock Connection
Characteristics Value Units
Frequency 25 MHz
Frequency tolerance (max.) ±50 ppm
Table 26. 25MHz Crystal / Reference Clock Selection Criteria
For the KSZ8091RNB in RMII – 50MHz clock mode, the reference clock is 50MHz. The reference clock connections to XI
(pin 9), and the reference clock selection criteria are provided in Figure 30 and Table 27.
Figure 30. 50MHz Oscillator Reference Clock Connection
Characteristics Value Units
Frequency 50 MHz
Frequency tolerance (max) ±50 ppm
Table 27. 50MHz Oscillator / Reference Clock Selection Criteria
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
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Magnetic – Connection and Sele ction
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8091MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8091MNX/RNB side should not be connected to any
power supply source on the board; instead, the center tap pins should be separated from one another and connected
through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage
is different between transmitting and receiving differential pairs.
Figure 31 shows the typical magnetic interface circuit for the KSZ8091MNX/RNB.
1
2
3
7
8
4
5
6
4 x 75
1000pF/2kV
RJ-45
CONNECTOR
CHASSIS GROUND
(2 x 0.1µF)
TXP
TXM
RXP
RXM
KSZ8091MNX-RNB
SIGNAL GROUND
Figure 31. Typical Magnetic Interface Circuit
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
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Table 28 lists recommended magnetic characteristics.
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (min.) 350µH 100mV, 100kHz, 8mA
Insertion loss (typ.) –1.1dB 100kHz to 100MHz
HIPOT (min.) 1500Vrms
Table 28. Magnetics Selection Criteria
Table 29 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that
can be used with the KSZ8091MNX/RNB.
Manufacturer Part Number Temperature
Range Magnetic +
RJ-45
Bel Fuse S558-5999-U7 0°C to 70°C No
Bel Fuse SI-46001-F 0°C to 70°C Yes
Bel Fuse SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70°C No
Pulse H1260 0°C to 70°C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C to 70°C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70°C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
Table 29. Compatible Single-Port 10/100 Mag netics
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 79 M9999-021513-1.0
Recommended Land Pattern
Figure 32. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN
Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum
thermal performance.
Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 0.87 x
0.87mm in size, 1.07mm pitch.
Micrel, Inc. KSZ8091MNX/KSZ8091RNB
February 2013 80 M9999-021513-1.0
Package Information(1)
32-Pin (5mm x 5mm) QFN
Note:
1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. (Micrel note body)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
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specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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