M62376GP - Renesas Technology / Hitachi Semiconductor

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 1 of 10

M62376GP

8-bit 12ch D/A Converter IC Built-in 12-bit I/O Expander REJ03D0881-0300

Rev.3.00

Mar 25, 2008

Description

The M62376GP is a semiconductor IC that adopts a CMOS structure having 12 channels of 8-bit D/A convert er and 12-

bit I/O expander. The IC has achieved a wide operation range of 2.7 to 5.5 V in power voltage.

Data is easily available via 3-wire combination system serial input of SI, CLK and EN. The IC also provides an SO pin

enabling cascade connection. It provides 8 pins that share D/A converter and I/O ports that can be arbitrarily switched

with serial input data.

Features

• Supply voltage: 2.7 to 5.5 V

• Adopts 4 special ports for each of DAC and I/O and 8 ports that share DAC output and I/O

• Each port can be set by serial data for input/output status

• Built-in power-on reset where D/A output is set to "L" in the initial status and I/O goes to high -impedance when

power is turned on

• Small package of 0.65 mm pitch and 24 pin

Application

Adjustment/control of industrial or home-use electronic equipment, such as VCR camera, VCR set, TV, and CRT

display.

Block Diagram

S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

......

............

23 13 14 24

GND

CLK

RESET

A12A5A4

12 15 185

...... D11/A5 ............ D4/A12 D3 D0

............

(12)

+− +− +− +−

Shift register

8-bit

latch

8-bit

latch

8-bit

latch

8-bit D/A

converter

8-bit D/A

converter

8-bit D/A

converter

8-bit

latch

8-bit D/A

converter

Decoder

Clock

control

circuit

I/O select

12-bit latch

Amp. Hi-Z

8-bit latch

Output data 8-bit latch Output data 4-bit latch

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 2 of 10

Pin Arrangement

205

196

187

178

169

1510

D6/A10

GND

A2 RESET

A3 EN

A4 SO

D11/A5 SI

D10/A6 CLK

D9/A7 D0

D8/A8 D1

D7/A9 D2

1411

1312D4/A12 V

D5/A11 V

M62376GP

(Top view)

Outline: PLSP0024JA-A (24P2E-A)

Pin Description

Pin No. Pin Name Function

20 SI Serial data input pin. Enters serial data of 16-bit in length.

21 SO Outputs data from 16-bit shift register that reads serial data or parallel data.

19 CLK Shift clock input pin. At the rise of shift clock, input signal from the SI pin is entered into

the 16-bit shift register.

22 EN Entry of low level into the EN pin starts to read data. Putting 16-bit data at high level after

input loads the input data to a specified register.

1 A1

2 A2

3 A3

4 A4

Special output pin for 8-bit D/A converter (DAC)

5 D11/A5

6 D10/A6

7 D9/A7

8 D8/A8

9 D7/A9

10 D6/A10

11 D5/A11

12 D4/A12

Pin that shares I/O and DAC output. Settings can be selected with serial data. D4 to D11

are connected to the VDD power supply.

18 D0

17 D1

16 D2

15 D3

Digital input output pin.

14 VCC Digital block power supply pin.

24 GND GND pin

13 VDD Power supply pin in analog block and reference voltage input pin on the upper side of D/A

converter

23 RESET RESET pin

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

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Block Diagram for Explanation of Terminals

CLK S15S14S13S12S11S10S9S8S7S6S5S4S3S2S1S0

Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0

EN EN

.........

...

............

112 15 16 17 184 5

CLK

RESET

A1 A4

...... D11/A5 ............ D4/A12 D3 D2 D1 D0

(12)

(8)

[1110]

[0000]

[1111]

[1101]

(8)

(4)

(8)

A12A5A4A1

13 14 24

GND

+− +− +− +−

Shift register

8-bit

latch

8-bit D/A

converter

8-bit

latch

8-bit D/A

converter

Power ON

RESET

8-bit

latch

8-bit D/A

converter

8-bit

latch

8-bit D/A

converter

8-bit

latch

Level

shift

Level shift

Decoder (12) Decoder (4)

Clock

control

circuit

-bit

latch

(11010000)

(A5-A12 Hi-Z)

Latch Latch

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Digital supply voltage VCC –0.3 to +7.0 V

Analog supply

(D/A converter upper reference voltage) VDD –0.3 to + 7.0 V

Input voltage VIN –0.3 to VCC + 0.3 V VCC supply side pin

Output voltage Vout –0.3 to VCC + 0.3 V VCC supply side pin

Input voltage VIN –0.3 to VDD + 0.3 V VDD supply side pin

Output voltage Vout –0.3 to VDD + 0.3 V VDD supply side pin

Power dissipation Pd 200 mW

Operating temperature Topr –20 to +85 °C

Storage temperature Tstg –40 to +125 °C

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 4 of 10

Electrical Characteristics

Item Symbol Ratings Unit Conditions

Digital supply voltage VCC 2.7 to 5.5 V

Analog supply

(D/A converter upper reference voltage) VDD 2.7 to 5.5 V VDD ≥ VCC

Input pin voltage (VCC part) VIN 0 to VCC V EN, SI, D0 to D3

Output pin voltage (VCC part) VOUT 0 to VCC V SO, D0 to D3

Input pin voltage (VDD part) VIN 0 to VDD V RESET, D4/A12 to D11/A5

Output pin voltage (VDD part) VOUT 0 to VDD V A1 to A4, D4/A12 to D11/A5

(VCC = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.)

Limits

Item Symbol

Min Typ Max

Unit Conditions

Supply voltage VCC 2.7 3.0 5.5 V

Supply current ICC — 0.2 2.5 mA CLK = 1 MHz operation,

VCC = 3 V, IAO = 0 µA

Input leak current IILK –10 — 10 µA VIN = 0 to VCC

Input low voltage VIL — — 0.2 VCC V

Input high voltage VIH 0.5 VCC — — V

Output low voltage VOL — — 0.4 V IOL = 2.5 mA

Output high voltage VOH V

CC – 0.4 — — V IOH = –400 µA

Forward threshold voltage

(EN, CLK) VT+ — — 0.5 VCC V

Backward threshold voltage

(EN, CLK) VT– 0.2 VCC — — V

(VDD = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.)

Limits

Item Symbol

Min Typ Max

Unit Conditions

Supply voltage VDD 2.7 3.0 5.5 V

Input leak current IILK –10 — 10 µA VIN = 0 to VDD

Input low voltage VIL — — 0.2 VDD V

Input high voltage VIH 0.5 VDD — — V

Output low voltage VOL — — 0.4 V IOL = 2.5 mA

Output high voltage VOH V

DD – 0.4 — — V IOH = –400 µA

Note: For circuit current of VDD, see the analog block.

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 5 of 10

(VDD (VrefU) = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.)

Limits

Item Symbol

Min Typ Max

Unit Conditions

Dissipation current IDD — 1.5 3.5 mA VrefU = 3 V input data condition:

When maximum current of R-2R

rudder is supplied

D/A converter upper

reference voltage range VDD

(VrefU) 2.7 — 5.5 V

In the setup range of reference

voltage, all values are not taken

with output. Values to be taken

depend on the item of buffer

amplifier output voltage range.

0.1 — VDD – 0.1 V IAO = ±100 µA

Buffer amplifier output

voltage range VAO 0.2 — VDD – 0.2 V IAO = +500 µA

–200 µA

Buffer amplifier output

drive range IAO –0.3 — 1 mA Upper saturation voltage = 0.4 V

Lower saturation voltage = 0.4 V

Differential nonlinearity

error SDL –1.0 — 1.0 LSB

Nonlinearity error SL –1.5 — 1.5 LSB

Zero code error SZERO –2 — 2 LSB

Full scale error SFULL –2 — 2 LSB

VDD = 2.700 V (VrefU)

Without load (IAO = +0 µA)

Output capacitive load CO — — 10 µF

Buffer amplifier output

impedance RO — 5 — Ω

AC Characteristics

(VCC, VDD = 2.7 to 5.5 V, Ta = –20 to +85°C, unless otherwise noted.)

Limits

Item Symbol

Min Typ Max

Unit Conditions

Clock low pulse width tCKL 200 — — ns

Clock high pulse width tCKH 200 — — ns

Clock rise time tCR — — 200 ns

Clock fall time tCF — — 200 ns

Data setup time tDCH 30 — — ns

Data hold time tCHD 60 — — ns

Clock (EN) setup time tCLH 100 — — ns

EN setup time tCHL 200 — — ns

EN high hold time tENH 200 — — ns

Serial data output delay time tSO — 200 350 ns CL = 100 pF

Parallel data output delay

time tDO — 400 600 ns CL = 100 pF

D/A output setting time tLDD — — 100 µs CL ≤ 100 pF, VAO: 0.1 ↔ 2.6 V

Until output takes ±2 LSB of the

final value.

Input OutputDUT

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 6 of 10

Timing Chart

CLK

D0 to D11 input

D0 to D11 output

SO output

A0 to A11 output

CLH

CKL

DCH

CHD

LDD

DCH

CHD

ENH

CHL

CKH

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 7 of 10

Data Structure

Serial data

MSB LSB

S14S15 S12S13 S10S11 S8S9 S6S7 S4S5 S2S3 S0S1

Data for DAC and I/O expander Address data

Address Data

S3 S2 S1 S0 Setup

0 0 0 0 (a)

0 0 0 1 A1 selection

0 0 1 0 A2 selection

0 0 1 1 A3 selection

0 1 0 0 A4 selection

0 1 0 1 A5 selection

0 1 1 0 A6 selection

0 1 1 1 A7 selection

1 0 0 0 A8 selection

1 0 0 1 A9 selection

1 0 1 0 A10 selection

1 0 1 1 A11 selection

1 1 0 0 A12 selection

1 1 0 1 I/O expander (serial → parallel conversion)

1 1 1 0 I/O expander (parallel → serial conversion)

1 1 1 1 I/O expander status setup

• I/O expander (serial → parallel conversion)

Outputs data on S4 to S15 to pins D0 to D11.

S3 S2 S1 S0

1 1 0 1

• I/O expander (parallel → serial conversion)

Writes data on D0 to D11 pins into S4 to S15.

When next data communication is provided, outputs data sequentially from SO pin at the rise of the shift clock

(CLK). S3 S2 S1 S0

1 1 1 0

• I/O expander status setup register

Sets input/output pin of I/O expanders.

Data: "0" = Input mode (Hi-Z status), "1" = Output mode

S3 S2 S1 S0

1 1 1 1

S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4

D11

Data

Pin D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 8 of 10

DAC Data

S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4*Analog output voltage (Reference

voltage on the low er side = 0.0 V fixed)

0 0 0 0 0 0 0 0 X X X 0 (VDD / 256) × 1 [V] (1 LSB)

0 0 0 0 0 0 0 1 X X X 0 (VDD / 256) × 2 [V] (2 LSB)

0 0 0 0 0 0 1 0 X X X 0 (VDD / 256) × 3 [V] (3 LSB)

: : : : : : : : : : : : :

1 1 1 1 1 1 1 0 X X X 0 (VDD / 256) × 255 [V] (255 LSB)

1 1 1 1 1 1 1 1 X X X 0 VDD [V] (256 LSB)

X X X X X X X X X X X 1

High-impedance

(I/O expander selected)

Note: X: Don’t care

Only A5 to A12 outputs are available for DAC output by S4 and Hi-Z conversion.

(a) Command to set DAC output to High-impedance (DACHiZ command)

S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Analog output voltage

X X X X X X X X 1 1 0 1 0 0 0 0

Sets D/A output of A5 to

A12 to High-impedance.

(b) Initial status just after power is turned on:

Low level output from A1 to A4 (set to 00h)

D4/A12 to D11/A5: DAC output of high-impedance (Hi-Z), I/O of input mode (Hi-Z)

D0 to D3: input mode (Hi-Z)

Note: To change the status of pins D4/A12 to D11/A5, switch both analog and digital after setup of high-impedance.

Timing Chart (Model)

.....

S15 S0 S1 S2 S3 S12 S13 S14 S15

H-Z

n-1 n-1 n n n n n n n

S12 S13 S14 S15

n-1 n-1 n-1

S0 S1 S2 S3

n-1 n-1 n-1 n-1

S15

n-2

H-Z

S15

n-2

S15

n-3

H-Z

CLK

.....

Parallel input

(

→

Serial output)

D0 to

D11

(Serial input

→

)

Parallel output

D0 to

D11

A1 to

A12

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 9 of 10

Application Example

5D11/A5

6D10/A6

7 D9/A7

8D8/A8

9D7/A9

10 D6/A10

11 D5/A11

12 D4/A12

16D2

RESET

21SO

CLK

13 14

GND

(*)

4MCU

I/O

Logic IC

comparator

DAC output

Adjustment pins

for analog IC

DAC output

Adjustment pins

for analog IC

I/O

Logic IC

comparator

Shared pins for

DAC and I/O

Note: The RESET pin is directly connected with the power pin to use power-on reset. However, when

forced reset is done from outside, the capacitance (0.1 to 10 µF) should be connected between

RESET pin and ground to remove noise due to installation of line, etc.

Precaution for Use

This IC has two power supply pins and a ground pin. Superimposition of these pins with ripple and spike noise may

cause reduction of conversion accuracy and occurrence of malfunction. Be sure to insert a capacitor between each

power supply and the GND pin to stabilize D/A converting operation.

The output buffer amplifier of this IC has strong characteristics against capacitive load. Accordingly, when the

capacitance (10 µF Max) is connected between output and ground to remove jitter and noise due to installation of

output line, no problem may occur in operation of DAC. However, notice that the removal results in lengthening the

settling time.

This IC also provides power-on reset function. To assure the resetting operation, power supply should be turned on in

the order of timing shown in the diagram below.

Order: 1. VCC → 2. VDD

Voltage

Time t

Figure 1 Order for Power-on

M62376GP

REJ03D0881-0300 Rev.3.00 Mar 25, 2008

Page 10 of 10

Package Dimensions

0.770.53

y0.10

e0.65

0° 10°

L0.3 0.5 0.7

0 0.1 0.2

A1.45

7.4 7.6 7.8

A21.15

E5.5 5.6 5.7

D7.7 7.8 7.9

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.13 0.15 0.2

P-LSSOP24-5.6x7.8-0.65 0.1g

MASS[Typ.]

24P2E-APLSP0024JA-A

RENESAS CodeJEITA Package Code Previous Code

bp0.17 0.22 0.32

24 13

1Index mark

Detail F

INCLUDE TRIM OFFSET.

DIMENSION "*3" DOES NOT

NOTE)

DO NOT INCLUDE MOLD FLASH.

DIMENSIONS "*1" AND "*2"1.

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