25E D mn 790457 ooodeL? 9 mm ON CHIP SYSTEMS [4-050] CEM 3330/ 3335 EECTROMUSK, SPECIALTIES 110 Highland-Ave.- Los Gatos Ca. 95090, USA Tel. (408) 395-3350 Dual Voltage Controlled Amplifier The CEM 3330 and GEM 3335 are dual, high performance, voltage controlled amplifiers intended for electronic musical instrument and professional - audio applications, For the 3330, each amplifier includes complete circuitry for simul: tarieous linear and exponential control of gain, In addition, the operating point of the amplifiers may be set anywhere fram Glass ~ B to Class A, allowing the user - to optimize those parameters Critical to the particular appli- ~ cation. Also featured are virtual ground summing nodes for both the signal and linear ~ control i inputs,.so that signal and control mixing may be accomplished. within the device itself. Finally, the VCA outputs are signal currents, allawing the device to be conveniently used in two-pole voltage controlled filters, as well as dual voltage controlled amplifiers. . The 3335 is the same device as the 3330 but without the linear control circuitry, and is Intended for those applications which require only the exponen: tlal control of gain, The devices include an. on-chip 6.5 volt Zenr, allowing thent. to operate off 15 volt - supplies. as well as +16, ~5 volt supplies. - CEM 3330 Circuit Block and Connection Diagram Features rar SIGNAL HESSI4 tut y @ Low Cost / @ Two Independent Voltage Contealted: Amplifiers ina Single Package vd elec 3 Bo nct SE ome ony. @ Simultaneous. Linear and = NAY : Exponential Controt Inputs Ju] easy W Wide Control Range: 12008 ue SIGHAL atte lrut? eat se a min. @ Vey Accurate Control Scates for Excallent Gain Tracking ve + stave vgcotni -| . : a Exceptionally Low Control - . Voltage. Feedthroughs -60d8: | WeveseV T - eainimurn without trim, ase . better than -80d8 with trim teVecety @. Low Distortion: Less than 0.1% @ Exceptionally Low Noises Better than -100d8 @ Cfass:B ta Class A Operation - ux tis 1 -. @ Summing Signal and Linear nF fae unt . a r Control: inputs ~ A i Srinue 1 @@ Current Outputs tor Ease of thy tax sar Tene ay yee in Voltage Controlled : . bik ole-Filters . - sicway = = A >= >= : pan . -* . LINEAR oureUr Heer sity Wy EXp LIMtAR W Can Be Used'in VCO and VCF Control Paths Without Causing Shift Imeur INPUT oe tee M 15 Volt Supplies:2SE D M@ 6790457 OO0O2b8 O mi T-74-65-o) ON CHIP SYSTEMS CEM 3330/ CEM 3335 . as . . . Electrical Characteristics Application Hints Veo = +18V Ta 200 - Supplies Parameter ; Conditions Min Typ Max Units Since the device can withstand Exponentiel Cantral Flange 120 150 = da no suopt than 24 valts between inear Control Range - 100 130 6 its supply pins, an internal 6. Linear . . volt 10% Zener diode has been Peak Cell Current, lop Ciass@ . | 400 2600 - nA provided to. allow the chip to (input plus output) Class A 280021400 - nA run off virtually any negative Exponential Control Scale Sensitivity 28 3.0 3.2 | mvide supply voltage. Lf the negative Tempco of Exponential Control Scale +3000 +3900 +3600 | ppm supply is between -4.5 and -6.0 Tempco of Linesr Contiol Scale - 100 300 | opm valts, it may be connected - a : directly to the negative supply Exponantial Control Scale Error - 0.3 1 | dB nin (pin 5). For voltages greater Linesr Cantrol Scate Grear! O<IL<100uA - 0.3 18 % than -7.5 volts, a series current Call Current Gain Vg <0 83 1 1.2 limiting resistor must be added Current Gain Tempco Vgr0 - 2100 300 | pom between pin 5 and the supply. Log Converter Qutput tel *!nee a) 0 +5 mv Its value is calculated. as fallows: Qutput Voltage Comerence -3 - +135 v Ree = (Vee -7.2)/leg i i cl - VW % . : Untrimmed Distortion: Cana - oe $ % where leg is .Q10 for idle Trimmed Distortion? Clas 8 - 0.2 os | % currents less than 10HA, .012 Class A - 05 02 % for idle currents between 10uA - . and 50uA, and .014 for idle Untrimmed Contrat Feedthrough? Class 8 = 02 98 uA currants between S0uA and 3 4 200uA. (See Selectian of Trtimed Control Feedthrough Class 8 - Oo 08 HA Quiescent Operating Current). Class A = t _| uA Although the circuit was Output Noise Current in 20KH2z Class B = 1.2 3.5 [nARMS designed for a positive supply Bandwidth [Vg 0) ClassA - 3.5 12. [nARMS voltage of +15 volts, it may be Signal Current dandwidth4 Class 8 30 100 - KHz operated from any voltage Class A 100 350 ~ KHz between +9 and +18 volts with Sigtiat Current Slew Rate Class 8 60 150 - nAluS little effect on performance. Class A 400 750 - HAILS . . Crosstalk Between VCAs & = 10KHz -60 =70 ~- dB Basic Operation Internal Bias Current at Signal & Linear Class 8 80 178 350 nA Each of the twa voltage con: Contrat tnputs Class-A 130 300 600 nA trolied amplifiers consists af a Exponential Control Input Current lay = 100nA 4 08 1.3 BA variable gain cell and, in the case Linear Control Input Offset Voltage 7 +3 +15 mv of the 3330, a tog converter as Signal Input Offset Voltage 15 5 +5 mv well {see Block Diagrams). The Positive Supply Current: Class 8 08 : 1.3 24 mA gain cell is the Surrentin, Class A 21 27 27 mA current-out type, accepting a Por . . . : bipolar input current, ty, and ositive Supply Range 5 +9 - +18 v providing a bipolar output cur: Negative Supply Range ; . 45 = 718 Mv rent, lo, with the following relationship: Note 1: From current gains of #20d8 to -80d8. Peak call current is fess than 100uA. . Ve/V. Note 2: Output tignal is 10d8 below clipping and ts at a frequency of 1KHz. Vg =0 lo = -line GINT Vr =KT/q Note 3: Currant gain varies (com unity to maximum. atianuation (> 11008), Note 4: Peak Output Current is 200KA. where Vg is the voltage applied Note : Current limiting resistar required for negative voltages greater than: -6 valts. to the direct control input of Note 6: Class 6 ts defined at an idle current of (uA; Class A is at an idie current of 100uA. each gain cell (pin 2 and pin 15 on the 3330, pin 2 and pin 11 on. the 3335). For the 3330, the fog con- verter generates the logarithm of the linear control input current,eSE D M@ 679045? g000269 2 mIT-T4-65-9) ON CHIP SYSTEMS Aah Hen - let, (pin 7 and pin 12) while transmitting the exponential control input, Veg, (pins 6 and 14} unchanged to its output. Thea transfer function for each log converter is: leu Ve =eVy In + Voge = V, ove =-Vr Ing + Vce = Ve where Ipeg is the current sourced into the direct control input. Since ths output of the fog converter intarnally connects to the direct control input of the gain cell, the overall current gain of the gain cell is given by: Tou. -Veg/v lo=-lin sje CeiVT Far proper operation, the linear contra current, ley, and refer- ence current, lace, ara positive in polarity; that is, they flow into the device. A negative input current for to, will simply shut the gain completely off, while a negative reference cur- rent should be avoided. The signal input current may, of course, be either patarity. The Block Diagrams show typical external components connections to the devices, Tha signal inputs and the linear control inputs are virtual ground summing nodes; therefore, the signal input currents and linear control currents may be ac: curately generated from their respective voltages simply with resistors terminating at these nodes, Note that these virtual ground inputs also allow multiple input valtages to be mixed (linearly. added) on-chip by merely adding more input resistors. Although the voltage com: pliance of the gain cell outputs anges from -0.3V to Veg + 1.5V, best results are obtained by feeding the outputs into virtual ground inputs. Thus, in the Black Diagrams, the output currents are converted to voltages with external op amps, Absolute Maximum Ratings or Ground Pins Voltage Between Vcc and Vee Pins Voltage Between Veg and Ground Pins Voltage Between Vee and Ground Pins Voltage Between Output and Distortion Trim Voltage Between All Other Pins and Ground Pin Current Through Any Pia Storage Temperature Range | Operating Temperature Range +24V,-0.6V. +18V,-0.5V -6.0V,40.5V +1BV,-0.5V 6,0V 40mA 55C ta +150C (=25C to +78C CEM 3335 Circuit Block and Connection Diagram SIGNAL cnt ourPuT rin g Y Ness a Aice2 3K SIGNA i INPUT [O0SuF easy REG, BIAS ADJ. SIK . a On 12 b3 a + { VG ' aA Ve o CELL tor ) aL = view | aA cetL | HESS34 SIGNAL QUTPUT Ace2 iNgt4 ai 3K 100K EXP. SIGNAL cATL. ~ INPUT INPUT *16V Rinve 6.0K Ree 0SuF Gas? / Ema Re tt thosCEM 3330/CEM ase Dd me 4790457 go00270 9 mT-I4-o5-ol ON CHIP SYSTEMS 3335 i i r T T T wel CELL CURRENT Gate VARIES ~ FAOMUMITY TO MAX ATTENUATION 7 sob 4 2ef- 4 4 zr 4 = 2 ase 4 E 3 a ad 4 ooh 4 QISTOATION TRA OLY ae 4 CistoRTiON + ae INPUT TRIAE 4 he 2 : Ww (te (NG CURRERTINA CONTROL FREOTHAGUGH T 7 T 1 . 4 CECE CUAAENT Galn EQUALS UNITY 4 eh ta 2 tO 2 z o it a z <. R we 4 1 L L L L 1 L i $ Ty it 1@ im VOLE CURRENT Ua QuTeUT CUARENT SLOW AATE T Cy - E T T * T ve CELL CURRENT GAIN 4 4 CQUAE UNITY Zz = 2 ua 4 e = 3 3 ee 4 i E UMULTIFLY ay 24 3 FOR CEAM CELE CUARENTI it! a L E z toe in 3 1 EY TOLE CUAAEAT IW A PEAR OUTPUT CUARENT QtFQKE CAPPING 40 BELOW FUNDAMENTAL GUIPUT MOISE (4a) AE 160.A.R MS, 68 BELOW FUNDAMERTAL me CUEING Ct WAH2 @ CLIPPING - 8 me, lees aecOw CulstinG a, ee > ~~ s 19 i 1OLE CURRENT INA EVER HABMOAIC DISTOATION ~ Noma a fo Head BELOW CLIP $ 14 xe VOLE CURRENT IW A O00 HAANONIE DISTORTION CELL CURAENT GAIN EQUALS UNITY OW +18. 1gKH? $ 10 20 IOLE CURRENT tH a NQISE OUTPUT FIGUAE TL VCA PERFOAMANCE VS 1OLE CUARENTase D me 679045? on002e71 O mre I4-o5-d1 ON CHIP SYSTEMS Sefection of Component Values Selection of the input and output resistor values requires consideration of the preferred and maximum operating current levels of the device as well as the available ingut voltages and desired output voltage. In gen- eral, the input signal current should be made. as large as pos: sible to obtain the best signal to noisa ratio, However, for either peak inputs currents or peak output currents greater than saveral hundred microam- pares, distortion begins to in- crease significantly, until the total. cell currant (input peak current plus output peak current) exceeds the maximum value specified.in the specifica- tions for fep. At this point, clipping occurs, resulting in severe distortion, For optimum noise per- formance, it is recommended that the input resistor, Ry, be selected so. that the maximum peak input signal voltage causes % the peak call current to flow in the input: Ry * Vin max! len Note that the input could handle up to GdB more current, but the cell current gain would have to be reduced so signifi- cantly to prevent clipping, that the signal to naise ratio would actually be degraded. (Output noise increases roughly by the square root of an increase in cell current gain). If more than one signal is being summed in the input, then the totaf of all peak input currents should be no greater than % Icp. Next, the output resistor, Reg, is selected $o that the desired maximum for the peak output valtage before Clipping is produced with the maximum input signal. Thus, Re = Vo Max/% lop Note that the cell current gain for these conditions is unity, but the vaftage gain for the circuit is Re/Ry and may be greater ' or less than unity. Note alsa. that the current gain may be made greater than unity for inputs less than Vin MAx Although R; and Re have bean selected using maximum input and output conditions, the device should nominally Operate at least 6 to 20 dB below these maximum levels (corresponding ta 100A or less input and output currents} for best distortion performance. ~ With the values of Ry and Rp selected, the maximum linear contra} current, to_, and most negative exponential control voltage, Veg. (VG in the case of the 9335), are selected to give the maximum desired voltage gain in accordance to tha follow- ing equations: , Ay aaz0 # Re tou, Veer Ry Ire or Re _-V6/v. A ~e GIVTt V 9335 * 7 @ The maximum gain is only limited by either the total cell current exceeding Icp, or exces: sive noise and OC output shift with cell current gains much greater than unity (>+40dB}), For greatest. linear scale accuracy, the maximum value of lot should be restricted to 1QQuA or less, although currents up to 300uA can be used with lncreasing error. For best distor- tion performance, the reference current, Inger, should also be set between SQuA and 200uA; it may be generated simply with a resistor to Veg. The linear control input resistor. Rex, is thus selected so that the maxi- mum available linear contrat voltage produces the desired maximum value for fou. Finally, the selected value of ineg together with lou max determines the most negative value of Vcg required to gen- erate the maximum voltage gain. If the exponential input is not used, then it may be grounded (Veg = 0), and only the values of lo: MAx and Ineg juggled to obtain the maximum gain factor, Selection of the Quiescent Operating Current - A unique feature of the davice. is that the quiescent standby, of idle, current of the signal- carrying transistors can be set. anywhere between one and several hundrad microamperes, thus effectively allowing the user to set the operation of the gain cells anywhere between Class 8 and Class A. Since the quiescent operating point affects ali VCA characteristics, improving some while worsen- ing others, the idle current is selected ta optimize those Parameters important to the particular application. As shown in the graphs af Figure 1, increasing the idte current decreases distartion, improves slew rate, and in- creases available output cur- rent, but all at the expense of increased naise and greater control voitage feedthrough. Thus, if the application is to control the level of low fre- quency control signals where control voltage rejection is critical, then the VCA is best operated Class B. For the pro- cessing of audio signals, however, the VCA should be operated Class AB to Class A, with the best compromise between dis- tortion, noise and bandwidth, The quiescent idle current is set the same for both .VCAs by placing a resistar between the idle adjust pin (pin 8 on the 3330; pin 6 on the 3335) and the fee pin (pin 5). Figure 2 shows the idle currant versus the value of this resistor. WithIDLE CURRENT ina 4B GELOW FUNDAMENTAL at 25E D ON CHIP SYSTEMS CEM 3330/ CEM 3335 3 I. ni i Fen CLASS 8 ae eg CLASS Al t e CLASS A a OSK 1K 14K ioye IN tt FIGURE 2 LOLE CURRENT VS.10LE ADJUST REsisTOA $k 1K no resistor (Rince * %) the idle current is typically at 1A and the VCAs will operate Class B. As can ba saen from Figure 2, the idle current may vary sig- nificantly from device to device for any given value of Riote, due to the 25% tolerance of the T ~T T T T T a TKHE curring | nee N\ \ i. \ 4 @10a8 BELOWS, CLIPEING N\ a 4 \ . . ' L t 5 1.28 so G08 (OLE CURRENT IK GA FIGUAE 9. SECOND HARMONIC OISTOATION, UNTARIMMED internal resistors. In most cases, this idle current tolerance is acceptable because the VCA Parameters will vary to a much lesser extent. However, the idle current may be set more pre- cisely by measuring the idle currant and adjusting the value of Ripce with a trim pot untit the desired value is obtained, The idle current is measured by measuring the output current with no signal input and at a current gain of unity while putting roughly -0.5 to -1.5 volt on the distortion trim pin. (pins 3 and 17 on the 3330, pins 3 and 13 on the 3335). Trimming of the Second Harmonic Distortion When operating the VCAs less than Class A, internal transistor mismatches will cause the gain during the positive portian of the input signal to differ from that during the negative portion, thus introducing even harmonic distortion {predominantly second}, tn Figure 3 is shown 3 graph of typical untrimmed second harmonic distortion (distortion trim pins connected to ground) versus the idle currnt. This distortion may be acceptable in some applications, but will have to be trimmed out in others, Trimming is accomplished by adjusting the voltage on the distortion trim pins (pins 3 and 17 on the 3330, pins 3 and 13 on the 3335) somewhere between 10mV, as shown in Figure 4. The even harmonic distortion may be trimmed to near mini- mum with the following simple procedure: The signal input is alternately switched between ground, a positive voltage source (such as a battery) and a nega- tive voltage source of the exact same magnitude (best accom: plished by simply reversing the leads to the positive voltage source}. The value of the voltage source is selected to be equal to ME 679045? ooo0a72 2 mT. 7U-05-o] the peak signal level at which it is desired to trim the distortion. The output voltage is measured ta four digits with a OVM for each of the three input condi- tions, arid the trim adjusted o that the output voltage change is the same going from the grounded to positive input as it is going fram the grounded to negative input, Althaugh the second harmonic may. be trimmed out to better than 80d8 at almost any gain setting and input signat level, it is best to perform the trimming at a Current gain of zero and input signal fevel around 10d8 below the clipping point. This. procedure will yield, in general, the best distortion performance at all input levels and gain Sattings except at the very highest (last 10 to 6dB before clipping at the output). And since in the case of the music and speech signals, the fast 19 to 20dB should be reserved for headraom, this result is acceptable, As most of the odd order harmonic distortion is due to crossover distortion, there is no way to trim it out; it may be reduced only by increasing the idle current. Optimizing the Bandwidth As can be seen from the Block Diagrams, the log converters are stabilized with a series 1K re- sistor and .01uF capacitor com- pensation network from the linear control input to ground, while each of the gain cells may be compensated with a .O05uF capacitor from the com- Pensation pins {pins 9 and 11 on the 3330, pins 7 and 9 on the 3335) to ground. This gain cell compensation is good for low frequency control applica- tions, but may result in inade- quate large signal bandwidth for quality audio applications. Figure 5 shows an improved compensation technique forese D Me 79045? 0000273 4 mE T-TY4-05-0| ON CHIP SYSTEMS greater bandwidths and slew rate: By placing a series 1K resistor and .OtuF capacitor network from the signal input to ground, the .QO5uF com: ~ pansation capacitors may be reduced to 150 pF, resulting in the bandwidths and slew rate shown in Figure 1. Control Inputs As was discussed earlier, the linear control input resistor, Rez, should be selected so that the linear control current reaches a maximum of 50zA to 200uA, This fevel is low enough so as Not to cause significant contrat scale non-linearity, but high nough to swamp out the effects of the internal input bias current. Since the actual current controlling the lingar gain is the input contral current minus this bias current, the input control voltage at which the gain becomes zera is given by: Vero * le Ret tVos This cut-off point may. be increased by injecting a small constant negative current into the control input, or decreased by injecting a small positive current into the input. As the scale sensitivity of the exponential control inputs on both the 3330 and 3335 are T8mV/-6d8, an attenuation network will in most cases by required, An increasing positive control voltage decreases the gain. The basic gain cell is fully temperature compensated. The only first order temperature effect is the exponential controt factor tempco (1/Vz). This effect may be substantially reduced by using a #3300ppm tampco resistor (Tel Labs Q81) for Regs, shown in the Black Diagrams. If only the linear control input ts to be used, then the exparientiat-input is grounded and no temperature compensa- tion is necessary, To use the 3330 for exponen- tial gain control only, the entire log converter may be bypassed, reducing the number of external components and potential errors introduced by the fog converter. This is accomplished by simply- leaving the linear and exponential control inputs open, and apply- ing the exponential control voltage directly to the igee pin (which is also the direct input, Vg, to the gain cell} as shown in Figure 6. The scale sensitivity is the same as that of the exponen- tial input to the log converter, and therefore requires the same considerations as discussed above, For best distortion per- formance, it is recommended that the impedance at both the distortion adjust inputs and direct contral inputs (3330 or 3335) be kept below several hundred ohms, . Trimming of the Control Vaitage Feedthrough The shift in the quiescent OC output voltage. as the gain is changed is due to several factors. One cause is the internal bias current at the signal current input, being only of concern at idle currents fess than 10uA, The ather cause is the same. po- tential imbalance between the two signal processing halves which also is responsible for even order harmonic distortion, Thus, there. are two methads for minimizing the control voltaga feedthrough: One is to inject an adjustable OG current into the signal current input pin, as shown in Figure 7. The range of this current should be roughly equal to plus and minus. the idle current. (For idle currents less than Sy, it is not necessary that this current be adjustable to negative values.} The best tech- nique for adjusting this trim for +tS + 1002 15 100K: x A. O090.090 0. 4 Ww 15V CEM 3338 #15V- 1 4 teak -16V ou og FIGURE 4; DISTOATION TRIM maximum control voltage rejec- tion is to simply set the gain ta maximum and adjust the pot for zero DC quiescent output current. (The OC output current at zero gain is always zero.) The other method for mini- mizing control voltage feed- through is ta balance the two circuit halves by adjusting the second harmonic distortion trim discussed abave. This method, although usually reducing the distortion below that of the un- trimmed value, will not adjust SIGNAL lPuT SIGNAL (HPUT SINSI4 LATCH-UP PREVENTION oLooEs. FIGURE 5: GAIN CELL COMPENSATION COA LARGER BANOWIOTHese D ON Mm 6790457? Go00e74 & CHIP SYSTEMS MT-4-05-0 cel LEAVE 10682 OPEN / oO tt oo exe. 15 1 #2 CNTL.. ) CEM 3330 cs 7 / OUI wep TE LEAVE 1K} pees OPEN 10602 FIGURE 6: BYPASSING THE LOG CONVERTERS SIGHAL INPUT otSV 140K iy ring. ; LATEH-UP aD CEM 9330 PREVENTION t aloves 0 100K By ROVE * iige sv SIGNAL tHeUT FIGURE 7. CONTAOL REJECTION TRIM the distortion to its. potential minimum, Conversely, mini- mizing the distortion with this trim does not necessarily minimize. the control voltage feedthrough, (At high vatues of idle current, it may even increase it.) The technique for using this trim to maximize the control rejection is the same as before: the pot is adjusted: for zero OC current output at maximum gain, - At idle currents less than 10uA, it is recommended that tha input trim of Figure 7 be used rather than the distortion trim, as the distortion trim tends to increase the distortion above. the untrimmed value when feedthrough has been. minimized, At higher idle currents, however, it is recommended that the dis- tortion trim be used to minimize feedthrough, since it will afso tend to reduce distortion below the untrimmed value. In fact, this is a good method for improving (but not necessarily optimizing) both distortion and control rejection with only a single trim. Far absolute best control voltage rejection, where the distortion is not as.critical as control rejection, it is recam- mended that both the input current adjust of Figure 7 and the distortion trim be simul- taneously adjusted to produce minimum feedthrough. Coverad by U.S. Patent 4,004,141. Curtis Electromusic Specraities (CES) assumes ng responsibility for use of any circurtry described. No citeurt licenses are tmphed, GES rasecves the fight, at any time without natice, to ehange said Gircurtry. Printed U S.A. 2 1980 8 Shown in Figure 1 are typical values of control feedthrough versus idle current. for un+ trimmed, trimmed with tha in- put current adjust only, trimmed with the distortion adjust only, and trimmed with the input adjust after the distortion has been trimmed for minimum. For best overall VCA per- formance at any idle current, where both distortion and feed- through are important, it is tecammended that the second harmonic distortion is first trimmed for minimum, and then the control voltage feedthraugh trimmed with the technique of Figure 7, Layout Considerations (n the usual case where the out- Puts connect to the summing inputs of op amps, these output traces should be kept short to prevent their high impedance from picking up extraneous signals. Since capacitance greater than SOpF at the idle adjust pin may cause high frequency oscillation, care should be exercised in the layout to minimize stray capacitance at this pin. CRS CURTIS ELECTROMUSIC SPECIALTIES 110 Highland Ava. Los Gatos Ca. 95030, USA Tel. (408) 395-3350ME 6790457 oo0ca7s & mT~74-05-6) ese D ON CHIP SYSTEMS is wet -{_} tt 01 me | ns z ayeuasobene Joye, J950(P DIM Sumit U uopetd era AO rai aooU sR aiatt 0 e t e N 3 9 eae ae ee a | uy St e co + 01 ut Pi all Sw HeeeNsd VOA-1ENG wWreg Votestedwoy efsesseqier