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FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
Semiconductor Components Industries, LLC, 2016 Publication Order Number:
December, 2016, Rev. 1.0 FDMC86183/D
1
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Pin 1
Pin 1
G
D
S
S
S
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S
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G
D
D
D
D
FDMC86183
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 47 A, 12.8 mΩ
Features
Shielded Gate MOSFET Technology
Max rDS(on) = 12.8 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 34.6 mΩ at VGS = 6 V, ID = 8 A
50% Lower Qrr than Other MOSFET Suppliers
Lowers Switching Noise/EMI
MSL1 Robust Package Design
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MV MOSFET is produced using ON
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized to minimise on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
Applications
Primary DC-DC MOSFET
Synchronous Rectifier in DC-DC and AC-DC
Motor Drive
Solar
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 100 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C (Note 5) 47
A
-Continuous TC = 100 °C (Note 5) 29
-Continuous TA = 25 °C (Note 1a) 9.7
-Pulsed (Note 4) 189
EAS Single Pulse Avalanche Energy (Note 3) 96 mJ
PDPower Dissipation TC = 25 °C 52 W
Power Dissipation TA = 25 °C (Note 1a) 2.3
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case 2.4 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53
Device Marking Device Package Reel Size Tape Width Quantity
FDMC86183 FDMC86183 Power 33 13 ’’ 12 mm 3000 units
Power 33
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
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2
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Con ditio ns Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 63 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V 100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 90 μA 2.0 3.2 4.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 90 μA, referenced to 25 °C -8 mV/°C
rDS(on) Static Drain to Source On Re sistance VGS = 10 V, ID = 16 A 11 12.8 mΩVGS = 6 V, ID = 8 A 18 34.6
VGS = 10 V, ID = 16 A, TJ = 125 °C 18 21
gFS Forward Transconductance VDS = 5 V, ID = 16 A 20 S
Ciss Input Capacitance VDS = 50 V, VGS = 0 V,
f = 1 MHz
1080 1515 pF
Coss Output Capacitance 646 905 pF
Crss Reverse Transfer Capacitance 10 15 pF
RgGate Resistance 0.1 0.5 1.5 Ω
td(on) Turn-On Delay Time VDD = 50 V, ID = 16 A,
VGS = 10 V, RGEN = 6 Ω
11 20 ns
trRise Time 310ns
td(off) Turn-Off Delay Time 15 27 ns
tfFall Time 310ns
QgTotal Gate Charge VGS = 0 V to 10 V VDD = 50 V,
ID = 16 A
15 21 nC
QgTotal Gate Charge VGS = 0 V to 6 V 10 14 nC
Qgs Gate to Source Charge 5 nC
Qgd Gate to Drain “Miller” Charge 3.4 nC
Qoss Output Charge VDD = 50 V, VGS = 0 V 43 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 V
VGS = 0 V, IS = 16 A (Note 2) 0.9 1.3
trr Reverse Reco very Tim e IF = 8 A, di/dt = 300 A/μs22 36 ns
Qrr Reverse Recovery Charge 36 58 nC
trr Reverse Reco very Tim e IF = 8 A, di/dt = 1000 A/μs18 33 ns
Qrr Reverse Recovery Charge 79 127 nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 96 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 8 A, VDD = 100 V, VGS =10 V. 100% test at L = 0.3 mH, IAS = 18 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
53 °C/W when mounted
on a 1 in2 pad of 2 oz
copper
125 °C/W when mounted
on a minimum pad of 2 oz
copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
a. b.
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
www.onsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted.
Figure 1.
012345
0
20
40
60
80
100
VGS = 6.5 V
VGS = 5.5 V
VGS = 7 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRA IN TO SOURCE VOLTAGE (V)
On-Region Characteristics Figure 2.
0 20406080100
0
1
2
3
4
5
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, D RA IN CUR REN T (A )
VGS = 6.5 V
VGS = 7 V
VGS = 5.5 V
VGS = 10 V
Normalized On-Resistance
vs. Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID = 16 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESIST ANCE
TJ, JUNCTION TEMPERATURE (oC)
vs. Junction Temperature Figure 4.
45678910
0
10
20
30
40
50
60
TJ = 125 oC
ID = 16 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAG E (V)
rDS(on), DRAIN TO
SOURCE ON-RESIS TANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs. Gate to
Source Voltage
Figure 5. Transfer Characteristics
2345678910
0
20
40
60
80
100
TJ = 150 oC
VDS = 5 V
PULSE DURA T ION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.00.20.40.60.81.01.2
0.001
0.01
0.1
1
10
100
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs. Source Current
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
www.onsemi.com
4
Figure 7.
0 4 8 12 16 20
0
2
4
6
8
10 ID = 16 A
VDD = 75 V
VDD = 50 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 25 V
Gate Charge Characteristics Figure 8.
0.1 1 10 100
1
10
100
1000
5000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRA IN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Cap a cit a nce vs . Dr ain
to Source Voltage
Figure 9.
0.01 0.1 1 10 100
1
10
50
TJ = 100 o C
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVA LANCHE (ms)
IAS, AVALANCHE CURRENT (A)
Unc l am p ed In d uc t ive
Switching Capability Figure 10.
25 50 75 100 125 150
0
10
20
30
40
50
VGS = 6 V
RθJC = 2.4 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE T EMPERATURE (oC)
Maximum Continuous Drain
Current vs. Case Temperature
Figure 11.
0.1 1 10 100 500
0.1
1
10
100
300
10 μs
CURVE BENT TO
MEA SURED DATA
100 μs
10 ms
100 ms
1 ms
ID, DRAIN CURRENT (A)
VDS, DRA IN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.4 oC/W
TC = 25 oC
Forward Bias Safe
Operating Area Figure 12. Single Pulse Maximum
Power Dissipation
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000 SINGLE PULSE
RθJC = 2.4 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WID TH (sec)
Typical Characteristics TJ = 25 °C unless otherwise noted.
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
www.onsemi.com
5
Figure 13. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.005
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EF FE CT IVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURA T ION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 2.4 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
Typical Characteristics TJ = 25 °C unless otherwise noted.
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN08SREV1
8
1
5
4
41
8 5
LAND PATTERN
RECOMMENDATION
1 4
8 5
PKG
C
L
PKG
L
C
PKG L
C
L
C
SYM
PKG
C
L
A
B
SCALE: 2X
SEE
DETAIL A
3.40
3.20
3.40
3.20
1.95
0.65
0.37
0.27 (8X)
0.60
0.40
1.99
1.79
0.10 C A B
(0.34)
(2.27)(0.52 TYP)
0.25
0.15
0.80
0.70
0.10 C
0.08 C 0.05
0.00 C
SEATING
PLANE
2.37 MIN
(0.45)
(0.40)
(0.65)
2.15 MIN
0.70 MIN
0.42 MIN
(8X)
1.95
0.65
PIN 1
INDICATOR
(0.33) TYP
www.onsemi.com
1
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
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