2001 Microchip Technology Inc. DS00691A-page 1
MAN691
INTRODUCTION
Mechanical potentiometers are typically used to adjust
system reference levels, gain errors and offset errors.
Digital potentiometers can be used for the same func-
tions while offering the added capability of digital
adjustment control. Devices, such as Microchip’s
MCP41XXX and MCP42XXX digital potentiometer
families, can be used much like a mechanical potenti-
ometer in that they have three resistive terminals for
the single versions (MCP41010, MCP41050, and
MCP41100) and six resistiv e term inals fo r the d ual v er-
sions (MCP42010, MCP42050, and MCP42100) as
illustrated in Figure 1.
The two modes that a potenti omete r can be confi gured
in are the Rheostat mode and Voltage Divider mode.
When used in the Rheostat mode, the wiper (terminal
PW), is shorted to either the PA or PB terminal of the
device. This configuration is shown in Figure 2. When
a digital potentiometer is used in the Voltage Divider
mode (Figure 2.b) all three terminals are connected to
differing nodes in the circuit.
In both of these configurations, the digital potentiome-
ter will have a nominal resistance and temperature
coefficient error that may affect the overall application
unless precautions are taken. In this application note,
circuit ideas will be presented that use the necessary
design techniques to mitigate these errors, conse-
quently optimiz ing the performance o f the digita l poten-
tiometer.
FIGURE 1: The operation of the digital potentiometer as compared to the mechanical potentiometer is functionally
the sam e. The adjus tment o f the di git al potenti omete r is do ne with a seria l code to the d evic e. Altho ugh the mech anica l
potentiometer provides simplicity, the digital potentiometer provides flexibility and reliability.
Author: Bonnie C. Baker,
Microchip Technology Inc.
RDAC1
SCK SOSI
Decode
Logic
16-bit Shift Register
PA0PB0
RDAC2
Data Register 1
PA1PB1PW1
CS
RS
SHDN
D7 D0
Data Register 0
D7 D0
D7 D0
Mechanical
PAPBPW
Potentiometer
Model
Digital
PAPBPW
Potentiometer
Model
PW0
Dual Digital Potentiometer
Optimizing Digital Potentiometer Circuits to Reduce
Absolu te and Temper ature Variations
AN691
DS00691A-page 2 2001 Microchip Technology Inc.
Rheostat Mode Operation and Specifications
In the Rhe ostat mode, eit her terminal PA or PB ar e con-
nected to the wiper terminal as shown in Figure 2.a. In
this mode, the output resistance is digitally adjusted
from the maximum nominal value, minus one LSB,
down to zero ohms. The nominal resistance of the ele-
ment in the Rheostat mode is calculated with the fol-
lowing for mulas:
or
where:
RAW is the resistance between pin A and pin W of
the digital potentiometer.
RAB is the nominal resistance across the entire
potentiometer, from pin A to pin B.
RBW is the resistance between pin B and pin W of
the digital potentiometer.
n is the number of digital potentiometer bits. For
the MCP4XXXX family of potentiometers, the
number of bits is eight.
Dn is the digital code in decimal form that is used
to program the digital potentiometer. With the
MCP4XXXX 8-bit digital potentiometers the pro-
grammable digital code ranges from 0 to 28 - 1 or
255.
RW is the parasitic resistance through the wiper.
As summarized in the table in Figure 2, the nominal
resistance of the digital potentiometer varies, depend-
ing on the dev ice s el ect ed. Add iti ona lly, th e part to p a r t
variation of the nominal resistance is specified to be
within a given percentage. For example, the nominal
resist ance of th e MCP4X010 is 10 kΩ ±20%. The resis-
ta nce varia tion of t hese d igit al potenti omete rs is pr ima-
rily dep endent on the process va riation of t he sheet-rho
of a dif fused p-sili con layer and the on-resist ance of the
internal switc hes.
The temperatur e var iance of t he di gital potentiometers
element is also shown in Figure 2. For instance, the
variance of the MCP41010 (10 kΩ) digital potentiome-
ter is 800 ppm/ °C (typical). With this specification, the
expected change of the total resistance of the
MCP41010 is from 10 kΩ at 25°C to 9.52 kΩ at 85°C.
FIGURE 2: The resistive elements of the digital potentiometer can be configured in (a.) the Rheostat mode or (b.) the Voltage
Divider mode. Each mode has its own set of performance specifications.
RBW
RAB DN
()
N
2
------------------------ RW
+=
RAW
RAB 2NDN
–
2N
---------------------------------------- RW
+=
a. Rheostat Mode b. Voltage Divider Mode
Device
Nominal
RAB
Resistance
(typ)
RAB Change
with
Temperature
(typ)
Nominal
Resistance
Match (typ)
RA, RB
Relative
Accuracy I NL
(typ)
Tempco
Variance
Between RA
and RB (typ)
Code to Code
Variance
DNL (typ)
MCP41010
(single) 10 K Ω ±20% 800 ppm/°C ----- ±0.25 LSB 1% ±0.25 LSB
MCP42010 (dual) 10 K Ω ±20% 800 ppm/°C 0.2% ±0.25 LSB 1% ±0.25 LSB
MCP41050
(single) 50 K Ω ±30% 800 ppm/°C ----- ±0.25 LSB 1% ±0.25 LSB
MCP42050 (dual) 50 K Ω ±30% 800 ppm/°C 0.2% ±0.25 LSB 1% ±0.25 LSB
MCP41100
(single) 100 KΩ ±30% 800 ppm/°C ----- ±0.25 LSB 1% ±0.25 LSB
MCP42100 (dual) 100 KΩ ±30% 800 ppm/°C 0.2% ±0.25 LSB 1% ±0.25 LSB
P
W
P
A
P
B
P
A
P
B
P
W
2001 Microchip Technology Inc. DS00691A-page 3
AN691
Digital Potentiometer Cir cuits Configured in th e
Rheostat Mode
The lev el of nom inal resi stive m atching th at is sh own in
Figure 2 can be acceptable for some applications.
However, if a degree of precision is desired, the dual
potentiometer can be used to an advantage in the
Rheos tat mo de. With th e dual di git al potenti ometer, the
nominal resistances between the two potentiometers
are ratio ma tched to a very small percenta ge as shown
in Figure 2. For inst ance, the matchin g of the tw o resis-
tive potentiometer elements in the MCP42010 (dual,
10 kΩ) is guaranteed to be less than ±0.2% (typ). This
close relationship between the two resistor arrays can
be us ed to a distinct advantage.
One circuit that takes advantage of the relationship
between the two potentiometers in the dual,
MCP42100 is shown in Figure 3.
FIGURE 3: The digital potentiometers in this
differential amplifier can be programmed to change
the gain o f the circui t as we ll a s en han ce the c om mo n-
mode rejection. The common-mode rejection of this
circuit is fairly immune to temperature changes.
In Figure 3, the arra ngement of the resistors aro und an
operatio nal amplifi er is call ed the dif ference a mplifier or
op amp subtractor. The DC transfer function of this cir-
cuit is equal to:
If R1/R2 is equal to R3/R4, the system gain of this circuit
equals:
The fact that R1/R2 is equal to R3/R4 simplifies the
mathematics in this system considerably. Since the
gain of both input signals are the same, the common-
mode voltage (CMV) of the two signals is conveniently
subtracted from the output results.
Ideally, CMV changes are rejected by this circuit. The
calculated common-mode rejection (CMR) error that is
attributed to resistor mismatches in this ci rcuit is equal
to:
where (% of mismatch error) is the mismatch in the
equation R1/R2 = R3/R4.
An exampl e of the impact of this error is demonstrated
with a 12-b it, 5V system, whe re the gain of the c ircuit is
100V/V, the common -mode volt age range s 0 to 5V and
the matching error is ±0.2%. Using the formula above,
the contributed error of this type of common-mode
excursion is equal to 0.2 mV. This voltage is five times
less than 1 LSB.
Adjustable gain is easily implemented by making the
discrete resistors equal (R1=R3) and changing both
potentiometers togethe r as desired. Although, any di g-
ital p otentiometer c an be used in th e R2 and R4 position
in this c ircuit, the highe r the nom inal v alue o f the dig ita l
potentiometer, the wider the adjustable gain range will
be.
In a single supply environment, a voltage reference is
used to center the output signal between ground and
the power supply. This volt age is represented in this cir-
cuit as VREF. The VREF circuit function can be imple-
mented with a precision voltage reference or with an
adjustable voltage reference circuit that uses a digital
potentiometer as shown in Figures 5, 6 and 7. The
adjust able voltag e reference designs of fer the flexibi lity
of removing offset system errors.
An alternative to the circuit shown in Figure 3 is illus-
trated in Fi gure 4. In this cir cuit configuratio n, the diff er-
ential inputs are high impedance and the output is
differential. There are three resistors used in this cir-
cuit, two of which are 1/2 of a dual potentiometer.
P
A
V
IN
-V
OUT
P
A
V
IN
+
R
1
=1 K
Ω
R
4
(1/2 of MC P42100)
R
2
(1/2 of MC P42100)
R
3
=1 K
Ω
P
B
P
B
P
W
+
-
P
W
V
REF
VOUT V1R4R1R2
+
()
R3R4
+()R1
()
------------------------------------------- V2R2
R1
-------
–VREFR3R1R2
+
()
R3R4
+()R1
()
----------------------------------------+=
VOUT V1V2
–()
R2
R1
-------
VREF
+=
CMR 100
1R1
R2
-------+
% of mismatch error
-----------------------------------------------------=
AN691
DS00691A-page 4 2001 Microchip Technology Inc.
FIGURE 4: This differential in and differential out
circuit uses two digital potentiometers in the Rheostat
mode. When the two digital potentiometers are set to
be equal, the gains on the two input signals are equal.
If R2 = R3, the transfer function of this circuit is:
This flexible gain circuit uses the matching of nominal
resistance and thermal shifts of the dual potentiometer
to an advantage.
Voltage Divider Mode: Operation and
Specifications
In the V oltage Divider mo de shown in Figure 2, all three
terminals to the potentiometer are connected to sepa-
rate nodes in the circuit. In this mode, the total resis-
tance of the device is separated into two resistors. The
first being the resistance from terminal PB to the wiper
(PW) and the second is between terminal PA to the
wiper. The relationship between these two resistors is
equal to:
where:
RB is equal to the resistance between the PB
terminal and PW terminal minus the wiper
resistance.
RA is equal to the resistance between the PA
terminal and PW terminal minus the wiper
resistance.
There is a third resistance from the digital potentiome-
ters element to the wiper terminal. This resistance is
called the wiper resistance or RW. If the wiper of the
digital potentiometer is followed by a high impedance
node, errors caused by the wiper resistance are elimi-
nated.
The absolute value of these resistances will still vary
between ±20% and ±30% (depending on the device
used), however as shown in the table in Figure 2, the
ratio between the two elements will be much lower. In
the case of the MCP4X010, the maximum mismatch
error between RB and RA is ±0.098% (DNL specifica-
tion).
The related temperature performance of these two
resistors is also lower than the absolute temperature
behavior at a typical 1 ppm/°C. Since the resistive ele-
ments of RB and RA are manufactured with the same
material on the same chip, the ratio of the thermal
changes with temperature is considerably better as
compared to the single resistive element in the Rheo-
stat mode.
Digital Potentiometer Circui ts Configured in the
Voltage Divider Mode
The digital potentiometer can be used very effectively
in a variety of circuits when it is configured in the Volt-
age Divider mode. All of the following circuits take
advantage of the resistive ratio matching of the two
resisti ve ele ments (RB and RA).
Volta ge Re fere nc e Circui ts
One fo rm of offse t voltage adjust ment is im plement ed
with a voltage reference. This type of adjustment usu-
ally compensates for all of the system offset errors in
the signal path.
In Figu re 5, a d igit al potenti omete r is used to des ign a n
adjust able volta ge referenc e. In Figure 5.a, the potent i-
ometer is placed between the positive power supply
and ground. The outpu t v oltage of the adjustable ref er-
ence is equal to:
The resolution of this reference circuit is dependent on
the number of programmable bits of the digital potenti-
ometer an d the val ue of VDD. When usi ng any of the 8-
bit digital potentiometers from Microchip and a 5V sup-
ply, the nomi nal LSB size would be 19.53 mV.
+
-
+
-
VOUT1
VIN2
VIN1
PA
R1
R2 (1/2 of a dual Digital Potentiometer)
VOUT2
PB
PW
PA
R3 (1/2 of a dua l Digital Potentiometer)
PB
PW
VOUT1 VOUT2
–()VIN1 VIN2
–()12R2
R1
-----------+
=
RBRAB Dn
()
n
2
------------=
RARAB
2nDn
–
2n
--------------------------=
VREF VDDRPOT B
–
RPOT AB–
-----------------------------------------=
2001 Microchip Technology Inc. DS00691A-page 5
AN691
FIGURE 5: A digitally adjustable reference can be
designed using the power supply across the digital
potentiometer (a). Higher accuracy can be achieved
by using additional resistors (b) in series with the
digital potentiometer.
In this circ uit, the o peratio nal a mplif ier ac ts to isola te or
buffer the digital potentiometer resistance from follow-
ing stages.
The absolute accuracy and over temperature perfor-
mance of the voltage presented to the input of the
amplifier is dependent on the matching of the digital
poten tiometer r esist ive elem ents a s well as the st abilit y
of the power supply.
As an example of the effects of the digital potentiome-
ter errors, the MCP4X010 (10 kΩ digit al poten tiometer)
would perform with an absolute accuracy less than
±0.25 LSB (typ) or ±3.9065 mV at 25°C. Over temper-
ature, the out put voltage would typically vary 1% due to
resistance matching. This translates into a typical vari-
ance over temperature (-40°C to +85°C) of 1.172 mV
or ±0.585 mV. Adding this to the error at room temper-
ature, the total possible error becomes ±4.99 mV. In
this example, it is assumed that the power supply is a
stable 5V.
If a smaller LSB size is required for an adjustable volt-
age reference that has the full dynamic range of the
power supply voltage, the circuit in Figure 6 can be
used.
FIGURE 6: Three digital potentiometers in
combin ati on w ith a du al am pl ifi er can be co nfig ure d f or
a wide dynamic range, adjustable voltage reference
that has an ideal LSB size of VDD / 2 2n, where n is the
number of digital potentiometer bits.
In this circuit, the wiper voltage of RPOT1 is buffered
with A1, a single supply, CMOS amplifier and RPOT2 is
buffered with A2. The dynam ic range of the o utput of A1
and A2 is equal to approximately (GND+50 mV) to
(VDD−1.2V). The positive output swing range is prima-
rily rest ricted by the amp lifiers maxim um input common
mode v oltage. The t heo reti cal LSB size of the vo lt ages
at V REF-A and VREF-B are equal to VDD/2n or 19.53 mV.
The voltage difference of VREF-A and VREF-B is
impressed across RPOT3. The difference of these volt-
ages are then divided again by the third digital potenti-
ometer to have an ideal LSB size equal to:
The configuration in Figure 6 provides an theoretical
output resolution of 16 bits. When VDD is equal to 5V,
the theoretical LSB size is 76.29 µV.
VREF A
–VDD RPOT B–
()
RPOT AB–
()
----------------------------------------------=
+
MCP606
VDD
RA
RB
RPOT
VREF-A
-
VDD
a.)
+
MCP606
V
DD
R
A
R
B
R
POT
V
REF
-
B
-
V
DD
R
2
R
3
b.) VREF B
–VDD RPOT B
–R3
+()
R2RPOT AB
–R3
++()
-----------------------------------------------------------------=
-
½ MCP602
V
DD
= 5V
R
A
R
B
R
POT
1
V
REF
-
A
+
R
A
R
B
-
½ MCP602
V
DD
R
A
R
B
R
POT
2
V
REF
-
B
+
V
REF
-
C
R
POT
3
A2
A1
VREF A
– and VREF B
–VDD RPOTx B–
()
RPOTx AB–
()
-------------------------------------------------=
VREF C
–VREF A
–VREF B
–
–()
RPOT3 B
–
()
RPOT3 AB
–
()
------------------------------------------------------------------------------------------------------=
VREF C
–VDD 2n
⁄()
2n
------------------------------=
VREF C
–VDD
22n
-------------=
AN691
DS00691A-page 6 2001 Microchip Technology Inc.
The value of the output of this precision adjustable ref-
erence is compromised by the absol ute matching resis-
tance and temperature coefficient of the digital
potentiometers.
In the error analysis of this circuit, it can quickly be
found that at 25°C, the nominal errors of the digital
potentiometer have the highest potential to create the
largest errors. This in shown in Table 1.
The errors of the first stage (including the amplifiers)
are d iv ide d d ow n by the second sta ge. G iv en this error
analysis, the circuit in Figure 6 is accurate to 13.3 bits
or ±0.057 mV. This anal ys is does not t ak e int o account
variations in VDD over temperature.
Another technique that can be used to design a preci-
sion adj us t ab le v oltage referenc e is sh own i n Fig ure 7.
FIGURE 7: A precision adjustable reference can be
configured using a precision reference that is not
adjustable along with a digital potentiometer. The
value of R1 is set so that the current through the
LM4040 does not go below its minimum operating
current.
In this circuit, the variability of the power supply is sta-
bilized with a precision voltage reference. Since the
digital potentiometer is configured in the Voltage
Divider m ode, the error s at the outpu t of the amplifi er is
simila r to the errors discu ssed in Figure 5. The onl y dif-
ference being that the power supply is replaced with a
precision reference. This configuration is often used
when the digital potentiometer is used as a DAC.
Offset Adjustment Cir cuits
Offset adjustment can be implemented in the analog
circuit by injecting a voltage into the signal path with a
simple volt age d ivide r or a comp let e adju st able v olt ag e
reference.
In Figures 8 and 9, a digital potentiometer is used to
change the offset errors of a simple amplifier circuit.
FIGURE 8: A high resolution offset adjust circuit is
implemented in this standard inverting amplifier
configuration with the addition of a digital
potentiometer, R3, R4 and R5.
In this circuit, the amplifier is configured in a inverting
configu rati on. The tra nsfer fun ction fo r the inpu t signa l,
VIN is equal to:
An offset voltage is injected with the same voltage
divider that was used in the circuit in Figure 5.b. The
transfer function of the offset voltage, VOFF is:
With the resistor val ues shown in the figure, the gain on
the VIN is 10V/V and the gain on VOFF is 0.1V/V. With
VDD = 5V, the LSB size of the offset adjust circuitry is
651 µV.
With this configuration, the nominal errors and over
temperature errors that are generated by the digital
potentio me ter is 10X sma ller than the errors di scus sed
in Figure 5.b.
Another method of implementing an analog offset
adjustment with a digital potentiometer is shown in
Figure 9.
Room
Temp.
Over -40°C
to 85°C
range
RPOT1
(±0.25 LSB typical error) ±0.019 mV ±0.003 mV
RPOT2
(±0.25 LSB typical error) ±0.019 mV ±0.003 mV
RPOT3
(±0.25 LSB typical error) ±0.019 mV ±0.003 mV
Total typical error
at VREF-C±0.057 mV ±0.009 mV
TABLE 1: This table shows the nominal and
temperature errors effecting adjustable voltage
reference shown in Figure 6. Calculations assume A1
and A2 are ideal amplifiers, the MCP4X010 digital
potentiometers are used and VDD = 5V. All val ues are
referred to the output, VREF-C.
VZ = 2.5V ±2.0%
LM4040-2.5
(Precision
Voltage
Reference)
+
MCP606
VDD
RA
RB
RPOT VREF
-
R
1
or
DAC
Output
+
-
VIN
VOUT
R
3
= 100 KΩ
R
4
=
MCP41010
RBRA
R
1
<10 KΩR
2
= 10 KΩ
VDD VOFF
10 KΩ
10 KΩ
MCP601
VDD
R
5
=
10 KΩ
RW
10 KΩ
VOUT V–IN R2
R1
-------
VDD
2
-------------+=
VOUT V
–OFF R2
R3
-------
=
2001 Microchip Technology Inc. DS00691A-page 7
AN691
FIGURE 9: A lower resolution offset adjust circuit
using a digital potentiometer can be used to adjust
large system offsets.
In this circuit, the gain of the signal is equal to:
And the gain of the offset adjust circuitry is equal to:
The offset adjustment circuit used in this application
has the same topology as the circuit in Figure 5.b. Con-
sequen tly, the errors due to t his con figuration is consi s-
tent with previous discussions.
Gain Adjust Amplifier Circuits
Circuit gain errors ca n compromise the analog dynamic
range of a circuit. These types of errors can be easily
calibrated out of the system digitally with the microcon-
troller, however, the analog dynamic range is never
fully utilized. Consequently, analog gain adjustments
are done where the full dynamic analog range is
needed.
An example of an amplifier circuit that has an adjust-
able positive (noninverted) gain is shown in Figure 10.
FIGURE 10: An amplifier circuit designed with an
adjustable noninverting gain.
In this circuit, the transfer function is:
The adjustable gain is implemented with the digital
potentiometer, RPOT. Digital potentiometers that have
higher nominal values are best suited for this circuit.
Highe r value re sist ances m inimize the error that is con-
tributed by the source resistance of VIN.
The maxim um gain is equ al to:
Using the values of resistors in Figure 10:
Gain (max) = (1 + 100kΩ/1kΩ) − (28 −1)/28
= 101.996V/V
At room temperature, the digital potentiometer’s DNL
error effects the circuit gain accuracy with gains that
are lower 10% of the range (assuming DNL (max) =
±0.25 LSB). This relationship is shown graphically in
Figure 11.
+
-
V
IN
V
OUT
10 K
Ω
10 K
Ω
MCP41010
R
1
<10 K
Ω
R
2
=10 K
Ω
R
B
R
A
VOUT V–IN R2
R1
-------
=
VOUT VDDRPOT B
–
1R2
R1
-------+
RPOT AB
–R2R3
++()
-----------------------------------------------------------------=
+
-
RA
RB
VIN
R
3
=100 KΩ
RPOT
1
MCP41100
VOUT
R
2
=10 KΩ
VOUT VIN
1R3
R2
-------+
RPOT1 B–
RPOT1 AB–
------------------------------------
-------------------------------------------=
Gain (max) 1 R3
R2
-------+
2n1–
2n
----------------
–
=
AN691
DS00691A-page 8 2001 Microchip Technology Inc.
FIGURE 11: For the circuit in Figure 10, the gain vs.
digital code is linear. Th e m ax im um pos si ble ga in e rror
is logarithmic, decreasing with higher digital
potentiometer codes.
In terms of temperature effects on the digital potentiom-
eter in this configuration, the changes of RA and RB
over temperature track at a rate of 800 ppm/°C (typ).
Since these elements are configured as a mathemati-
cal ratio, this error is cancelled. The variance between
the two elements over temperature is 1% (typ). This
variance will be directly translated into gain error over
temperature.
Anot her amp lifi er gain cir cui t th at u ses a di gita l po ten-
tiomete r is shown in Figure 12. In this c ircuit, the ampli-
fier circuit executes an inverting adjustable gain
function.
FIGURE 12: This amplifier circuit uses a digital
potentiometer to implement an adjustable inverting
gain.
The circuit transfer function is:
With this circuit, the gain function versus digital poten-
tiometer code is nonlinear as shown in Figure 13.
FIGURE 13: The transfer function of VOUT to VIN of
the circuit shown in Figure 12 has a nonlinear
response over the code span of the digital
potentiometer. This phenomena creates a circuit that
gains the input signal below digital potentiometer
codes of 128 and attenuates the signal with codes
above 128.
The nominal accuracy of this gain cell is minimized
bec ause the tw o s ides of th e digital po tentiome ter are
ratioed in the circ uit transfer func ti on. Any gain error at
room temp erature is due to the DNL error of the digital
potentiometer. The maximum effects of the error is
shown graphically in Figure 13.
In terms of temperature effects on the digital po tentiom-
eter in this configuration, RA and RB are configured as
a mathematical ratio in the transfer function. This can-
cels the change in the 800 ppm/°C (typ) resistive ele-
ment. The variance between the two elements over
temperature is 1% (typ). This variance will be directly
translated into gain error over temperature.
The circuits in Figure 10 and Figure 12 can be com-
bined to build an adjustable gain difference amplifier
much li ke the circ ui t sh ow n i n Fi gur e 3. Thi s c onf igu r a-
tion is shown Figure 14.
V
IN
+
-
MCP601
V
REF
R
POT
2
R
A
R
B
V
DD
VOUT VREF RPOT2 B
–
RPOT2A–
------------------------------- 1+
VIN
–RPOT2 B–
RPOT2 A
–
-------------------------------
=
VOUT VIN RPOT2 A–
R4B–
-------------------------
VREF RPOT2 A–
RPOT2 B–
-------------------------
1++=
2001 Microchip Technology Inc. DS00691A-page 9
AN691
FIGURE 14: A difference amplifier that has stable
resistor matching and temperature coefficients.
If the digital code setting for RPOT1 and RPOT2 are
equal, the transfer function for this circuit is:
The gain o f this c ircuit (VOUT/(V1-V2)) versus the digit al
potentiometer code is shown graphically in Figure 15.
FIGURE 15: The gain of circuit in Figure 14 is greater
than one with digital code settings larger than 128 and
between zero and one for digital code settings less
than 128. The gain error, due to typical DNL errors, is
less than 1% betwe en 28 and 229.
The temperature performance of this circuit is signifi-
cantly improved over the circuit shown in Figure 3
because all of the resistors in this circuit are elements
of the digital potentiometers.
Once again, the common-mode rejection (CMR) error
that is attr ibuted to resistor mi smatche s in this circui t is
equal to:
where (% of mismatch error) is the mismatch in the
equation R1/R2 = R3/R4.
CONCLUSION
The digital potentiometer has entered the market with
clear advantages over the mechanical potentiometer.
Its programmability allows to change the offset, gain
and voltage references reliably as well as on the fly.
The effects of variances of the absolute resistances
and temperature drifts can be minimized if good circuit
design tec hni ques are used.
R
A
R
B
R
POT
1
V
IN
+
V
REF
V
IN
-
R
POT
2
R
A
R
B
V
DD
+
-
MCP601
V
OUT
VOUT V1V2
–()
RPOTX B–
RXA–
--------------------------
VREF
+=
CMR 100 1R1
R2
-------+
% of mismatch error
-----------------------------------------------------=
AN691
DS00691A-page 10 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. DS00691A-page 11
AN691
“All rights reserved. Copyright © 2001, Microchip
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licenses are conveyed, implicitly or otherwise, under
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Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Embedded Contr ol
Solutions Company are registered trademarks of
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© 2001, M icr oc hip Technolo gy Inco rpo r ate d, Prin ted in
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Microchip received QS-9000 quality system
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