PAM8014
Document number: DS38114 Rev. 2 - 3
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3.2W MONO CLASS D AUDIO AMPLIFIER
Description
The PAM8014 is a 3.2W mono filter-less class-
D amplifier with high
PSRR and differential input that eliminate noise and RF rectification.
Features like greater than 90% efficiency and small PCB area make
the PAM8014 Class-
D amplifier ideal for portable applications. The
output uses a filter-less architecture mi
nimizing the number of
external
components and PCB area whilst providing a high
performance, simpl e and lower cost s ystem.
The PAM8014 features short circuit protection and thermal shutdown.
The PAM8014 is available in U-WLB1313-9 package.
Features
Ultra Low EMI, -20dB Better Than FCC Class-B @ 300MHz
High Efficienc y up to 93% @2W with a 8Ω Speaker
Shutdown Current <1μA
3.2W@10% THD Output with a 4Ω Load at 5V Supply
Demanding Few External Components
Superior Low Noise without Input
Supply Voltage from 2.5V to 5.5 V
Short Circuit Prot ection
Thermal Shutdown
Available in Space Saving U-WLB1313-9 Package
Totally Lead-Free&Fully RoHS Compliant (Notes 1& 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Pin Assignments
(Top View)
IN+ GND OUT-
VDD PVDD PGND
A1 A2 A3
B1 B2 B3
IN- SD OUT+
C1 C2 C3
U-WLB1313-9
Applications
Cellular Phones/Smart Phones
MP4/MP3
VOIP
Digital Photo Frame
Electronic Dict i onary
Portable Game Machines
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead -free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
Typical Applicat ions C ircuit
PVDD VDD
OUT+
OUT-
PGND GND
SD
IN-
IN+
Audio Input
1µ F
0.1µ F
0.1µ F
VDD
Shut Down
PAM8014
NOT RECOMMENDED FOR NEW DESIGN
USE PAM8012 or PAM8013
PAM8014
Document number: DS38114 Rev. 2 - 3
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Pin Descriptions
Pin Name
Function
A1 IN+ Positive Diff erent i al Input
GND
Ground
OUT-
Negative BTL Output
B1 VDD Power Supply
B2 PVDD Power Supply
PGND
Power Ground
IN-
Negative Differential Input
C2 EN Chip Enable
C3 OUT+ Positive BTL Output
Functional Block D iagram
+
-
PWM
Modulator
UVLO
Startup
Protection
OSC
Bias and
Vref
Gate
Drive
Gate
Drive
SC
Protect
OTP
IN+
IN-
PVDD
OUT+
OUT-
GND
VDD
PGND
EN
EN
R
IN
R
IN
R
F
R
F
Absolute Ma ximum Ratings (@TA = +25°C, unless otherwise specifi ed. )
Symbol
Parameter
Value
Unit
VDD
Supply Voltage (VDD)
6.0 V
VI
Input Voltage (IN+, IN-, EN)
-0.3 to VDD+0.3
V
TS
Storage Temperature
-65 to +150
°C
TJ Maximum Juncti on Temperat ure +150 °C
Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.)
Symbol
Parameter
Min
Max
Unit
VDD
Supply Voltage 2.5 5.5 V
TA
Operating Ambient Temperature Range
-25
+85
°C
TJ
Junction Temperature
-40
+125
°C
PAM8014
Document number: DS38114 Rev. 2 - 3
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Electrical Characteristics (@TA = +25°C , VDD = 5V, RIN = 0, Gain=18dB, RL = L(33μH)+R+L(33μH), unless otherwise specified.)
Symbol Parameter Test Conditions Min Typ Max Unit
VDD
Supply Voltage
2.5
5.5
V
PO Output Power
THD+N = 10%, f = 1kHz, R = 4Ω V
DD
= 5.0V 3.2 W
V
DD
= 3.6V 1.6
THD+N = 1%, f = 1kHz, R = 4Ω V
DD
= 5.0V
2.45
W
VDD = 3.6V
1.3
THD+N = 10%, f = 1kHz, R = 8Ω
VDD = 5.0V
1.8 W
VDD = 3.6V
0.95
THD+N = 1%, f = 1kHz, R = 8Ω
VDD = 5.0V
1.40 W
VDD = 3.6V
0.72
THD+N Total Harmonic
Distortion Plus
Noise
VDD = 5.0V, PO = 1W, R = 8Ω
f = 1kHz
0.17
%
VDD = 3.6V, PO = 0.1W, R = 8Ω 0.16
V
DD
= 5.0V, P
O
= 0.5W, R = 4Ω f = 1kH z 0.14 %
V
DD
= 3.6V, P
O
= 0.2W, R = 4Ω 0.16
PSRR Power Supply Ripple
Rejection VDD = 3.6V, Input AC-ground with
C = 1μF
f = 217Hz
-75
dB
f = 1kHz -75
Dyn Dynam ic Range V
DD
= 5V, THD = 1%, R = 8Ω f = 1kHz 95 dB
VN Output Noise Input AC-ground
No A
weighting
60 μV
A-weighting
40
η Efficiency
RL = 8Ω, THD = 10%
f = 1kHz
93
%
RL = 4Ω, THD = 10%
86
IQ
Quiescent Current
VDD = 5V
No Load 4 mA
ISD
Shutdown Current
VDD = 2.5V to 5 V
SD = 0V
1 μA
RDS(ON) Static Drain-to-Source
On-State Resistor
High Side PMOS, I = 500mA
VDD = 5 .0V
200
Low Side NMOS, I = 500mA
VDD = 5 .0V
200
fSW Switching Frequenc y VDD = 2.5V to 5.5V 250 kHz
G
v
Closed-Loop Gain V
DD
= 2.5V to 5.5V 8 V/V
RIN Input Impedance (In
Chip)
VDD = 2.5V to 5.5V 31
t
ON
Turn-on Time V
DD
= 2.5V to 5.5V 32 ms
OTP
Over Temperature
Protection
VDD = 2.5V to 5.5V +150
OTH
Over Temperature
Hysterisis
VDD = 2.5V to 5.5V +40
VOS
Output Offset Voltage
Input AC-ground, VDD = 5V
20
mV
VIH
EN Input High Voltage
VDD = 5V
1.4
V
VIL
EN Input Low Voltage
VDD = 5V
1.0
PAM8014
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Performance Characteristics (@TA = +25°C, VDD = 5V, RIN = 0, Gain = 18dB, RL = L(33μH)+R+L(33μH), unless otherwise
specified.)
THD+N vs. Output Power (VDD=5V, RL=4Ω) THD+N vs. Output Power (VDD=5V, RL=8Ω)
THD+N vs. Output Power (VDD=3.6V, RL=4Ω) THD+N vs. Output Power (VDD=3.6V, RL=8Ω)
THD+N vs. Frequency (VDD=5.0V, RL=4Ω) THD+N vs. Frequency (VDD=5.0V, RL=8Ω)
0.01
60
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20
%
1m
5
2m
5m
10m
20m
50m
100m
200m
500m
1
2
W
f=100Hz /1KHz/10KHz
Red/Blue/Pink
0.01
60
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20
%
1m
3
2m
5m
10m
20m
50m
100m
200m
500m
1
2
W
f=100Hz /1KHz/10KHz
Red/Blue/Pink
0.01
60
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20
%
1m
5
2m
5m
10m
20m
50m
100m
200m
500m
1
2
W
f=100Hz /1KHz/10KHz
Red/Blue/Pink
0.01
60
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20
%
1m
3
2m
5m
10m
20m
50m
100m
200m
500m
1
2
W
0.02
10
0.05
0.1
0.2
0.5
1
2
5
%
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
f=100Hz /1KHz/10KHz
Red/Blue/Pink
0.02
10
0.05
0.1
0.2
0.5
1
2
5
%
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
P
O
=0.5W /1W/2W
Red/Blue/Pink
P
O
=0.3W /0.5W/1W
Red/Blue/Pink
PAM8014
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Performance Characteristics (@TA = +25°C, VDD = 5V, RIN = 0, Gain = 18dB, RL = L(33μH)+R+L(33μH), unless otherwise
specified.)
PSRR vs. Frequency (VDD=5.0V, RL=4Ω) PSRR vs. Frequency (VDD=5.0V, RL=8Ω)
Frequency Response Noise Floor
Efficiency vs. Output Power (VDD=5.0V, RL=4Ω) Efficiency vs. Output Power (VDD=5.0V, RL=8Ω)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
+15
+20
+15.25
+15.5
+15.75
+16
+16.25
+16.5
+16.75
+17
+17.25
+17.5
+17.75
+18
+18.25
+18.5
+18.75
+19
+19.25
+19.5
+19.75
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
CIN=1μF
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
0
10
20
30
40
50
60
70
80
90
100
10 50 100 300 500 700 1000 1300 2000
3000
0
20
40
60
80
100
10
50
80
100
150
200
300
500
800
1000
1300
1500
1800
%
Output Power--mW
Output Power--mW
%
PAM8014
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Applic ation Information
Close Loop Gain (GV)
The close loop gain is set by the ratio of the input resistance RIN and feedback resistance RF(refer to block diagram), and the close loop gain
equation is as follow:
= 2 RF
RIN
Which RF is set at 124KΩ and RIN is 31KΩ, the GV default is 8V/V, which is 18dB.
Input Capacitors (CIN)
In the typical application, an input capacitor, CIN, is required to allow the amplifier to bias the input signal to the proper DC level for optimum
operation. I n this case, CIN and the input impedance RIN form is a high-pass filter with the corner frequency determined in the follow equation:
 =1
2ININ
It is important to consider the value of CIN as it directly affects the low frequency perform ance of the circuit. For example, when RIN is 31kΩ and
the specific ation cal ls for a flat bass response are down to 150Hz. Equation is reconfigured as followed:
IN =1
2INC
When input resistance variation is considered, the CIN is 7nF, so one would likely choos e a value of 10nF. A furt her considerat i on for t his capacitor
is the l eakage path from the i nput source through the input network CIN, RIN and feedback resistor RF to the l oad. This l eakage c urrent creates a
DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage
tantalum or ceramic c apacitor is the best choice. When polarized capac itors are used, the positive side of the capacitor should face the amplifier
input in most applications as the DC level is held at VDD/2, which is likely higher than the source DC level. Please note that it is important to
confirm the capacit or polarit y i n the application.
Decoupling Capacitor (CS)
The PAM8014 is a high-performance CMOS audio amplifier that requires adequate power supply decoupl ing to ensure the output total harmonic
distortion (T HD) as low as possible. Power supply decoupling also prevents the oscil lations causing by long lead length between the amplifi er and
the speaker.
The optimum decoupling is achieved by using two different types of capacitors that target on different types of noise on the power supply leads.
For higher frequency t ransients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1μF,
is placed as close as possible to the device VDD pin for the best operation. For filteri ng lower frequency noise signals, a large ceramic capacitor of
10μF or greater placed near the audio power amplifier is recomm ended.
How to Reduce EMI
Most applicati ons require a ferrite bead filter for EMI elimi nation shown at Figure 1. The ferrit e filter reduces EMI around 1MHz and higher. W hen
selecting a ferrite bead, choose one with high impedance at high frequenci es, but low impedance at low frequencies.
200pF
200pF
OUT+
OUT-
Ferrite Bead
Ferrite Bead
Figure 1. Ferrite Bead Filter to Reduce EMI
PAM8014
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Applic ation Information (Cont.)
Shutdown Operation
In order to reduce power cons umption while not in use, the PAM8014 contains shutdown circuit ry amplifier off when logic low is placed on the EN
pin. By switching the shutdown pin connected to GND, the PAM8014 supply current draw will be minimized in idle mode.
Under Voltage Lock-out (UVLO)
The PAM8014 incorporates circuitry designed to detect low supply voltage. When the supply voltage drops to 2.0V or below, the PAM8014 goes
into a state of shutdown, and the device comes out of its shutdown state and restore to normal function only when VDD higher than 2.2V.
Short Circuit Protectio n (SCP )
The PAM8014 has short circuit protection circuitry on the outputs to prevent the device from damage when output-to-output shorts or output-to-
GND shorts occur. When a short circuit occurs, the device immediately goes into shutdown state. Once the short is removed, the device will be
reactivated.
Over Temperature Protectio n (OTP)
Thermal protection on the PAM8014 prevents the device from damage when the internal die temperature exceeds +150°C. There is a +15°C
tolerance on t his trip point from device to device. Once the die t emperature exceeds the set point, t he device will enter the shut down state and the
outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die decreased by +40°C. This large
hysteresis will prevent motor boating sound well and the device begins norm al operati on at this point with no external system interaction.
POP and Click Circuitry
The PAM8014 cont ains circuitry to minimize turn-on and turn-off transients or “click and pops”, where turn-on refers to either power supply turn-on
or device recover from shutdown mode. When the device is turned on, the amplifiers are internally muted. An internal current sou rce r am ps up t he
internal reference voltage. The device will remain in mute mode until the reference voltage reach half supply voltage, 1/2 VDD. As soon as the
reference voltage is stable, the device will begin full operation. For the best power-off pop performance, the amplifier should be set in shutdown
mode prior to removing the power supply voltage.
Ordering Information (Note 4)
PAM8014 X X X
A: 9 Pin Z: U-WLB1313-9 R: Tape & Reel
Part Number Package
7” Tape and Reel
Quantity
Part Number Suffix
PAM8014AZR U-WLB1313-9 3000/Tape & Reel -7
Note: 4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.
Package
Packing
Pin Configuration
PAM8014
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Marking Information
PAM8014- U-WLB1313-9
Package Ou t lin e Dim en sio ns
Please see AP02001 at http://www.diodes.com/_files/datasheets/ap02001.pdf for the latest version.
U-WLB1313-9
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/_files/datasheets/ap02001.pdf for the latest version.
U-WLB1313-9
D
E
Pin #1 ID
e
9x-Ø b
A2
A
SEATING PLANE
e
A1
Da
Ea
U-WLB1313-9
Dim
Min
Max
Typ
A
0.500
0.600
0.550
A1
0.185
0.235
0.210
A2
0.315
0.365
0.340
b
0.208
0.308
0.258
D
1.240
--
--
Da
0.750
0.850
0.800
E
1.240
--
--
Ea
0.750
0.850
0.800
e
0.400 BSC
All Dimensions in mm
Dimensions
Value
(in mm)
C
0.400
C1
0.800
C2
0.800
D
0.258
BJ: Product Code
Y: Year 0~9
W: Week: A~Z : 1~26 weeks;
a~z: 27~52 weeks; z
represents 52 and 53
weeks.
C
D ( 9x)
C
C1
C2
PAM8014
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IMPORTANT NOTICE
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final and determinative f orm at released by Diodes I ncorporat ed.
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written approval of the Chief Executive Off icer of Diodes I ncorporat ed. As us ed herein:
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1. are intended to implant into the body, or
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labeling can be reasonably expected to result in si gnifi cant injury to the user.
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