1
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual 12-Bit 250Msps/
210Msps/170Msps ADCs
n Communications
n Cellular Basestations
n Software Defined Radios
n Medical Imaging
n High Definition Video
n Testing and Measurement Instruments
n 68.5dB SNR
n 90dB SFDR
n Low Power: 628mW/592mW/545mW Total
n Single 1.8V Supply
n DDR LVDS Outputs
n Easy-to-Drive 1.5VP-P Input Range
n 1.25GHz Full-Power Bandwidth S/H
n Optional Clock Duty Cycle Stabilizer
n Low Power Sleep and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit Versions
n 64-Lead (9mm × 9mm) QFN Package
The LTC
®
2157-12/LTC2156-12/LTC2155-12 are a family of
dual 250Msps/210Msps/170Msps 12-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals. They are perfect for demanding communications
applications with AC performance that includes 68.5dB
SNR and 90dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to achieve high
undersampling ratio with very low attenuation. The latency
is only six clock cycles.
DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.54LSBRMS.
The digital outputs are double data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2157-12: 32K Points 2-Tone FFT,
fIN = 71MHZ and 69MHz, 250Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G11
100 120
–20
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
DA10_11
•
•
•
DA0_1
DB10_11
•
•
•
DB0_1
CLOCK
ANALOG
INPUT
21576512 TA01
DDR
LVDS
DDR
LVDS
V
DD
OVDD
OGND
GND
CHANNEL A
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OGND
OVDD
CHANNEL B
LTC2157-12/
LTC2156-12/LTC2155-12
2
21576512fb
For more information www.linear.com/LTC2157-12
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD, OVDD ................................................ –0.3V to 2V
Analog Input Voltage
AINA/B+, AINA/B–, PAR/SER,
SENSE (Note 3) ........................ –0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC– (Note 3) ................ –0.3V to (VDD + 0.3V)
CS, SDI, SCK (Note 4) ........................... –0.3V to 3.9V
SDO (Note 4) ............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2157C, LTC2156C, LTC2155C ............ 0°C to 70°C
LTC2157I, LTC2156I, LTC2155I ............ –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
65
GND
V
DD 1
V
DD 2
GND 3
A
INA+ 4
A
INA– 5
GND 6
SENSE
7
V
REF 8
GND 9
V
CM 10
GND 11
A
INB– 12
A
INB+ 13
GND 14
V
DD 15
V
DD 16
48 OGND
47 DA2_3+
46 DA2_3–
45 DA0_1+
44 DA0_1–
43 NC
42 NC
41 CLKOUT+
40 CLKOUT–
39 DB10_11+
38 DB10_11–
37 DB8_9+
36 DB8_9–
35 DB6_7+
34 DB6_7–
33 OGND
64 VDD
63 PAR/SER
62 CS
61 SCK
60 SDI
59 SDO
58 GND
57 DA10_11+
56 DA10_11–
55 DA8_9+
54 DA8_9–
53 DA6_7+
52 DA6_7–
51 DA4_5+
50 DA4_5–
49 OVDD
VDD 17
GND 18
ENC+ 19
ENC– 20
GND 21
OF– 22
OF+ 23
NC 24
NC 25
DB0_1– 26
DB0_1+ 27
DB2_3– 28
DB2_3+ 29
DB4_5– 30
DB4_5+ 31
OVDD 32
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2157CUP-12#PBF LTC2157CUP-12#TRPBF LTC2157UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2157IUP-12#PBF LTC2157IUP-12#TRPBF LTC2157UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
LTC2156CUP-12#PBF LTC2156CUP-12#TRPBF LTC2156UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2156IUP-12#PBF LTC2156IUP-12#TRPBF LTC2156UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
LTC2155CUP-12#PBF LTC2155CUP-12#TRPBF LTC2155UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2155IUP-12#PBF LTC2155IUP-12#TRPBF LTC2155UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTC2157-12 LTC2156-12 LTC2155-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l12 12 12 Bits
Integral Linearity Error Differential Analog Input (Note 6) l–2.3 ±0.26 2.3 –2.2 ±0.30 2.2 –1.9 ±0.30 1.9 LSB
Differential Linearity Error Differential Analog Input l–0.6 ±0.16 0.8 –0.6 ±0.16 0.6 –0.6 ±0.16 0.6 LSB
Offset Error (Note 7) l–13 ±5 13 –13 ±5 13 –13 ±5 13 mV
Gain Error External Reference l–4 ±1 2.2 –4 ±1 2.2 –4 ±1 2.2 %FS
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise 0.54 0.54 0.54 LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1.5 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) lVCM – 20mV VCM VCM + 20mV V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l1.200 1.250 1.300 V
IIN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l–1 1 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–1 1 µA
IIN3 SENSE Input Leakage Current 1.2V < SENSE < 1.3V l–1 1 µA
tAP Sample-and-Hold Acquisition Delay Time 1 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 75 dB
BW-3B Full-Power Bandwidth 1250 MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2157-12 LTC2156-12 LTC2155-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 15MHz Input
70MHz Input
140MHz Input
l
66.9
68.5
68.4
68.0
67.3
68.5
68.3
67.9
67.4
68.5
68.3
67.8
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
15MHz Input
70MHz Input
140MHz Input
l
71
90.6
88
80
74
90.1
89
81
75
90
88
80
dBFS
dBFS
dBFS
Spurious Free Dynamic Range
4th Harmonic or Higher
15MHz Input
70MHz Input
140MHz Input
l
81
98
95
85
82
98
95
87
83
98
95
88
dBFS
dBFS
dBFS
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
15MHz Input
70MHz Input
140MHz Input
l
66.1
68.4
68.3
67.7
66.7
68.4
68.3
67.7
66.8
68.4
68.3
67.7
dBFS
dBFS
dBFS
Crosstalk Crosstalk Between Channels Up to 315MHz Input –95 –95 –95 dB
LTC2157-12/
LTC2156-12/LTC2155-12
4
21576512fb
For more information www.linear.com/LTC2157-12
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.435 • VDD – 18mV 0.435 • VDD 0.435 • VDD + 18mV V
VCM Output Temperature Drift ±37 ppm/°C
VCM Output Resistance –1mA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±30 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
VID Differential Input Voltage (Note 8) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)
l
1.1
1.2
1.5
V
V
RIN Input Resistance (See Figure 2) 10 kΩ
CIN Input Capacitance (Note 8) 2 pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 3.6V l–10 10 µA
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance (Note 8) 4 pF
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2157-12 LTC2156-12 LTC2155-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
VDD Analog Supply Voltage (Note 9) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 9) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current l309 345 291 320 266 295 mA
IOVDD Digital Supply Current 1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
40
68
46
76
38
66
45
75
37
65
42
74
mA
mA
PDISS Power Dissipation 1.75mA LVDS Mode
3.5mA LVDS Mode
l
l
628
679
704
758
592
643
657
711
545
596
607
665
mW
mW
PSLEEP Sleep Mode Power Clock Disabled
Clocked at fS(MAX)
<5
<5
<5
<5
<5
<5
mW
mW
PNAP Nap Mode Power Clocked at fS(MAX) 181 168 154 mW
5
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
mV
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2157-12 LTC2156-12 LTC2155-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 9) l10 250 10 210 10 170 MHz
tLENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.9
1.5
2
2
50
50
2.26
1.5
2.38
2.38
50
50
2.79
1.5
2.94
2.94
50
50
ns
ns
tHENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
1.9
1.5
2
2
50
50
2.26
1.5
2.38
2.38
50
50
2.79
1.5
2.94
2.94
50
50
ns
ns
DIGITAL DATA OUTPUTS
SYMBOL PARAMETER CONDITIONS
LTC215X-12
MIN TYP MAX UNITS
tDENC to Data Delay CL = 5pF (Note 8) l1.7 2 2.3 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1.3 1.6 2 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0.3 0.4 0.55 ns
Pipeline Latency 6 6 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode
Readback Mode CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
tSCS to SCK Set-Up Time l5 ns
tHSCK to CS Hold Time l5 ns
tDS SDI Set-Up Time l5 ns
tDH SDI Hold Time l5 ns
tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l125 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 250MHz (LTC2157),
210MHz (LTC2156), or 170MHz (LTC2155), differential ENC+/ENC– = 2V
P-P
sine wave, input range = 1.5V
P-P
with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
LTC2157-12/
LTC2156-12/LTC2155-12
6
21576512fb
For more information www.linear.com/LTC2157-12
TIMING DIAGRAMS
Double-Data Rate Output Timing, All Outputs Are Differential LVDS
tH
tC
tD
tL
OF_AN-6 OF_BN-6 OF_AN-5 OF_BN-5 OF_AN-4 OF_BN-4
t
SKEW
DA0N-6 DA1N-6 DA0N-5 DA1N-5 DA0N-4 DA1N-4
DA10N-6 DA11N-6 DA10N-5 DA11N-5 DA10N-4 DA11N-4
DB0N-6 DB1N-6 DB0N-5 DB1N-5 DB0N-4 DB1N-4
DB10N-6 DB11N-6 DB10N-5 DB11N-5 DB10N-4 DB11N-4
tAP
N + 1
N + 2
N + 3
N
ENC–
ENC+
DB0_1+
DB0_1–
DA0_1+
DA0_1–
DB10_11
+
DB10_11
–
DA10_11
+
DA10_11
–
CLKOUT+
CLKOUT–
OF+
OF–
215765112 TD01
7
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
TIMING DIAGRAMS
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
21576512 TD02
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
LTC2157-12/
LTC2156-12/LTC2155-12
8
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2157-12: Integral Nonlinearity
(INL)
LTC2157-12: Differential Nonlinearity
(DNL)
LTC2157-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 70MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 122MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 380MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 420MHz, –1dBFS, 250MHz
LTC2157-12: 32K Point FFT,
fIN = 229MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 171MHz, –1dBFS, 250Msps
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21576512 G01
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21576512 G02
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G03
100 120
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G05
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G06
100 120
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G08
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G09
100 120
–20
9
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
LTC2157-12:
Shorted Input Histogram
LTC2157-12: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2157-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 250Msps
LTC2157-12: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
LTC2157-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2157-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 250Msps
LTC2157-12: 32K Point 2-Tone
FFT, fIN = 71.0MHz and 69.0MHz,
250Msps
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100 120
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G11
100 120
–20
OUTPUT CODE
2048
COUNT
12000
16000
20000
21576512 G12
8000
4000
10000
14000
18000
6000
2000
02052
2056
SAMPLE RATE (Msps)
0
I
OVDD
(mA)
60
70
80
200
21576512 G13
50
40
30
50 100 150
250
LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
SAMPLE RATE (Msps)
0
I
VDD
(mA)
260
280
300
200
21576512 G14
240
220
200 50 100 150
250
AMPLITUDE (dBFS)
–90
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0
21576512 G15
60
–80 –60 –30 –20 –10
dBFS
dBc
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10
0
21576512 G16
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21576512 G17
20
30
10
0200 400 500
1000
90
80
600
100 300 900
700
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100 120
–20
LTC2157-12/
LTC2156-12/LTC2155-12
10
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2156-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 71MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 101MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 171MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 227MHz, –1dBFS, 210Msps
LTC2156-12: Integral Nonlinearity
(INL)
LTC2156-12: Differential
Nonlinearity (DNL)
LTC2157-12: Frequency Response
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21576512 G19
–4.0
100
–2.0
–1.5
–1.0
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21576512 G20
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21576512 G21
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G22
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G23
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G24
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G25
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G26
100
–20
LTC2157-12: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21576512 G18
45
40 200 400 500
1000
75
70
600
100 300 900
700
11
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2156-12: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2156-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2156-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point 2-Tone
FFT, fIN = 70.0MHz and 69.0MHz,
210Msps
LTC2156-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 417MHz, –1dBFS, 210Msps
LTC2156-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 210Msps
LTC2156-12: Shorted
Input Histogram
LTC2156-12: 32K Point FFT,
fIN = 379MHz, –1dBFS, 210Msps
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G29
100
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G30
100
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80
100
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60 80 100
–20
OUTPUT CODE
2044 2048
COUNT
12000
16000
20000
21576512 G33
8000
4000
10000
14000
18000
6000
2000
02052
2056
SAMPLE RATE (Msps)
0
I
OVDD
(mA)
60
70
168
21576512 G34
50
40
30
42 84 126
210
LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
SAMPLE RATE (Msps)
0
I
VDD
(mA)
260
280
168
21576512 G35
240
220
200
180 42 84 126
210
AMPLITUDE (dBFS)
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0
21576512 G36
60
–80 –60 –30 –20 –10 10
dBFS
dBc
LTC2157-12/
LTC2156-12/LTC2155-12
12
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2155-12: 32K Point FFT,
fIN = 15MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 70MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 121MHz, –1dBFS, 170Msps
LTC2155-12: Integral Nonlinearity
(INL)
LTC2155-12: Differential
Nonlinearity (DNL)
LTC2156-12: Frequency Response
LTC2156-12: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
210Msps
LTC2156-12: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
210Msps
LTC2156-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 210 Msps
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10
0
21576512 G37
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21576512 G38
20
30
10
0200 400 500
1000
90
80
600
100 300 900
700
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21576512 G39
45
40 200 400 500
1000
75
70
600
100 300 900
700
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21576512 G40
–4.0
100
–2.0
–1.5
–1.0
OUTPUT CODE
0
–2.0
–1.5
–1.0
–0.5
INL ERROR (LSB)
0
0.5
2.0
1.5
1.0
4095
21576512 G41
OUTPUT CODE
0
–0.50
–0.25
DNL ERROR (LSB)
0
0.25
0.50
4095
21576512 G42
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G43
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G44
80
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60
10 30 50 70
80
–20
13
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
LTC2155-12: 32K Point FFT,
fIN = 176MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 420MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 567MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 907MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 380MHz, –1dBFS, 170Msps
LTC2155-12: 32K Point FFT,
fIN = 225MHz, –1dBFS, 170Msps
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60
10 30 50 70
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G47
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G48
80
–20
FREQUENCY (MHz)
0
–120
–100
–80
–60
–40
20 40 60
10 30 50 70
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G50
80
–20
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60
10 30 50 70
21576512 G51
80
–20
LTC2155-12: 32K Point 2-Tone
FFT, fIN = 70.0MHz and 69.0MHz,
170Msps
LTC2155-12: Shorted
Input Histogram
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 3010 40 50 60 70 80
21576512 G52
–20
OUTPUT CODE
2056
COUNT
12000
16000
20000
21576512 G53
8000
4000
10000
14000
18000
6000
2000
02060
2064
LTC2155-12: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
SAMPLE RATE (Msps)
0
25
I
OVDD
(mA)
30
40
45
50
68 136
170
70
21576512 G54
35
34 102
55
60
65 LVDS CURRENT 3.5mA
LVDS CURRENT 1.75mA
LTC2157-12/
LTC2156-12/LTC2155-12
14
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2155-12: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
LTC2155-12: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
LTC2155-12: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps
LTC2155-12: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps
LTC2155-12: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2155-12: Frequency Response
SAMPLE RATE (Msps)
0
I
VDD
(mA)
250
260
136
21576512 G55
240
230
220
210
200
190
180 34 68 102
170
AMPLITUDE (dBFS)
0
SFDR (dBFS)
40
20
80
100
120
–70 –50 –40 0 10
21576512 G56
60
–80 –60 –30 –20 –10
dBFS
dBc
INPUT LEVEL (dBFS)
10
0
SNR (dBc AND dBFS)
20
30
40
50
70
60
–70 –50 –30–60 –40 –20 –10
0
21576512 G57
dBFS
dBc
INPUT FREQUENCY (MHz)
0
SFDR (dBFS)
50
40
60
70
800
21576512 G38
20
30
10
0200 400 500
1000
90
80
600
100 300 900
700
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
55
50
60
65
800
21576512 G59
45
40 200 400 500
1000
75
70
600
100 300 900
700
INPUT FREQUENCY (MHz)
–5.0
INPUT AMPLITUDE (dBFS)
–4.5
–3.5
–3.0
–2.5
1000
–0.5
21576512 G60
–4.0
100
–2.0
–1.5
–1.0
15
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
PIN FUNCTIONS
VDD (Pins 1, 2, 15, 16, 17, 64): 1.8V Analog Power Supply.
Bypass to ground with 0.1µF ceramic capacitors. Pins 1,
2, 64 can share a bypass capacitor. Pins 15, 16, 17 can
share a bypass capacitor.
GND (Pins 3, 6, 9, 11, 14, 18, 21, 58, Exposed Pad
Pin 65): ADC Power Ground. The exposed pad must be
soldered to the PCB ground.
AINA+ (Pin 4): Positive Differential Analog Input for
Channel A.
AINA– (Pin 5): Negative Differential Analog Input for
Channel A.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 × VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. Nominally 1.25V.
VCM (Pin 10): Common Mode Bias Output; nominally equal
to 0.435 • VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
AINB– (Pin 12): Negative Differential Analog Input for
Channel B.
AINB+ (Pin 13): Positive Differential Analog Input for
Channel B.
ENC+ (Pin 19): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 20): Encode Complement Input. Conversion
starts on the falling edge.
NC (Pins 24, 25, 42, 43): Not Connected.
OGND (Pins 33, 48): Output Driver Ground.
OVDD (Pins 32, 49): 1.8V Output Driver Supply. Bypass
each pin to ground with separate 0.1µF ceramic capacitors.
SDO (Pin 59): Serial Interface Data Output. In serial pro-
gramming mode, (PAR/SER = 0V), SDO is the optional serial
interface data output. Data on SDO is read back from the
mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2k pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
SDI (Pin 60): Serial Interface Data Input. In serial program-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registers on the rising edge of SCK. In the parallel pro-
gramming mode (PAR/SER = VDD), SDI selects 3.5mA or
1.75mA LVDS output current (see Table 2). SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin 61): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK can be used to place the part in the
low power sleep mode (see Table 2). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin 62): Serial Interface Chip Select Input. In serial
programming mode, (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD), CS
controls the clock duty cycle stabilizer (see Table 2). CS
can be driven with 1.8V to 3.3V logic.
PAR/SER (Pin 63): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
control the A/D operating modes. Connect to VDD to en-
able the parallel programming mode where CS, SCK, SDI
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
LTC2157-12/
LTC2156-12/LTC2155-12
16
21576512fb
For more information www.linear.com/LTC2157-12
PIN FUNCTIONS
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF–/OF+ (Pins 22/23): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
The overflows for channel A and channel B are multiplexed
together.
DB0_1–/DB0_1+ to DB10_11–/DB10_11+ (Pins 26/27, 28/29,
30/31, 34/35, 36/37, 38/39): Channel B Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DB0, DB2, DB4,
DB6, DB8, DB10) appear when CLKOUT+ is low. The odd
data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 40/41): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DA0_1–/DA0_1+ to DA10_11–/DA10_11+ (Pins 44/45, 46/47,
50/51, 52/53, 54/55, 56/57): Channel A Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (DA0, DA2, DA4,
DA6, DA8, DA10) appear when CLKOUT+ is low. The odd
data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when
CLKOUT+ is high.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
S/H
VCM
BUFFER
BUFFER
BUFFER
GND
VCM
0.1µF
CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
21576512 F01
DDR
LVDS
DDR
LVDS
V
DD
OVDD
OGND
CS
CHANNEL A
CHANNEL B
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
SPI
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OVDD
OGND
VREF
2.2µF
GND
GND
SENSE
SCK
SDI
PAR/SER
DA10_11
•
•
•
DA0_1
DB10_11
•
•
•
DB0_1
17
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
CONVERTER OPERATION
The LTC2157-12/LTC2156-12/LTC2155-12 are two-
channel, 12-bit 250Msps/210Msps/170Msps A/D con-
verters that are powered by a single 1.8V supply. The
analog inputs must be driven differentially. The en-
code inputs should be driven differentially for optimal
performance. The digital outputs are double-data rate
LVDS. Additional features can be chosen by programming
the mode control registers through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-
hold circuits (Figure 2). The inputs must be driven differ-
entially around a common mode voltage set by the VCM
output pin, which is nominally 0.435 • VDD. For the 1.5V
input range, the inputs should swing from VCM – 0.375V
to VCM + 0.375V. There should be 180° phase difference
between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC compo-
nent values should be chosen based on the application’s
specific input frequency.
T
ransformer-Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin.
At higher input frequencies a transmission line balun
transformer (Figures 4 and 5) has better balance, resulting
in lower A/D distortion.
Figure 2. Equivalent Input Circuit. Only One
of Two Analog Channels Is Shown
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
APPLICATIONS INFORMATION
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
2pF
RON
20Ω
RON
20Ω
VDD
VDD
LTC2157-12
AIN+
21576512 F02
2pF
VDD
AIN–
ENC
–
ENC
+
2pF
2pF
1.2V
10k
25Ω
25Ω 4.7Ω
4.7Ω
10Ω
0.1µF
10pF
0.1µF
LTC2157-12
IN
0.1µF T1
1:1
T1: MACOM ETC1-1T
21576512 F03
AIN+
AIN–
VCM
45Ω
45Ω
100Ω
10Ω
4.7Ω
4.7Ω
0.1µF
0.1µF
IN
0.1µF
0.1µF
T1: MABA
007159-000000
T2: WBC1-1L
21576512 F04
LTC2157-12
AIN+
AIN–
VCM
LTC2157-12/
LTC2156-12/LTC2155-12
18
21576512fb
For more information www.linear.com/LTC2157-12
APPLICATIONS INFORMATION
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz Up to 900MHz
Figure 6. Front-End Circuit Using a High
Speed Differential Amplifier
Amplifier Circuits
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain block
is single-ended, then a transformer circuit (Figures3 and
5) should convert the signal to differential before driving
the A/D. The A/D cannot be driven single ended.
Reference
The LTC2157-12/LTC2156-12/LTC2155-12 has an internal
1.25V voltage reference. For a 1.5V input range with in-
ternal reference, connect SENSE to VDD. For a 1.5V input
range with an external reference, apply a 1.25V reference
voltage to SENSE (Figure 7).
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
Figure 7. Reference Circuit
Figure 8. Equivalent Encode Input Circuit
45Ω
100Ω
4.7Ω
4.7Ω
45Ω
10Ω 0.1µF
0.1µF
IN
0.1µF
0.1µF
T1: MABA
007159-000000
21576514 F05
LTC2157-12
AIN+
AIN–
VCM
4.7Ω
4.7Ω
50Ω
50Ω
0.1µF
AIN+
AIN–
0.1µF
3pF
3pF
3pF
VCM
LTC2157-12
21576512 F06
INPUT
0.1µF
SCALER/
BUFFER
V
REF
2.2µF
SENSE
1.25V
21576512 F07
5Ω
ADC
REFERENCE
SENSE
DETECTOR
VDD
LTC2157-12
21576512 F08
1.2V
10k
ENC+
ENC–
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
19
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this case care should be taken to make the clock a 50%
(±5%) duty cycle.
Figure 9. Sinusoidal Encode Drive
DIGITAL OUTPUTS
The digital outputs are double-data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are six LVDS output pairs for channel A
(DA0_1+/DA0_1– through DA10_11–/DA10_11+) and six
pairs for channel B (DB0_1+/DB0_1– through DB10_11–/
DB10_11+). Overflow (OF+/OF–) and the data output clock
(CLKOUT+/CLKOUT–) each have an LVDS output pair. Note
that overflow for both channels is multiplexed onto the
OF+/OF– output pair.
Figure 10. PECL or LVDS Encode Drive
LTC2157-12
T1
VDD
21576512 F09
1.2V
10k
50Ω
100Ω
50Ω
0.1µF
0.1µF
T1: MACOM ETC1-1-13
VDD
LTC2157-12
PECL OR
LVDS INPUT
21576512 F10
1.2V
10k
100Ω
0.1µF
0.1µF
ENC+
ENC–
LTC2157-12/
LTC2156-12/LTC2155-12
20
21576512fb
For more information www.linear.com/LTC2157-12
APPLICATIONS INFORMATION
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair
. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
The OF output is double-data rate; when CLKOUT+ is low,
channel A’s overflow is available; when CLKOUT+ is high,
channel B’s overflow is available.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
trol register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 11).
Figure 11. Phase Shifting CLKOUT
CLKOUT+
D0-D11, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
21576512 F11
ENC+
21
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LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
Figure 12. Functional Equivalent of Digital Output Randomizer
Figure 13. Decoding a Randomized Digital
Output Signal
APPLICATIONS INFORMATION
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(1.5V Range) OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>0.75 V
+0.75V
+0.7496337V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.0003662V
+0.000000V
–0.0003662V
–0.0007324V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.74963378V
–0.75V
< –0.75V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
CLKOUT
CLKOUT
OF
D11/D0
D10/D0
•
•
•
D1/D0
D0
21576512 F12
OF
D11
D10
D1
D0
RANDOMIZER
ON
D11
FPGA
PC BOARD
D10
•
•
•
D1
D0
21576512 F13
D0
D1/D0
D10/D0
D11/D0
OF
CLKOUT
LTC2157-12
LTC2157-12/
LTC2156-12/LTC2155-12
22
21576512fb
For more information www.linear.com/LTC2157-12
Alternate Bit Polarity
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output random-
izer—either both or neither function can be on at the same
time. The alternate bit polarity mode is enabled by serially
programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11 to D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Sleep Mode
The A/D may be placed in a power-down mode to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in < 5mW power consumption. If the en-
code input signal is not disabled the power consumption
will be higher (up to 5mW at 250Msps). Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SCK (parallel programming mode).
In the serial programming mode it is also possible to dis-
able channel B while leaving channel A in normal operation.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF .
For the suggested values in Figure 1, the A/D will stabi-
lize after 0.1ms + 2500 • tp where tp is the period of the
sampling clock.
Nap Mode
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster wake-
up. Recovering from nap mode requires at least 100 clock
cycles. Wake-up time from nap mode is guaranteed only if
the clock is kept running, otherwise sleep mode wake-up
conditions apply. Nap mode is enabled by setting register
A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC215x-12 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
APPLICATIONS INFORMATION
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LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is neces-
sary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is WRITE-ONLY.
GROUNDING AND BYPASSING
The LTC215x-12 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF pins. Bypass capacitors must be
located as close to the pins as possible. Size 0402 ceramic
capacitors are recommended. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC215x-12 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
APPLICATIONS INFORMATION
LTC2157-12/
LTC2156-12/LTC2155-12
24
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For more information www.linear.com/LTC2157-12
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bit 7 RESET Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0 Unused bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X SLEEP NAP PDB 0
Bits 7-4 Unused, these bits are read back as 0
Bit 3 SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2 NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1 PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0 Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, these bits are read back as 0
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
25
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LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF
Bits 7-5 Unused, these bits are read back as 0
Bits 4-2 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0 OUTOFF Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
OUTTEST2 OUTTEST1 OUTTEST0 ABP 0 DTESTON RAND TWOSCOMP
Bits 7-5 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D11-D0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3 Must be set to 0
Bit 2 DTESTON Enable the digital output test patterns (set by Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0 TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
APPLICATIONS INFORMATION
LTC2157-12/
LTC2156-12/LTC2155-12
26
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
27
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
LTC2157-12/
LTC2156-12/LTC2155-12
28
21576512fb
For more information www.linear.com/LTC2157-12
TYPICAL APPLICATIONS
Bottom Side
Inner Layer 4 Inner Layer 5
29
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
TYPICAL APPLICATIONS
LTC2157-12 Schematic
VDD
VDD
GND
AINA+
AINA–
GND
SENSE
VREF
GND
VCM
GND
AINB–
AINB+
GND
VDD
VDD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OGND
DA2_3+
DA2_3–
DA0_1+
DA0_1–
NC
NC
CLKOUT+
CLKOUT–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
DB6_7+
DB6_7–
OGND
DA2_3+
DA2_3–
DA0_1+
DA0_1–
CLKOUT+
CLKOUT–
DB10_11+
DB10_11–
DB8_9+
DB8_9–
DB6_7+
DB6_7–
VDD
GND
ENC+
ENC–
GND
OF–
OF+
NC
NC
DB0_1–
DB0_1+
DB2_3–
DB2_3+
DB4_5–
DB4_5+
OVDD
DB4_5+
DB4_5–
DB2_3+
DB2_3–
DB0_1+
DB0_1–
OF+
OF–
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
PAR_SER
CS
SCK
SDI
SDO
GND
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7–
DA4_5+
DA4_5–
OVDD
DA10_11+
DA10_11–
DA8_9+
DA8_9–
DA6_7+
DA6_7–
DA4_5+
DA4_5–
SDO
SDI
SCK
CS
VDD
VDD
C4
2.2µF
AINB+
AINB–
C29
0.1µF
R12
100Ω
R8
100Ω
SENSE
OVDD
OVDD
LTC2157-12
VDD
ENC+
ENC–
R56
100Ω
PAR/SER
R7
10Ω
R6
10Ω
C78
0.1µF
C14
0.1µF
C79
0.1µF
C13
0.1µF
C15
0.1µF
C5
0.1µF
C7
0.1µF
C11
0.1µF C12
0.1µF
C3
1pF
AINA+
AINA–
R34
10Ω
R33
10Ω
C27
1pF
21576512 TA11
LTC2157-12/
LTC2156-12/LTC2155-12
30
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For more information www.linear.com/LTC2157-12
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
9 .00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
PIN 1 TOP MARK
(SEE NOTE 5)
0.40 ±0.10
6463
1
2
BOTTOM VIEW—EXPOSED PAD
7.15 0.10
7.15 0.10
7.50 REF
(4-SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UP64) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
7.50 REF
(4 SIDES)
7.15 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
PIN 1
CHAMFER
C = 0.35
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
31
21576512fb
LTC2157-12/
LTC2156-12/LTC2155-12
For more information www.linear.com/LTC2157-12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/14 Changed the pipeline latency to 6
Updated G16, G37 and G57
5 and 6
9, 12 and 14
B 07/15 Correcting the connection of SENSE in the schematic 29
LTC2157-12/
LTC2156-12/LTC2155-12
32
21576512fb
For more information www.linear.com/LTC2157-12
© LINEAR TECHNOLOGY CORPORATION 2011
LT 0715 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2157-12
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LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5575 800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
,
Integrated RF and LO Transformer
Amplifiers/Filters
LTC6409 10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply Current
3mm × 2mm QFN Package
LTC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain
Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise
Figure, 4mm × 4mm QFN-24
LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC
Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per
Amplifier, 3mm × 4mm QFN-20
Receiver Subsystems
LTM
®
9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
LTM9003 12-Bit Digital Pre-Distortion Receiver ADC Driver, 0.4GHz to 3.8GHz RF Input
TYPICAL APPLICATION
LTC2157-12: 32K Points 2-Tone FFT,
fIN = 71MHz and 69MHz, 250Msps
FREQUENCY (MHz)
0
–120
AMPLITUDE (dBFS)
–100
–80
–60
–40
0
20 40 60 80
21576512 G11
100 120
–20
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
DA10_11
•
•
•
DA0_1
DB10_11
•
•
•
DB0_1
CLOCK
ANALOG
INPUT
21576512 TA01
DDR
LVDS
DDR
LVDS
V
DD
OVDD
OGND
GND
CHANNEL A
S/H CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OGND
OVDD
CHANNEL B