[> s Connection Diagram 28-Pin PCC OLKg CLKg CLK Vega OLKy CLKg OLKg BEE __ C) CLKz CLK; Ky CLK, CLKy Vega CLK CLKy CLK DS010648-2 rr err re March 1998 FAIRCHILD OE SEMICONDUCTOR m Low Skew 1:9 Differential Clock Driver General Description Features The 100311 contains nine low skew differential drivers, de- | Low output to output skew signed for generation of multiple, minimum skew differential | 2000V ESD protection clocks from a single differential input (CLKIN, CLKIN). If a sm 1:9 low skew clock driver single-ended input is desired, the Vgs output pin may be ww Differential inputs and outputs used to drive the remaining input line. A HIGH on the enable pin (EN) will force a LOW on all of the CLK, outputs and a HIGH on all of the CLK,, output pins. The 100311 is ideal for distributing a signal throughout a system without worrying about the original signal becoming too corrupted by undesir- able delays and skew. The 100311 is pin-for-pin compatible with the Motorola 100E111. Ordering Code: Logic Symbol Pin Names Description CLKIN, CLKIN Differential Clock Inputs CLK, =7 ky EN Enable = CLK, CLKy_g, CLKy_g Differential Clock Outputs CLK a clk, Ves Veg Output CLK, NC No Connect CLK aks Truth Table CLRIN | cLity cLKIN ie ae CLKIN CLKIN EN CLK, CLK, my | Ek L H L L H rt CLK H L L H L CLKg | | CLK, xX xX H L H OK, L LKy CLKy 1998 Fairchild Semiconductor Corporation DS010648 www fairchildsemi.com =| M8YS MO LLEOOL 0 49O0[D [BNUSsI9IG 6 JA9OALAAbsolute Maximum Ratings (note 1) Above which the useful life may be impaired Storage Temperature (Tsya@) Maximum Junction Temperture (TJ) Ceramic Plastic Pin Potential to Ground Pin (Vee) Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Commercial Version DC Electrical Characteristics Ver = -4.2V to -5.7V, Voc = Veca = GND, Te = 0C to +85C (Note 3) -65C to +150C +175C +150C -7.0V to +0.5V Veg to +0.5V -50 mA 2>2000V Recommended Operating Conditions Case Temperature (Tg) Commercial 0C to +85C Industrial -40C to +85C Supply Voltage (Vee) -5.7V to -4.2V Note 1: Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin = Vin (Max) Loading with VoL Output LOW Voltage -1830 -1705 -1620 mV or Vi_ (Min) 50Q to -2.0V Vouc Output HIGH Voltage -1035 mV Vin = Vin Loading with Voie Output LOW Voltage -1610 mV or ViL (Max) 50Q to -2.0V VeB Output Reference Voltage -1380 -1320 -1260 mV lyep = 300 HA VoleEF Input Voltage Differential 150 mV Required for Full Output Swing Vom Common Mode Voltage Veco - 2.0 Voc - 0.5 v Vin Input High Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input Low Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vit (Min) la Input HIGH Current Vin = Vin (Max) CLKIN, CLKIN 100 WA EN 250 loBo Input Leakage Current -10 HA Vin = Vee lee Power Supply Current -115 -57 mA Inputs Open AC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND Note 3: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Symbol Parameter Toe =0C To = +25C To = +85C Units | Conditions Min) Typ Max| Min Typ Max] Min Typ Max finax Max Toggle Frequency 750 750 750 MHz CLKIN to Q, teLy Propagation Delay, tpHL CLKIN, to CLK, Differential | 0.75 084 095]0.75 086 095]084 093 1.04 ns Figure 3 Single-Ended | 0.65 0.90 1.05] 0.67 093 1.17 ]0.74 1.06 1.24 teLy Propagation Delay 0.75 1.03 1.20] 080 1.05 125/085 1.12 1.35 ns Figure 2 teu SEL to Output tps LH-HL Skew 10 30 10 30 10 30 (Notes 4, 7) tosLu GateGate Skew LH 20 50 20 50 20 50 (Notes 5, 7) tosHL Gate-Gate Skew HL 20 50 20 50 20 50 ps (Notes 5, 7) tost GateGate LH-HL Skew 30 60 30 60 30 60 (Notes 6, 7) www fairchildsemi.comAC Electrical Characteristics (Continue Vee = 4.2V to -5.7V, Voo = Veca = GND Symbol Parameter To = OC To = +25C To = +85C Units Conditions Min Typ Max| Min Typ Max! Min Typ Max ts Setup Time 250 250 300 ps EN, to CLKIN, ty Hold Time 0 0 0 ps EN, to CLKIN, tr Release Time 300 300 300 ps EN, to CLKIN, tty Transition Time 275 500 750 | 275 480 750 | 275 460 750 ps Figure 4 trae 20% to 80%, 80% to 20% Note 4: tpg describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's low to high and high to low propagation delays. With differential signal pairs, a low to high or high to low transition is defined as the transition of the true output or input pin. Note 5: tog. describes in-phase gate-to-gate differential propagation skews with all differential outputs going low to high; togu_ describes the same conditions ex- cept with the outputs going high to low. Note 6: tost describes the maximum worst case difference in any of the tps, tosLH or tost delay paths combined. Note 7: The skew specifications pertain to differential |/O paths. Note 8: fmax = the highest frequency at which output VoL/Vou levels still meet Vin specifications. The F311 will function @ 1 GHz. Industrial Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND (Note 9) Symbol Parameter To = -40C To = OC to +85C [Units Conditions Min Max Min Max Vou Output HIGH Voltage -1085 -870 -1025 -870 mV | Vin = Vin (Max)! Loading with VoL Output LOW Voltage -1830 -1575 -1830 -1620 mV | or Vi (Min) 50Q to -2.0V Vouc | Output HIGH Voltage -1095 -1035 mV] Vin = Vin Loading with Voto Output LOW Voltage -1565 -1610 mV | or Vi, (Min) 50Q to -2.0V Ves Output Reference Voltage -1395 -1255 -1380 -1260 mV | lyga = -300 PA VoIFF Input Voltage Differential 150 150 mV | Required for Full Output Swing Vom Common Mode Voltage Veo -2.0 Veco-0.5 | Veo-2.0 Voc - 0.5 Vv Vin Input High Voltage -1170 -870 -1165 -870 mV | Guaranteed HIGH Signal for All Inputs DC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND (Note 9) Symbol Parameter To = -40C Te = OC to+85C | Units Conditions Min Max Min Max Vit Input Low Voltage -1830 -1480 -1830 -1475 mV | Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 0.50 HA | Vin = Vit (Min) liq Input HIGH Current Vin = Vin (Max) CLKIN, CLKIN 100 100 uA EN 250 250 loBo Input Leakage Current -10 -10 HA | Vin = Vee lee Power Supply Current -115 -57 -115 -57 mA | Inputs Open Vpp Minimum Input Swing 150 150 mV Vome\ Common Mode Range | Veco-2.0 Voc 0.5 Voec-2.0 Voc 0.5 Vv Note 9: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. www fairchildsemi.comAC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND Symbol Parameter To = -40C To = +25C To = +85C Units Conditions Min Typ Max| Min Typ Max| Min Typ Max finax Max Toggle Frequency 750 750 750 MHz CLKIN to Q,, teLy Propagation Delay, TPHL CLKIN, to CLK, Differential |} 0.72 0.81 0.92]0.77 086 095]084 093 1.04 ns Figure 3 Single-Ended | 0.62 0.89 1.02]067 0.93 1.17] 074 1.06 1.24 teLy Propagation Delay 0.70 0.97 120/080 1.05 125/085 1.12 1.35 ns Figure 2 tpHL SEL to Output Ips LH-HL Skew 10 30 10 30 10 30 (Notes 10, 13) tosLH GateGate Skew LH 20 50 20 50 20 50 ps (Notes 11, 13) tosHL GateGate Skew HL 20 50 20 50 20 50 (Notes 11, 13) lost GateGate LH-HL Skew 30 60 30 60 30 60 (Notes 12, 13) ts Setup Time 250 250 300 ps EN, to CLKIN,, ty Hold Time 0 0 0 ps EN, to CLKIN,, tr Release Time 300 300 300 ps EN, to CLKIN,, tH Transition Time 275 500 750 | 275 480 750 | 275 460 750 ps Figure 4 tra 20% to 80%, 80% to 20% Note 13: The skew specifications pertain to differential |/O paths. Note 12: tost describes the maximum worst case difference in any of the tps, tos_H or togt delay paths combined. Note 10: tpg describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's low to high and high to low propagation delays. With differential signal pairs, a low to high or high to low transition is defined as the transition of the true output or input pin. Note 11: tog. describes in-phase gate differential propagation skews with all differential outputs going low to high; togy, describes the same conditions except with the outputs going high to low. www fairchildsemi.comTest Circuit L1 5 l SCOPE CHAN B 0.011 uF Lb L2 TL [ | L3 SCOPE CHAN A 1 = SCOPE CHAN C Veca cLK1 CLKIN SCOPE CHAN D DIFFERENTIAL PULSE GENERATOR oO KP KP a 2 ~ | -2.5V DS010848-3 Note 14: Shown for testing CLKIN to CLK1 in the differential mode. Note 15: L1, L2, L3 and L4 = equal length 50 impedance lines. Note 16: All unused inputs and outputs are loaded with 50Q in parallel with < 3 pF to GND. Note 17: Scope should have 50Q input terminator internally. FIGURE 1. AC Test Circuit Switching Waveforms 0.740.1ns SEL CLK(O-8) OUTPUTS CLK(O-8) DS010648-4 FIGURE 2. Propagation Delay, EN to Outputs CLKIN 1.05V INPUTS CLKIN 0.31V teu toy tPHL tPHL CLK(0-8) TRUE OUTPUTS CLK(0-8) COMPLEMENT DS010648-5 FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs www fairchildsemi.comSwitching Waveforms (continued) CLK(0-8) 80% 80% __ 20% 20% CLK(0-8) tty tra DS010648-6 FIGURE 4. Transition Times Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100311 Q Device Type L Temperature Range (Basic) C = Commercial (0C to + 85C) | = Industrial ( 40C to + 85C) Package Code (PCC only) Q = Plastic Leaded Chip Carrier (PCC) DS010648-7 www fairchildsemi.com 6iver 9 Differential Clock Dri 100311 Low Skew 1 Physical DimensiONS inches (millimeters) unless otherwise noted 0.450 79-008 [11.43] "0-08 PIN #1 IDENT 1 26 0.02940.003 [0.740.08] [] 25 U] O U U] U] L]19 [4.19-4.57] 0.49040.005 [12.450.13] 0.165-0.180 typ ase x 0-045 [1.14] 9.0170.004 ryp "] [0.4340.10] 0.4100.020 typ [10.4140.51] SEATING PLANE la }<- 9-029 win TYP [0.51] |_0.10540.015 [2.6740.38] [0.004 [0.10] V28A (REV h) 28-Lead Plastic Chip Carrier (Q) Package Number V28A LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- 2. tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. Americas Fax: +49 (0) 1 80-530 85 86 13th Floor, Straight Block, Tel: 81-3-5620-6175 Customer Response Center Email: europe.support@nsc.com Ocean Centre, 5 Canton Rd. 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