October 1998 7-49
MIC58P42 Micrel
7
VEE
OUTPUT
ENABLE/RESET
STROBE
SERIAL DATA OUT
VDD
VSS
SERIAL DATA IN
CLOCK
VEE
K
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
SHIFT REGISTER
LATCHES
SUB
UVLO THERMAL
SHUTDOWN
I LIMIT
SUB
9
8
7
6
5
4
3
2
1
10
11
12
13
14
15
16
17
18
General Description
The MIC58P42 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common STROBE, CLOCK, SERIAL DATA INPUT, and
OUTPUT ENABLE functions. Similar to the MIC5842, addi-
tional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and over-
current shutdown.
The bipolar/CMOS combination provides an extremely low-
power latch with maximum interface flexibility. The MIC58P42
has open-collector outputs capable of sinking 500 mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
With a 5V logic supply, the MIC58P42 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current detection, the
affected channel will turn OFF until VDD is cycled or the
ENABLE/RESET pin is pulsed high. Current pulses less than
2µs will not activate current shutdown. Temperatures above
165°C will shut down the device. The UVLO circuit prevents
operation at low VDD; hysteresis of 0.5V is provided. See the
MIC59P60 for a similar device that additionally provides an
error flag output.
Features
• 3.3 MHz Minimum Data-Input Rate
• CMOS, PMOS, NMOS, and TTL Compatible
• Internal Pull-Up/Pull-Down Resistors
• Low Power CMOS Logic and Latches
• High Voltage (80V) Current-Sink Outputs
• Output Transient-Protection Diodes
• Single or Split Supply Operation
• Thermal Shutdown
• Under-Voltage Lockout
• Per-Output Over-Current Shutdown (500mA typical)
Ordering Information
Part Number Temperature Range Package
MIC58P42BN –40°C to +85°C 18-Pin Plastic DIP
MIC58P42BV –40°C to +85°C 20-Pin PLCC
MIC58P42BWM –40°C to +85°C 18-Pin Wide SOIC
Pin Configuration
(DIP and SOIC)
Functional Diagram
CLOCK
SERIAL
DATA IN
VSS
UVLO
THERMAL
SHUTDOWN ILIMIT
K OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
SUB
VEE
MOS
BIPOLAR
SERIAL DATA OUT
VDD
STROBE
OUTPUT
ENABLE/RESET
8-BIT SERIAL–PARALLEL SHIFT REGISTER
LATCHES
1
2
3
4
5
6
7
8
910 1112131415161718
MIC58P42
8-Bit Serial-Input Protected Latched Driver
7-50 October 1998
MIC58P42 Micrel
Absolute Maximum Ratings (Note 1, 2)
at 25°C Free-Air Temperature and VSS = 0V
Output Voltage 80V
Output Voltage, VCE(SUS) (Note 1) 50V
Logic Supply Voltage Range, VDD 4.5V to 15V
VDD with Reference to VEE 25V
Emitter Supply Voltage (Substrate), VEE –20V
Input Voltage Range, VIN –0.3V to VDD + 0.3V
Package Power Dissipation, PD
MIC58P42BN 1.82W
Derate above TA = +25°C 18mW/°C
MIC58P42BV 1.4W
Derate above TA = +25°C 14mW/°C
MIC58P42BWM 1.2W
Derate above TA = +25°C 12mW/°C
Operating Temperature Range, TA–55°C to +125°C
Storage Temperature Range, TS–65°C to +150°C
Note 1:For Inductive load applications.
Note 2: CMOS devices have input-static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
STROBE
OUTPUT
ENABLE
DD
V
SS
V
CLOCK
SERIAL
DATA IN
DD
V
SS
V
Typical Input Circuits
PLCC Pin Configuration
1
2
3
4
12 1311
20 19
18
14
15
16
17
9 10
5
6
7
8
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
OUT 8
K
SERIAL DATA OUT
VSS
SERIAL DATA IN
STROBE
NC
OE/RESET
VDD
NC
VEE
MIC58P42BV
CLOCK
VEE
SUB
NOUT
K
EE
V
3K
Typical Output Driver
Pin Name Description
(DIP & S.O.)
1,9 VEE Substrate. Most Negative voltage in the system connects here.
2 CLOCK Serial Data Clock. A CLEAR input must also be clocked into the latches.
3 SERIAL DATA IN Serial Data Input pin.
4V
SS Logic reference (Ground) pin.
5V
DD Logic Positive Supply voltage.
6 SERIAL DATA OUT Serial Data Output pin. (Flow–through).
7 STROBE Output Strobe pin. Loads output latches when high. Strobe is needed to clear latch.
8 OUTPUT When Low, Outputs are active. When High, device is reset from a fault condition.
ENABLE/RESET
10 K Transient suppression diode's cathode common pin.
11—18 OUTPUT N Open Collector outputs 8 through 1.
Pin Description
October 1998 7-51
MIC58P42 Micrel
7
Electrical Characteristics at TA = +25°C, VDD = 5V, VSS = VEE = 0V (unless otherwise noted)
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Output Leakage Current ICEX VOUT = 80V 50 µA
VOUT = 80V, TA = +70°C 100
Collector-Emitter VCE(SAT) IOUT = 100mA 0.9 1.1 V
Saturation Voltage IOUT = 200mA 1.1 1.3
IOUT = 350mA 1.3 1.6
Collector-Emitter VCE(SUS) IOUT = 350mA, L = 2mH 50 V
Sustaining Voltage
Input Voltage VIN(0) 1.0 V
VIN(1) VDD = 12V 10.5
VDD = 10V 8.5
VDD = 5.0V, Note 1 3.5
Input Resistance RIN VDD = 12V 50 200 kΩ
VDD = 10V 50 300
VDD = 5.0V 50 600
Supply Current IDD(ON) All Drivers ON, VDD = 12V 6.4 10.0 mA
All Drivers ON, VDD = 10V 6.0 9.0
All Drivers ON, VDD = 5.0V 4.6 7.5
IDD (1 ON) One Driver ON, All others OFF, VDD = 12V 3.1 4.5
One Driver ON, All others OFF, VDD = 10V 2.9 4.5
One Driver ON, All others OFF, VDD = 5V 2.3 3.6
IDD(OFF) All Drivers OFF, VDD = 12V 2.6 4.2
All Drivers OFF, VDD = 10V 2.4 3.6
All Drivers OFF, VDD = 5.0V 1.9 3.0
Clamp Diode IRVR = 80V 50 µA
Leakage Current
Clamp Diode VFIF = 350mA 1.7 2.0 V
Forward Voltage
Output Current ILIM 500 mA
Shutdown Threshold
Start Up Voltage VSU Note 2 3.5 4.0 4.5 V
Minimum Supply (VDD)V
DD MIN 3.0 3.5 4.0 V
Thermal Shutdown 165 °C
Thermal Shutdown Hysteresis 10 °C
Note 1: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 2: Undervoltage Lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V.
7-52 October 1998
MIC58P42 Micrel
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
D
B
A
E
C
G
OUTN
F
Timing Conditions
(TA = +25°C, Logic Levels are VDD and VSS), VDD = 5V
A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ...........................................................................75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time)..............................................................................75 ns
C. Minimum Data Pulse Width .....................................................................................................................................150 ns
D. Minimum Clock Pulse Width....................................................................................................................................150 ns
E. Minimum Time Between Clock Activation and Strobe .............................................................................................300 ns
F. Minimum Strobe Pulse Width...................................................................................................................................100 ns
G. Typical Time Between Strobe Activation and Output Transition .............................................................................500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.
MIC58P42 Truth T able
Shift Register Contents Serial Latch Contents Output Contents
Serial Data Clock Data Strobe Output
Input Input I1I2I3…… I8Output Input I1I2I3…… I8Enable I1I2I3…… I8
HHR
1R2…… R7R7
LLR
1R2…… R7R7
XR1R2R
3…… R8R8
OOO……O L
XXX……X X L R
1R2R3…… R8
P1P2P3…… P8P8HP
1P2P3…… P8LP
1P2P3……P8
XX X……X H H H H……H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
October 1998 7-53
MIC58P42 Micrel
7
VDD = 12V Number of Outputs ON
(IOUT = 200mA Max. Allowable Duty Cycle at Ambient Temperature of:
VDD = 12V) 25°C40°C50°C60°C70°C
8 80% 68% 60% 52% 44%
7 91% 77% 68% 59% 50%
6 100% 90% 79% 69% 58%
5 100% 100% 95% 82% 69%
4 100% 100% 100% 100% 86%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
Number of Outputs ON
(IOUT = 200mA Max. Allowable Duty Cycle at Ambient Temperature of:
VDD = 5.0V) 25°C40°C50°C60°C70°C
8 85% 72% 64% 55% 46%
7 97% 82% 73% 63% 53%
6 100% 96% 85% 73% 62%
5 100% 100% 100% 88% 75%
4 100% 100% 100% 100% 93%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
–50 0 50 100 150
SATURATION VOLTAGE (V)
TEMPERATURE (°C)
Output Saturation
Voltage vs. Temperature
IL = 350mA
IL = 100mA
VDD = 5V to 12V
0
1
2
3
4
5
–50 0 50 100 150
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
ALL OUTPUTS ON
ALL OUTPUTS OFF
Supply Current
vs. Temperature
V
DD
= 5V
0.35
0.40
0.45
0.50
0.55
0.60
–50 0 50 100 150
SHUTDOWN THRESHOLD (A)
TEMPERATURE (°C)
V
DD
= 5V
V
DD
= 12V
Current Shutdown
Threshold vs. Temperature
50
100
150
200
250
300
5 7 9 11 13 15
OUTPUT DELAY (ns)
SUPPLY VOLTAGE (V
DD
)
T
D
OFF
T
D
ON
Output Delay
vs. Supply Voltage
R
L
= 50Ω
0
1
2
3
4
5
6
7
–50 0 50 100 150
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
Supply Current
vs. Temperature
ALL OUTPUTS ON
ALL OUTPUTS OFF
V
DD
= 12V
0
2
4
6
8
10
12
14
16
18
20
0.3 0.4 0.5 0.6 0.7 0.8 0.9
CURRENT LIMIT DELAY (µs)
OUTPUT CURRENT (A)
Current Shutdown
Delay vs. Output Current
V
DD
= 12V
V
DD
= 5V
Maximum Allowable Duty Cycle, Plastic DIP
VDD = 5.0V
Typical Characteristic Curves
