Programmable Skew Clock Buffer
CY7B991
CY7B992
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07138 Rev. ** Revised September 26, 2001
92
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at 1⁄2 and 1⁄4 input frequency
—Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input to output delay
• 50% duty-cyc le outputs
•Outputs drive 50Ω terminated lines
•Low operating current
•32-pin PLCC/LCC package
•Jitter < 200 ps peak-to-peak (< 25 ps RMS)
•Compatible wit h a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buf f-
ers (PSCB) offer user-selectable control over system clock
function s. Thes e multip le-output clock d rivers p rovide th e sys-
tem int egra tor with func tion s nec es sa ry to optimize the tim in g
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each ou tput can be hardwired to o ne of ni ne delay or func tio n
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequen cy with outputs ab le to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock d istrib ution dif ficul ty while allowi ng maxi mum sys -
tem clock speed and flexibility.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram Pin Configurati o n
7B991–1
7B991–2
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL) SKEW
SELECT
MATRIX
1234323130
17161514 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F0
FS
V
REF
GND
TEST
2F1
FB
2Q1
2Q0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
CCQ
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3Q1
3Q0
CCN
V
CCN
V
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B991
CY7B992
FILTER
PHASE
FREQ
DET
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 2 of 15
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) in put and the fe edbac k (FB) i nput a nd gen erate c orrec-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signa l.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generato r to create di sc rete tim e uni ts that are s ele cte d i n th e
skew select matrix. The operational range of the VCO is de-
termined by the FS control pin. The time unit (tU) is determined
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
Skew Select Matrix
The ske w select ma trix is c om pri se d of fo ur in dependen t se c-
tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ 1), a nd tw o c orre sp ond ing t hree-level f unc tio n se lec t
(xF0, xF1) inputs. Table 2 below sh ows the nine possib le out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0tU se lec ted .
Pin Definitions
Signal
Name I/O Description
REF IReference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
FB IPLL feedback input (typically connected to one of the eight outputs).
FS IThree-level frequency range select. See Table 1.
1F0, 1F1 IThree-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 IThree-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 IThree-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST IThree-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 OOutput pair 1. See Table 2.
2Q0, 2Q1 OOutput pair 2. See Table 2.
3Q0, 3Q1 OOutput pair 3. See Table 2.
4Q0, 4Q1 OOutput pair 4. See Table 2.
VCCN PWR Power supply for output drivers.
VCCQ PWR Power supply for internal circuitry.
GND PWR Ground.
Table 1. Frequency Range Select and tU Calculation[1]
FS[2, 3]
fNOM (MHz)
where N =
Approximate
Frequency (MHz) At
Which tU = 1.0 nsMin. Max.
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 80 16 62.5
tU1
fNOM N×
------------------------=
Table 2. Programmable Skew Configurations[1]
Function Selects Output Functions
1F1, 2F1,
3F1, 4F1 1F0, 2F0,
3F0, 4F0 1Q0, 1Q1,
2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
LOW LOW –4tUDivide by 2 Divide by 2
LOW MID –3tU–6tU–6tU
LOW HIGH –2tU–4tU–4tU
MID LOW –1tU–2tU–2tU
MID MID 0tU0tU0tU
MID HIGH +1tU+2tU+2tU
HIGH LOW +2tU+4tU+4tU
HIGH MID +3tU+6tU+6tU
HIGH HIGH +4tUDivide by 4 Inverted
Notes:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW
indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating fre-
quency (fNOM) of the VCO and Time Unit Generator (see Logic Block
Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be fNOM
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition
upon powe r- up until VCC has reached 4.3V.
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 3 of 15
Test Mode
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B991 /CY7B9 92 to o perate as ex plain ed brie fly a bove ( for
test in g pu rp os es , an y of t h e thr e e -le ve l in put s ca n ha v e a re -
movable jumper to ground, or be tied LOW through a 100Ω
resistor. This will allow an external tester to change the state
of these pins. )
If the TEST input is forced to its MID or H IGH sta te, the device
will operate with its internal phase locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.
Maximum Ratings
(Above w hi ch the usef ul l ife m ay be im pai red. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temper atu re with
Power Applied............................................–55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................64 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[4]
t
0
– 6t
U
t
0
– 5t
U
t
0
– 4t
U
t
0
– 3t
U
t
0
– 2t
U
t
0
– 1t
U
t
0
t
0
+1t
U
t
0
t
0
t
0
t
0
t
0
+2t
U
+3t
U
+4t
U
+5t
U
+6t
U
FBInput
REFInput
– 6t U
– 4t U
– 3t U
– 2t U
– 1t U
0tU
+1tU
+2tU
+3tU
+4tU
+6tU
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
7B991–3
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
Military[5] –55°C to +125°C 5V ± 10%
Notes:
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
MID).
5. Indicates case temperature.
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 4 of 15
Electrical Characteristi cs Ov er the Op erating Ran ge[6]
CY7B991 CY7B992
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –16 mA 2.4 V
VCC = Min., IOH =–40 mA VCC–0.75
VOL Output LOW Voltage VCC = Min., IOL = 46 mA 0.45 V
VCC = Min., IOL = 46 mA 0.45
VIH Input HIGH Voltage
(REF and FB inputs only) 2.0 VCC VCC –
1.35 VCC V
VIL Input LOW Voltage
(REF and FB inputs only) –0.5 0.8 –0.5 1.35 V
VIHH Three-Level Input HIGH
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. VCC – 0.85 VCC VCC – 0.85 VCC V
VIMM Three-Level Input MID
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. VCC/2 –
500 mV VCC/2 +
500 mV VCC/2 –
500 mV VCC/2 +
500 mV V
VILL Three-Level Input LOW
Voltage (Test, FS, xFn)[7] Min. ≤ VCC ≤ Max. 0.0 0.85 0.0 0.85 V
IIH Input HIGH Leakage Current
(REF and FB inputs only) VCC = Max., VIN = Max. 10 10 µA
IIL Input LOW Leakage Current
(REF and FB inputs only) VCC = Max., VIN = 0.4V –500 –500 µA
IIHH Input HIGH Current
(Test, FS, xFn) VIN = VCC 200 200 µA
IIMM Input MID Current
(Test, FS, xFn) VIN = VCC/2 –50 50 –50 50 µA
IILL Input LOW Current
(Test, FS, xFn) VIN = GND –200 –200 µA
IOS Output Short Circuit
Current[8] VCC = Max., VOUT
= GND (25 °C only) –250 N/A mA
ICCQ Operating Current Used by
Internal Circuitry VCCN = V CCQ =
Max., All Input
Selects Open
Com’l85 85 mA
Mil/Ind 90 90
ICCN Output Buffer Cur rent per
Output Pair[9] VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
14 19 mA
PD Power Dissipati on per
Output Pair[10] VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
78 104[11] mW
Notes:
6. See the last pag e of this speci fic at ion for Gro up A sub gro up test ing in for ma tion .
7. These inputs are normally wired to VCC, GND, or left un conn ected (a ctua l thres hold volta ges va ry as a per cent age of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all datasheet limits are achieved.
8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only . CY7B992 outputs
should not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B991: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 5 of 15
Capacitance[12]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz, VCC = 5.0V 10 pF
Note:
12. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
7B991–47B991–5
TTL ACTest Load (CY7B991) TTL Input Test Waveform (CY7B991)
5V
R1
R2
CL
R1
R2
CL
7B991–6
CMOS AC Test Load (CY7B992)
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns ≤1ns
2.0V
0.8V
Vth =1.5V
80%
Vth =V
CC/2
20%
0.0V
≤3ns ≤3ns
80%
20%
Vth =V
CC/2
7B991–7
CMOS InputTest Waveform (CY7B992)
VCC
R1=130
R2=91
CL=50pF(C
L=30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
R1=100
R2=100
CL=50pF(C
L
(Includes fixture and probe capacitance)
VCC
=30 pF for –2 and –5 devices)
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 6 of 15
Switching Characteristics Over the Operating Range[2, 13]
CY7B991–2[14] CY7B992–2[14]
Parameter Description Min. Typ. Max. Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2 , 3] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Pulse Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.05 0.20 0.05 0.20 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18,19] 0.1 0.25 0.1 0.25 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs) [16, 20] 0.25 0.5 0.25 0.5 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20] 0.3 0.5 0.3 0.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs) [16, 20] 0.25 0.5 0.25 0.5 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20] 0.5 0.9 0.5 0.7 ns
tDEV Device-to-Device Skew[14, 21] 0.75 0.75 ns
tPD Propagation Delay, REF Rise to FB Rise –0.25 0.0 +0.25 –0.25 0.0 +0.25 ns
tODCV Output Duty Cycle Variation[22] –0.65 0.0 +0.65 –0.5 0.0 +0.5 ns
tPWH Output HIGH Time Deviation from 50%[23, 24] 2.0 3.0 ns
tPWL Output LOW Time Deviation from 50%[23, 24 ] 1.5 3.0 ns
tORISE Output Rise Time[23, 25] 0.15 1.0 1.2 0.5 2.0 2.5 ns
tOFALL Output Fall Ti me[23, 25] 0.15 1.0 1.2 0.5 2.0 2.5 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
Note:
13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC T est Loads and Waveforms unless otherwise specified.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 50 pF and terminated with 50Ω to 2.0 6V (CY7B991) or VCC/2 (CY7B9 92).
17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
20. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
or Divide-by-4 mode).
21. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow , etc.)
22. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B991) or VCC/2 (CY7B992).
24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992.
26. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 7 of 15
Switching Characteristics Over the Operating Range[2, 13] (continued)
CY7B991–5CY7B992–5
Parameter Description Min. Typ. Max. Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2 , 3] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Pulse Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18] 0.25 0.5 0.25 0.5 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs) [16, 20] 0.6 0.7 0.6 0.7 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20] 0.5 1.0 0.6 1.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs) [16, 20] 0.5 0.7 0.5 0.7 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20] 0.5 1.0 0.6 1.7 ns
tDEV Device -to-Device Skew[14, 21] 1.25 1.25 ns
tPD Propagation Delay, REF Rise to FB Rise –0.5 0.0 +0.5 –0.5 0.0 +0.5 ns
tODCV Output Duty Cycle Variation[22] –1.0 0.0 +1.0 –1.2 0.0 +1.2 ns
tPWH Output HIGH Time Deviation from 50%[23, 24] 2.5 4.0 ns
tPWL Output LOW Time Deviation from 50%[23, 24] 34.0 ns
tORISE Output Rise Ti me[23, 25] 0.15 1.0 1.5 0.5 2.0 3.5 ns
tOFALL Output Fall Time[23, 25] 0.15 1.0 1.5 0.5 2.0 3.5 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 8 of 15
Switching Characteristics Over the Operating Range[2, 13] (continued)
CY7B991–7CY7B992–7
Parameter Description Min. Typ. Max. Min. Typ. Max. Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Puls e Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18] 0.3 0.75 0.3 0.75 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 20] 0.6 1.0 0.6 1.0 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20] 1.0 1.5 1.0 1.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20] 0.7 1.2 0.7 1.2 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20] 1.2 1.7 1.2 1.7 ns
tDEV Devi ce - to- D e vic e Skew[14, 21] 1.65 1.65 ns
tPD Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 –0.7 0.0 +0.7 ns
tODCV O utput Duty Cycle Variation[22] –1.2 0.0 +1.2 –1.5 0.0 +1.5 ns
tPWH Output HIGH T ime Deviation from 50%[23, 24] 35.5 ns
tPWL Output LOW T ime Deviati on from 50% [23, 24] 3.5 5.5 ns
tORISE Output Rise Time[23, 25] 0.15 1.5 2.5 0.5 3.0 5.0 ns
tOFALL Output Fall Time[23, 25] 0.15 1.5 2.5 0.5 3.0 5.0 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 9 of 15
AC Timing Diagrams
tODCV
tODCV
tREF
REF
FB
Q
OTHERQ
INVER T ED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
7B991–8
tRPWH
tRPWL
tPD
tSKEWPR,
tSKEW0,1tSKEWPR,
tSKEW0,1
tSKEW2 tSKEW2
tSKEW3,4tSKEW3,4tSKEW3,4
tSKEW1,3, 4tSKEW2,4
tJR
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 10 of 15
Operational Mode Descriptions
Figure 2 shows the PSCB configured as a zero-skew clock
buffer. In this mode the 7B991/992 can be used as the basis
for a low-skew clock distribution tree. When all of the function
select inputs (xF0, xF1) are left open, the outputs are aligned
and may each drive a termin ated tra nsmiss ion li ne to an inde-
pendent load. The FB input can be tied to any output in this
configuration and the operating frequency range is selected
with the FS pin. The low-skew specification, coupled with the
ability to drive termi nated transmi ssion lines (with impedance s
as low as 50 ohms), allows efficient printed circuit board de-
sign.
Figure 3 shows a configuration to equalize skew between met-
al traces of different lengths. In addition to low skew between
outp uts, the P SCB ca n be prog ram med t o stag ger the t imi ng
of its outputs. The four groups of output pairs can each be
programmed to different output timing. Skew timing can be
adjusted over a wide range in small increments with the appro-
priate strapping of the function select pins. In this configuration
the 4Q0 output is fe d back to FB and configured fo r zero skew .
The other three pairs of outputs are programmed to yield dif-
ferent skews relative to the feedback. By advancing the clock
signal on the longer traces or retarding the clock signal on
shorter traces, all loads can receive the clock pulse at the
same time.
In this illustration the FB input is connected to an output with
0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn-
chroniz es the FB and REF inputs and aligns the ir rising ed ges
to insure that all outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tU) when using
an output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and since the PLL aligns the rising edges of REF and FB,
it is possible to create wider output skews by proper selection of the
xFn inputs. For example a +10 tU between REF and 3Qx can be
achieved by connecting 1Q0 to FB and s etting 1F0 = 1F1 = GN D,
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
SYSTEM
CLOCK
L1
L2
L3
L4
LENGTH L1 = L2 = L3 = L4 7B991–9
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z0
LOAD
LOAD
LOAD
LOAD
REF
Z0
Z0
Z0
Figure 3. Programmable-Skew Clock Driver
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches 7B991–10
SYS–
TEM
CLOCK
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
Z0
LOAD
LOAD
LOAD
LOAD
REF
Z0
Z0
Z0
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 11 of 15
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx
skews to +6 tU, a total of +10 tU skew is realized.) Many other con-
figurations can be realized by skew ing both the output used as the
FB input and skewing the other outputs.
Figure 4 sh ows an exampl e of the invert functio n of the PSCB.
In this example the 4Q0 output used as the FB input is pro-
grammed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew . When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q out-
puts to bec ome the “inverted” outputs w ith respe ct to the REF
input. By selectin g which out put is connect to FB, i t is poss ible
to have 2 inverted and 6 non-inverted outputs or 6 inverted and
2 non-in verted outputs. The correct configuration would be de-
termine d by the need for more (or fewer ) inverted outputs . 1Q,
2Q, and 3Q outputs can also be skewed to compensate for
varying trace delays independent of inversion on 4Q.
Figure 5 illustrates the PSCB configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is fed
back to FB. This cau ses the PLL to in crease its fre quency unti l
the 3Q0 an d 3Q1 ou tputs a re lo cked at 20 MHz w hile the 1Qx
and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, which results in a 40-MHz wave-
form at these outputs. Note that the 20- and 40-MHz clocks fall
simult aneous ly an d are ou t of pha se on t heir ris ing ed ge. Thi s
will allow the designer to use the rising edges of the 1⁄2 fre-
quency and 1⁄4 frequency outputs without concern for ris-
ing-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at
80 MHz and are skewed by programming their select inputs
accordingly . Note that the FS pin is wired for 80-MHz operation
because that is the frequency of the fastest output.
Figure 6 demons trates the PSCB in a clock di vider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
output s a re al ign ed. This all ows u se of the rising edge s of th e
1⁄2 frequency and 1⁄4 frequency without concern for skew
mismatch. The 1Qx outputs are programmed to zero skew and
are ali gned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15- to 30-MHz range
since the hig hes t frequ enc y output is runnin g at 20 MHz.
Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx out put s. Thes e inclu de inv erted ou tputs an d
outputs t hat offer divide-by-2 and divide-by-4 timing . An invert-
ed output allows the system designer to clock different sub-
systems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function allows
the two subsystems to each be clocked 180 degrees out of
phase, but still to be aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without th is feature, an exte rnal divider wou ld need to be add-
ed, and the propagation delay of the divider would add to the
skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
allow the PSCB to multiply the clock rate at the REF input by
either two or four. This mode will enable the designer to dis-
tribute a low-frequency clock between various portions of the
system , and then lo cally multip ly the clock rate to a more sui t-
able fre quenc y, w hile still maintai ning the l ow-s kew c haract er-
istics of the cl ock driver . The PSCB can perform all of the func -
tions des cribed above at the sam e time. It can mul tiply by two
and four or divide by two (and four) at the same time that it is
shiftin g its outpu ts over a wide range or main taining zero skew
between selected outputs.
Figure 4. Inverted Output Connections
Figure 5. Frequency Multiplier with Skew Connections
7B991–11
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
7B991–12
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
20 MHz
40 MHz
80 MHz
Figure 6. Frequency Divider Connections
7B991–13
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
20 MHz
5 MHz
10 MHz
20 MHz
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 12 of 15
Figure 8 s how s the CY7B 991 /99 2 c on nec te d i n s eri es to co n-
struct a zero-skew clock dis tribution tree between boards. D e-
lays of the downstream clock buffers can be programmed to
compensate for the wire length (i.e., select negative skew
equal to the wire delay) necessary to connect them to the mas-
ter clock source, approximating a zero-delay clock tree. Cas-
caded clock buffers will accumulate low-frequency jitter be-
cause of the non-i deal fi ltering charac teristi cs of the PLL fi lter.
It is recommended that not more than two clock buffers be
connected in series.
Figure 7. Multi-Function Clock Driver
Figure 8. Board-to-Board Clock Distribution
20–MHz
DISTRIBUTION
CLOCK
80-MHz
INVERTED
Z0
7B991–14
20-MHz
80-MHz
ZERO SKEW
80-MHz
SKEWED –3.125 ns (–4tU)
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF LOAD
LOAD
LOAD
LOAD
Z0
Z0
Z0
SYSTEM
CLOCK
Z0
L1
L2
L3
L4
7B991–15
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z0
Z0
Z0
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 13 of 15
MILITAR Y SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Accuracy
(ps) Ordering Code Package
Name Package Type Operating
Range
250 CY7B991–2JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
500 CY7B991–5JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7B991–5JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
750 CY7B991–7JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7B991–7JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7B991–7LMB L55 32-Pin R ectangul ar Leadless Chip Ca rrier Military
250 CY7B992–2JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
500 CY7B992–5JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7B992–5JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
750 CY7B992–7JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7B992–7JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7B992–7LMB L55 32-Pin R ectangul ar Leadless Chip Ca rrier Military
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
VIHH 1, 2, 3
VIMM 1, 2, 3
VILL 1, 2, 3
IIH 1, 2, 3
IIL 1, 2, 3
IIHH 1, 2, 3
IIMM 1, 2, 3
IILL 1, 2, 3
ICCQ 1, 2, 3
ICCN 1, 2, 3
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 14 of 15
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
32-Lead Plastic Leaded Chip Carrier
32-Pin Rectangul ar Leadle ss Chip Carrier
MIL-STD-1835 C-12
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 15 of 15
Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer (PSCB)
Document Number: 38-07138
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110247 12/19/01 SZV Change from Spec number: 38-00513 to 38-07138
