General Description
The DS17285, DS17485, DS17885, DS17287, DS17487,
and DS17887 real-time clocks (RTCs) are designed to
be successors to the industry-standard DS12885 and
DS12887. The DS17285, DS17485, and DS17885 (here-
after referred to as the DS17x85) provide a real-time
clock/calendar, one time-of-day alarm, three maskable
interrupts with a common interrupt output, a program-
mable square wave, and 114 bytes of battery-backed
NV SRAM. The DS17x85 also incorporates a number
of enhanced functions including a silicon serial number,
power-on/off control circuitry, and 2k, 4k, or 8kbytes of
battery-backed NV SRAM. The DS17287, DS17487, and
DS17887 (hereafter referred to as the DS17x87) integrate
a quartz crystal and lithium energy source into a 24-pin
encapsulated DIP package. The DS17x85 and DS17x87
power-control circuitry allows the system to be powered
on by an external stimulus such as a keyboard or by a
time-and-date (wake-up) alarm. The PWR output pin is
triggered by one or either of these events, and is used to
turn on an external power supply. The PWR pin is under
software control, so that when a task is complete, the
system power can then be shut down.
For all devices, the date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including correction for leap years. It also operates in
either 24-hour or 12-hour format with an AM/PM indicator.
A precision temperature-compensated circuit monitors
the status of VCC. If a primary power failure is detected,
the device automatically switches to a backup supply. A
lithium coin cell battery can be connected to the VBAT
input pin on the DS17x85 to maintain time and date oper-
ation when primary power is absent. The DS17x85 and
DS17x87 include a VBAUX input used to power auxiliary
functions such as PWR control. The device is accessed
through a multiplexed byte-wide interface.
Applications
Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
Features
Incorporates Industry-Standard DS12887 PC
Clock Plus Enhanced Functions
RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap Year Compensation
Through 2099
Optional +3.0V or +5.0V Operation
SMI Recovery Stack
64-Bit Silicon Serial Number
Power-Control Circuitry Supports System Power-
On from Date/Time Alarm or Key Closure
Crystal Select Bit Allows Operation with 6pF or
12.5pF Crystal
12-Hour or 24-Hour Clock with AM and PM in
12-Hour Mode
114 Bytes of General-Purpose, Battery-Backed NV
SRAM
Extended Battery-Backed NV SRAM
2048 Bytes (DS17285/DS17287)
4096 Bytes (DS17485/DS17487)
8192 Bytes (DS17885/DS17887)
RAM Clear Function
Interrupt Output with Six Independently Maskable
Interrupt Flags
Time-of-Day Alarm Once per Second to Once per
Day
End of Clock Update Cycle Flag
Programmable Square-Wave Output
Automatic Power-Fail Detect and Switch Circuitry
Available in PDIP, SO, or TSOP Package
(DS17285, DS17485, DS17885)
Optional Encapsulated DIP (EDIP) Package with
Integrated Crystal and Battery (DS17287,
DS17487, DS17887)
Optional Industrial Temperature Range Available
Underwriters Laboratory (UL) Recognized
19-5222; Rev 2; 5/16
Ordering Information, Pin Configurations, and Typical
Operating Circuit appear at end of data sheet.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Voltage Range on VCC Pin Relative to Ground ...-0.3V to +6.0V
Operating Temperature Range (Noncondensing)
Commercial.........................................................0°C to +70°C
Industrial ......................................................... -40°C to +85°C
Storage Temperature Range
EDIP ............................................................... -40°C to +85°C
PDIP, SO, TSOP ........................................... -55°C to +125°C
Lead Temperature (soldering, 10s) .................................+260°C
(Note: EDIP is hand or wave-soldered only.)
Soldering Temperature (reflow) ....................................... +260°C
(VCC = +4.5V to +5.5V, or VCC = +2.7V to +3.7V, TA = Over the operating temperature range, unless otherwise noted. Typical
values are with TA = +25°C, VCC = 5.0V or 3.0V and VBAT = 3.0V, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage (Note 3) VCC
(-5) 4.5 5.0 5.5 V
(-3) 2.7 3.0 3.7
VBAT Input Voltage VBAT (Note 3) 2.5 3.0 3.7 V
VBAUX Input Voltage (Note 3) VBAUX
(-5) 2.5 3.0 5.2 V
(-3) 3.7
Input Logic 1 (Note 3) VIH
(-5) 2.2 VCC +
0.3 V
(-3) 2.0 VCC +
0.3
Input Logic 0 (Note 3) VIL
(-5) -0.3 +0.8 V
(-3) -0.3 +0.6
VCC Power-Supply Current
(Note 4) ICC1
(-5) 25 50 mA
(-3) 15 30
VCC Standby Current (Notes 4, 5) ICCS
(-5) 1.0 3.0 mA
(-3) 0.5 2.0
Input Leakage IIL -1.0 +1.0 µA
I/O Leakage IOL (Note 6) -1.0 +1.0 µA
Output Logic 1 Voltage (Note 3) VOH
(-5), -1.0mA 2.4 V
(-3), -0.4mA 2.4
Output Logic 0 Voltage
AD0–AD7, IRQ, SQW (Note 3) VOL
(-5), +2.1mA 0.4 V
(-3), +0.8mA 0.4
Output Logic 0 Voltage
PWR (Note 3) VOL
(-5), +10mA 0.4 V
(-3), +4mA 0.4
Power-Fail Voltage (Note 3) VPF
(-5) 4.25 4.37 4.5 V
(-3) 2.5 2.6 2.7
VRT Trip Point VRTTRIP (Note 3) 1.3 V
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
2
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(VCC = 0V, VBAT = 3.0V, TA = Over the operating range, unless otherwise noted.) (Note 1)
(VCC = +4.5V to +5.5V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VBAT or VBAUX Current
(Oscillator On); TA = +25°C,
VBAT = 3.0V
IBAT (Note 7) 500 700 nA
VBAT or VBAUX Current
(Oscillator Off) IBATDR (Note 7) 50 400 nA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Cycle Time tCYC 240 DC ns
Pulse Width, RD or WR Low PWRWL 120 ns
Pulse Width, RD or WR High PWRWH 80 ns
Input Rise and Fall tR, tF30 ns
Chip-Select Setup Time Before
RD or WR tCS 20 ns
Chip-Select Hold Time tCH 0 ns
Read-Data Hold Time tDHR 10 50 ns
Write-Data Hold Time tDHW 0 ns
Address Setup Time to ALE Fall tASL 20 ns
Address Hold Time to ALE Fall tAHL 10 ns
RD or WR High Setup to ALE
Rise tASD 25 ns
Pulse Width ALE High PWASH 40 ns
Delay Time ALE Low to RD Low tASED 30 ns
Output Data Delay Time from RD tDDR (Note 8) 20 120 ns
Data Setup Time tDSW 30 ns
IRQ Release from RD tIRD 2 µs
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
3
DC Electrical Characteristics
AC Electrical Characteristics
(VCC = +2.7V to +3.7V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Cycle Time tCYC 360 DC ns
Pulse Width, RD or WR Low PWRWL 200 ns
Pulse Width, RD or WR High PWRWH 150 ns
Input Rise and Fall tR, tF30 ns
Chip-Select Setup Time Before
RD or WR tCS 20 ns
Chip-Select Hold Time tCH 0 ns
Read-Data Hold Time tDHR 10 90 ns
Write-Data Hold Time tDHW 0 ns
Address Setup Time to ALE Fall tASL 40 ns
Address Hold Time to ALE Fall tAHL 10 ns
RD or WR High Setup to ALE
Rise tASD 30 ns
Pulse Width ALE High PWASH 40 ns
Delay Time ALE Low to RD Low tASED 30 ns
Output Data Delay Time from RD tDDR (Note 8) 20 200 ns
Data Setup Time tDSW 70 ns
IRQ Release from RD tIRD 2 µs
PWASH
tASED
PWRWH PWRWL
tCS
tAHL
tASL tDSW tDHW
tCH
tASD
tASD
tCYC
CS
WR
AS
RD
AD0–AD7
WRITE
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
4
AC Electrical Characteristics
Write Timing
AD0–AD7
CS, WR, RD
HIGH IMPEDANCE
DON'T CARE
VALID
RECOGNIZED RECOGNIZED
VALID
VCC
tF
VPF(MAX)
VPF(MIN)
tREC
tR
tASL tDDR
PWASH
CS
WR
ALE
RD
AD0–AD7
tASD
PWRWL
tCS
tDHR
tAHL
tCH
tCYC
PWRWH
tASED
IRQ
tIRD
tASD
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
5
Power-Up/Power-Down Timing
Read Timing
Note 1: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations not used to prevent damage to the crystal.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: All outputs are open.
Note 5: Specified with CS = RD = WR = VCC, ALE, AD0–AD7 = 0.
Note 6: Applies to the AD0–AD7 pins, IRQ, and SQW when each is in a high-impedance state.
Note 7: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8: Measured with a 50pF capacitance load plus 1TTL gate.
Note 9: If the oscillator is disabled in software, or if the countdown chain is in reset, tREC is bypassed, and the part becomes
immediately accessible.
Note 10: Guaranteed by design. Not production tested.
(TA = -40°C to +85°C) (Note 2)
(TA = +25°C)
(TA = +25°C) (Note 10)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Recovery at Power-Up tREC (Note 9) 20 150 ms
VCC Fall Time, VPF(MAX) to
VPF(MIN)
tF300 µs
VCC Fall Time, VPF(MAX) to
VPF(MIN)
tR0 µs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Expected Data Retention tDR (Note 9) 10 Years
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capacitance on All Input Pins
Except X1 CIN (Note 10) 12 pF
Capacitance on IRQ, SQW, and
DQ0–DQ7 Pins CIO (Note 10) 12 pF
PARAMETER CONDITIONS
Input Pulse Levels: 0 to 3.0V
Output Load Including Scope and Jig: 50pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels: Input/Output: VIL max and VIH min
Input Pulse Rise and Fall Times: 5ns
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
6
Power-Up/Power-Down Characteristics
Data Retention (DS17x87 Only)
Capacitance
AC Test Conditions
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode can cause loss of data.
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PIN NAME FUNCTION
24 28
1 8 PWR
Active-Low Power-On Reset. This open-drain output pin is intended for use as an on/off control
for the system power. With VCC voltage removed from the device, PWR can be automatically
activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the system is
powered on, the state of PWR can be controlled by bits in the control registers. The PWR pin
can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage
of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup
supply should be no greater than 3.9V.
2, 3 9, 10 X1, X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed
for operation with a crystal having a specied load capacitance (CL) of 6pF or 12.5pF. Pin X1 is
the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator.
The output of the internal oscillator, pin X2, is left unconnected if an external oscillator is
connected to pin X1. These pins are missing (N.C.) on the EDIP package.
4–11 12–17,
19, 20 AD0–AD7
Multiplexed Bidirectional Address/Data Bus. The addresses are presented during the rst
portion of the bus cycle and latched into the device by the falling edge of ALE. Write data is
latched by the rising edge of WR. In a read cycle, the device outputs data during the latter
portion of the RD low. The read cycle is terminated and the bus returns to a high-impedance
state as RD transitions high.
12, 16 21, 22, 26 GND Ground
SUPPLY CURRENT
vs. TEMPERATURE
DS17285/87 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
65503520
5
-10-25
300
350
400
250
-40 80
VBAT = 3.0V
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
DS17285/87 toc03
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (Hz)
5.04.54.03.53.0
32768.1
32768.2
32768.3
32768.4
32768.5
32768.6
32768.7
32768.0
2.5 5.5
SUPPLY CURRENT
vs. INPUT VOLTAGE
DS17285/87 toc01
VBAT (V)
SUPPLY CURRENT (nA)
3.53.33.02.8
250
300
350
400
200
2.5 3.8
VCC = 0V
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
7
Typical Operating Characteristics
Pin Description
PIN NAME FUNCTION
24 28
13 23 CS
Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the device
to be accessed. CS must be kept in the active state during RD and WR. Bus cycles that take
place without asserting CS latch addresses, but no access occurs.
14 24 ALE Address Latch Enable Input, Active High. This input pin is used to demultiplex the address/data
bus. The falling edge of ALE causes the address to be latched within the device.
15 25 WR Active-Low Write Input. This pin denes the period during which data is written to the
addressed register.
17 27 RD Active-Low Read Input. This pin identies the period when the device drives the bus with read
data. It is an enable signal for the output buffers of the device.
18 28 KS
Active-Low Kickstart Input. When VCC is removed from the device, the system can be powered
on in response to an active-low transition on the KS pin, as might be generated from a key
closure. VBAUX must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the
kickstart function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC
is applied, the KS pin can be used as an interrupt input. If not used, KS must be grounded and
ABE set to 0.
19 1 IRQ
Active-Low Interrupt Request. This pin is an active-low output that can be used as an interrupt
input to a processor. The IRQ output remains low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the application
software must clear all enabled ag bits contributing to the pin’s active state. When no interrupt
conditions are present, the IRQ level is in the high-impedance state. Multiple interrupting
devices can be connected to an IRQ bus, provided that they are all open drain. The IRQ pin
requires an external pullup resistor to VCC.
20 2 VBAT
Connection for Primary Battery. This supply input is used to power the normal clock functions
when VCC is absent. Diodes placed in series between VBAT and the battery can prevent proper
operation. If VBAT is not required, the pin must be grounded. UL recognized to ensure against
reverse charging current when used with a lithium battery (www.maximintegrated.com/qa/
info/ul). This pin is missing (N.C.) on the EDIP package.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
8
Pin Description (continued)
PIN NAME FUNCTION
24 28
21 3 RCLR
Active-Low RAM Clear Input. This pin is used to clear (set to logic 1) all the 114 bytes of
general-purpose RAM but does not affect the RAM associated with the real time clock or
extended RAM. RCLR may be invoked while the part is powered from any supply. The RCLR
function is designed to be used via a human interface (shorting to ground manually or by a
switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an
external pullup resistor on this pin.
22 4 VBAUX
Auxiliary Battery Input. Required for kickstart and wake-up functions. This input also supports
clock/calendar and user RAM if VBAT is at lower voltage or is not used. A standard +3V lithium
cell or other energy source can be used. Diodes placed in series between VBAUX and the
battery may prevent proper operation. UL recognized to ensure against reverse charging
current when used with a lithium battery (www.maximintegrated.com/qa/info/ul/). For 3V
VCC operation, VBAUX must be held between +2.5V and +3.7V. For 5V VCC operation, VBAUX
must be held between +2.5V and +5.2V. If VBAUX is not used it should be grounded and the
auxiliary-battery-enable bit bank 1, register 4BH, should = 0.
23 5 SQW
Square-Wave Output. When VCC rises above VPF, bits DV1 and E32k are set to 1. This
condition enables a 32kHz square-wave output. A square wave is output if either SQWE = 1
or E32k = 1. If E32k = 1, then 32kHz is output regardless of the other control bits. If E32k =
0, then the output frequency is dependent on the control bits in Register A. The SQW pin can
output a signal from one of 13 taps provided by the 15 internal divider stages of the RTC. The
frequency of the SQW pin can be changed by programming Register A, as shown in Table 3.
The SQW signal can be turned on and off using the SQWE bit in Register B or the E32k bit
in extended register 4Bh. A 32kHz square wave is also available when VCC is less than VPF
if E32k = 1, ABE = 1, and voltage is applied to the VBAUX pin. When disabled, SQW is high
impedance when VCC is below VPF.
24 6, 7 VCC
DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the device
is fully accessible and data can be written and read. When VCC is below VPF reads and writes
are inhibited.
2, 3,
16, 20
(DS17x87
only)
11, 18 N.C. No Connection
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
9
Pin Description (continued)
Figure 1. Functional Diagram
X1
OSCILLATOR
POWER
CONTROL
X2
DS17x87
ONLY
VBAT
GND
DIVIDE
BY 8
REGISTERS A, B, C, D
CLOCK/CALENDAR
UPDATE LOGIC
EXTENDED
USER RAM
2k/4k/8k
BYTES
SELECT
EXTENDED RAM ADDR/
DATA REGISTERS
EXTENDED CONTROL/
STATUS REGISTERS
64-BIT SERIAL NUMBER
CENTURY COUNTER
DATE ALARM
RTC ADDRESS-2
RTC ADDRESS-3
DIVIDE BY
64
DIVIDE BY
64
16:1 MUX
SQUARE-
WAVE
GENERATOR
SQW
IRQ
PWR
KS
RLCR
IRQ
GENERATOR
VCC
VBAUX
BUS
INTERFACE
CS
WR
RD
ALE
AD0–AD7
CLOCK/CALENDAR AND
ALARM REGISTERS
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
USER RAM
114 BYTES
RAM
CLEAR
LOGIC
DS17x85/87
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
10
Detailed Description
The DS17x85 is a successor to the DS1285 real-time
clock (RTC). The device provides 18 bytes of real-time
clock/calendar, alarm, and control/status registers and 114
bytes of nonvolatile battery-backed RAM. The device also
provides additional extended RAM in either 2k/4k/8kbytes
(DS17285/DS17485/DS17885). A time-of-day alarm, six
maskable interrupts with a common interrupt output, and
a programmable square-wave output are available. It also
operates in either 24-hour or 12-hour format with an AM/
PM indicator. A precision temperature-compensated cir-
cuit monitors the status of VCC. If a primary power-supply
failure is detected, the device automatically switches to
a backup supply. The backup supply input supports a
primary battery, such as a lithium coin cell. The device is
accessed by a multiplexed address/data bus.
Oscillator Circuit
The DS17x85 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crystal
parameters for the external crystal, and Figure 2 shows
a functional schematic of the oscillator circuit. The oscil-
lator is controlled by an enable bit in the control register.
Oscillator startup times are highly dependent upon crystal
characteristics, PC board leakage, and layout. High ESR
and excessive capacitive loads are the major contributors
to long startup times. A circuit using a crystal with the
recommended characteristics and proper layout usually
starts within one second.
An external 32.768kHz oscillator can also drive the
DS17x85. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is left
unconnected.
Clock Accuracy
The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capaci-
tive load for which the crystal was trimmed. Additional
error will be added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit may result in the clock running fast.
Figure 3 shows a typical PC board layout for isolation of
the crystal and oscillator from noise. Refer to Application
Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information.
Clock Accuracy (DS17287,
DS17487, and DS17887)
The encapsulated DIP (EDIP) modules are trimmed at the
factory to ±1 minute per month accuracy at 25°C.
Figure 2. Oscillator Circuit Showing Internal Bias Network
Figure 3. Layout Example
Table 1. Crystal Specifications* (DS17x85
Only)
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for addi-
tional specifications.
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal
Frequency fO32.768 kHz
Series
Resistance ESR 50 kΩ
Load
Capacitance CL
6 or
12.5 pF
COUNTDOWN
CHAIN
X1 X2
CRYSTAL
CL1 CL2RTC REGISTERS
DS17285/87
DS17485/87
DS17885/87
LOCAL GROUND PLANE (TOP LAYER)
CRYSTAL
GND
X2
X1
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
11
Power-Down/Power-Up
Considerations
The RTC function continues to operate, and all the RAM,
time, calendar, and alarm memory locations remain non-
volatile regardless of the level of the VCC input. VBAT or
VBAUX must remain within the minimum and maximum
limits when VCC is not applied. When VCC falls below
VPF, the device inhibits all access, putting the part into
a low-power mode. When VCC is applied and exceeds
VPF (power-fail trip point), the device becomes acces-
sible after tREC, if the oscillator is running and the oscil-
lator countdown chain is not in reset (Register A). This
time period allows the system to stabilize after power
is applied. If the oscillator is not enabled, the oscilla-
tor enable bit is enabled on powerup, and the device
becomes immediately accessible.
Power Control
The power control function is provided by a precise,
temperature-compensated voltage reference and a com-
parator circuit that monitors the VCC level. The device is
fully accessible and data can be written and read when
VCC is greater than VPF. However, when VCC falls below
VPF, the device inhibits read and write access. If VPF is
less than VBAT, the device power is switched from VCC
to the higher of VBAT or VBAUX when VCC drops below
VPF. If VPF is greater than the higher of VBAT or VBAUX,
the device power is switched from VCC to the higher of
VBAT or VBAUX when VCC drops below the higher backup
source. The registers are maintained from the VBAT or
VBAUX source until VCC is returned to nominal levels.
After VCC returns above VPF, read and write access is
allowed after tREC.
Time, Calendar, and Alarm
Locations
The time and calendar information is obtained by read-
ing the appropriate register bytes. The time, calendar,
and alarm are set or initialized by writing the appropriate
register bytes. The contents of the 12 time, calendar, and
alarm bytes can be either binary or binary-coded deci-
mal (BCD) format. Tables 3A and 3B show the BCD and
binary formats of the 12 time, date, and alarm registers,
control registers A to D, plus the two extended registers
that reside in bank 1 only (bank 0 and bank 1 switching is
explained later in this text).
The day-of-week register increments at midnight, incre-
menting from 1 through 7. The day-of-week register is
used by the daylight saving function, and so the value 1
is defined as Sunday. The date at the end of the month
is automatically adjusted for months with fewer than 31
days, including correction for leap years.
Before writing the internal time, calendar, and alarm
registers, the SET bit in Register B should be written to
logic 1 to prevent updates from occurring while access is
being attempted. In addition to writing the 12 time, calen-
dar, and alarm registers in a selected format (binary or
BCD), the data mode bit (DM) of Register B must be set
to the appropriate logic level. All 12 time, calendar, and
alarm bytes must use the same data mode. The set bit in
Register B should be cleared after the data mode bit has
been written to allow the real time clock to update the time
and calendar bytes. Once initialized, the real time clock
makes all updates in the selected mode. The data mode
cannot be changed without reinitializing the 12 data bytes.
Tables 3A and 3B show the BCD and binary formats of the
12 time, calendar, and alarm locations.
The 24-12 bit cannot be changed without reinitializing the
hour locations. When the 12-hour format is selected, the
high order bit of the hours byte represents PM when it is
logic 1. The time, calendar, and alarm bytes are always
accessible because they are double-buffered. Once per
second, the eight bytes are advanced by one second and
checked for an alarm condition.
If a read of the time and calendar data occurs during an
update, a problem exists where seconds, minutes, hours,
etc., may not correlate. The probability of reading incor-
rect time and calendar data is low. Several methods of
avoiding any possible incorrect time and calendar reads
are covered later in this text.
Table 2. Power Control
SUPPLY CONDITION READ/WRITE
ACCESS POWERED BY
VCC < VPF, VCC <
(VBAT | VBAUX)No VBAT or VBAUX
VCC < VPF, VCC >
(VBAT | VBAUX)No VCC
VCC > VPF, VCC <
(VBAT | VBAUX)Yes VCC
VCC > VPF, VCC >
(VBAT | VBAUX)Yes VCC
DS17285/DS17287/
DS17485/DS17487/
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The alarm bytes can be used in two ways. First, when the
alarm time is written in the appropriate hours, minutes, and
seconds alarm locations, the alarm interrupt is initiated at
the specified time each day, if the alarm enable bit is high.
In this mode, the “0” bits in the alarm registers and the cor-
responding time registers must always be written to 0 (see
Table 3A and 3B). Writing the 0 bits in the alarm and/or time
registers to 1 can result in undefined operation.
The second use condition is to insert a “don’t care” state
in one or more of the alarm bytes. The don’t care code is
any hexadecimal value from C0 to FF. The two most sig-
nificant bits of each byte set the don’t care condition when
at logic 1. An alarm will be generated each hour when the
“don’t care” bits are set in the hours byte. Similarly, an
alarm is generated every minute with don’t care codes in
the hours and minute alarm bytes. An alarm is generated
every second with don’t care codes in the hours, minutes,
and seconds alarm bytes.
All 128 bytes can be directly written or read except for the
following:
1) Registers C and D are read-only.
2) Bit 7 of register A is read-only.
3) The MSB of the seconds byte is read-only.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds reg-
ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
Table 3A. Time, Calendar, and Alarm Data Modes—BCD Mode (DM = 0)
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Seconds Seconds Seconds Alarm 00–59
02h 0 10 Minutes Minutes Minutes 00–59
03h 0 10 Minutes Minutes Minutes Alarm 00–59
04h AM/PM 00 10 Hour Hours Hours 1–12 + AM/PM
00–23
0 10 Hour
05h AM/PM 00 10 Hour Hours Hours Alarm 1–12 + AM/PM
00–23
0 10 Hour
06h 0 0 0 0 0 Day Day 01–07
07h 0 0 10 Date Date Date 01–31
08h 0 0 0 10 Month Month Month 01–12
09h 10 Year Year Year 00–99
0Ah UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 Control
0Bh SET PIE AIE UIE SQWE DM 24/12 DSE Control
0Ch IRQF PF AF UF 0 0 0 0 Control
0Dh VRT 0 0 0 0 0 0 0 Control
Bank 1, 48h 10 Century Century Century 00–99
Bank 1, 49h 10 Date Date Date Alarm 01–31
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Control Registers
The four control registers (A, B, C, and D) reside in both
bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Bit 7: Update In Progress (UIP). This bit is a status flag
that can be monitored. When the UIP bit is 1, the update
transfer will soon occur. When UIP is 0, the update trans-
fer does not occur for at least 244μs. The time, calendar,
and alarm information in RAM is fully available for access
when the UIP bit is 0. The UIP bit is read-only. Writing the
SET bit in Register B to 1 inhibits any update transfer and
clears the UIP status bit.
Bits 6, 5, and 4: DV2, DV1, and DV0. These bits are
used to turn the oscillator on or off and to reset the count-
down chain. A pattern of 01X is the only combination of
bits that turns the oscillator on and allows the RTC to keep
time. A pattern of 11X enables the oscillator but holds
the countdown chain in reset. The next update occurs at
500ms after a pattern of 01X is written to DV0, DV1, and
DV2. DV0 is used to select bank 0 or bank 1 as defined in
Table 5. When DV0 is set to 0, bank 0 is selected. When
DV0 is set to 1, bank 1 is selected.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds reg-
ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
Table 3B. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1)
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00h 0 0 Seconds Seconds 00–3B
01h 0 0 Seconds Seconds Alarm 00–3B
02h 0 0 Minutes Minutes 00–3B
03h 0 0 Minutes Minutes Alarm 00–3B
04h AM/PM 0 0 0 Hours Hours 1–0C + AM/PM
00–17
0 Hours
05h AM/PM 0 0 0 Hours Hours Alarm 1–0C + AM/PM
00–17
0 Hours
06h 0 0 0 0 0 Day Day 01–07
07h 0 0 0 Date Date 01–1F
08h 0 0 0 0 Month Month 01–0C
09h 0 Year Year 00–63
0Ah UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 Control
0Bh SET PIE AIE UIE SQWE DM 24/12 DSE Control
0Ch IRQF PF AF UF 0 0 0 0 Control
0Dh VRT 0 0 0 0 0 0 0 Control
Bank 1, 48h 10 Century Century Century 00–63
Bank 1, 49h 10 Date Date Date Alarm 01–1F
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0
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Register A (0Ah)
Bits 3 to 0: Rate Selector Bits (RS3 to RS0). These
four rate-selection bits select one of the 13 taps on the
15-stage divider or disable the divider output. The tap
selected can be used to generate an output square wave
(SQW pin) and/or a periodic interrupt. The user can do
one of the following:
1) Enable the interrupt with the PIE bit;
2) Enable the SQW output pin with the SQWE or E32k
bits;
3) Enable both at the same time and the same rate; or
4) Enable neither.
Table 4 lists the periodic interrupt rates and the square-
wave frequencies that can be chosen with the RS bits.
*RS3 to RS0 determine periodic interrupt rates as listed for E32K = 0.
Table 4. Periodic Interrupt Rate and Square-Wave Output Frequency
EXT REG B SELECT BITS REGISTER A tPI PERIODIC INTERRUPT
RATE SQW OUTPUT FREQUENCY
E32K RS3 RS2 RS1 RS0
0 0 0 0 0 None None
0 0 0 0 1 3.90625ms 256Hz
0 0 0 1 0 7.8125ms 128Hz
0 0 0 1 1 122.070Fs 8.192kHz
0 0 1 0 0 244.141Fs 4.096kHz
0 0 1 0 1 488.281Fs 2.048kHz
0 0 1 1 0 976.5625Fs 1.024kHz
0 0 1 1 1 1.953125ms 512Hz
0 1 0 0 0 3.90625ms 256Hz
0 1 0 0 1 7.8125ms 128Hz
0 1 0 1 0 15.625ms 64Hz
0 1 0 1 1 31.25ms 32Hz
0 1 1 0 0 62.5ms 16Hz
0 1 1 0 1 125ms 8Hz
0 1 1 1 0 250ms 4Hz
0 1 1 1 1 500ms 2Hz
1 X X X X * 32.768kHz
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Bit 7: SET. When the SET bit is 0, the update transfer
functions normally by advancing the counts once per sec-
ond. When the SET bit is written to 1, any update transfer
is inhibited, and the program can initialize the time and
calendar bytes without an update occurring in the midst
of initializing. Read cycles can be executed in a similar
manner. SET is a read/write bit and is not affected by any
internal functions of the DS17x85.
Bit 6: Periodic Interrupt Enable (PIE). This bit is a read/
write bit that allows the periodic interrupt flag (PF) bit in
Register C to drive the IRQ pin low. When PIE is set to 1,
periodic interrupts are generated by driving the IRQ pin low
at a rate specified by the RS3–RS0 bits of Register A. A 0
in the PIE bit blocks the IRQ output from being driven by
a periodic interrupt, but the PF bit is still set at the periodic
rate. PIE is not modified by any internal DS17x85 functions.
Bit 5: Alarm Interrupt Enable (AIE). This bit is a read/
write bit that, when set to 1, permits the alarm flag (AF)
bit in Register C to assert IRQ. An alarm interrupt occurs
for each second that the three time bytes equal the three
alarm bytes, including a don’t care alarm code of binary
11XXXXXX. When the AIE bit is set to 0, the AF bit does
not initiate the IRQ signal. The internal functions of the
DS17x285/87 do not affect the AIE bit.
Bit 4: Update-Ended Interrupt Enable (UIE). This bit is
a read/write bit that enables the update-end flag (UF) bit
in Register C to assert IRQ. The SET bit going high clears
the UIE bit.
Bit 3: Square-Wave Enable (SQWE). When this bit is set
to 1 and E32k = 0, a square-wave signal at the frequency
set by RS3–RS0 is driven out on the SQW pin. When the
SQWE bit is set to 0 and E32k = 0, the SQW pin is held
low. SQWE is a read/write bit. SQWE is set to 1 when
VCC is powered up.
Bit 2: Data Mode (DM). This bit indicates whether time
and calendar information is in binary or BCD format. The
program sets the DM bit to the appropriate format and can
be read as required. This bit is not modified by internal
functions. A 1 in DM signifies binary data, while a 0 in DM
specifies binary-coded decimal (BCD) data.
Bit 1: 24/12 Control (24/12). This bit establishes the for-
mat of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write and
is not affected by internal functions.
Bit 0: Daylight Saving Enable (DSE). This bit is a read/
write bit that enables two daylight saving adjustments
when DSE is set to 1. On the first Sunday in April, the
time increments from 1:59:59AM to 3:00:00AM. On
the last Sunday in October when the time first reaches
1:59:59AM, it changes to 1:00:00AM. When DSE is
enabled, the internal logic tests for the first/last Sunday
condition at midnight. If the DSE bit is not set when the
test occurs, the daylight saving function does not operate
correctly. These adjustments do not occur when the DSE
bit is zero. This bit is not affected by internal functions.
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SET PIE AIE UIE SQWE DM 24/12 DSE
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Register B (0Bh)
Bit 7: Interrupt Request Flag (IRQF). This bit is set to 1
when any of the following are true:
PF = PIE = 1 WF = WIE = 1
AF = AIE = 1 KF = KSE = 1
UF = UIE = 1 RF = RIE = 1
Any time the IRQF bit is 1, the IRQ pin is driven low. Flag
bits PF, AF, and UF are cleared after reading Register C.
Bit 6: Periodic Interrupt Flag (PF). This is a read-only bit
that is set to 1 when an edge is detected on the selected
tap of the divider chain. The RS3–RS0 bits establish the
periodic rate. PF is set to 1 independent of the state of the
PIE bit. When both PF and PIE are 1s, the IRQ signal is
active and sets the IRQF bit. Reading Register C clears
this bit.
Bit 5: Alarm Interrupt Flag (AF). A 1 in this bit indicates
that the current time has matched the alarm time. If the
AIE bit is also 1, the IRQ pin goes low and a 1 appears in
the IRQF bit. Reading Register C clears this bit.
Bit 4: Update-Ended Interrupt Flag (UF). This bit is set
after each update cycle. When the UIE bit is set to 1, the
1 in UF causes the IRQF bit to be 1, which asserts IRQ.
Reading Register C clears this bit.
Bits 3 to 0: Unused. These unused bits always read 0
and cannot be written.
Register D (0Dh)
Bit 7: Valid RAM and Time (VRT). This bit indicates
the condition of the battery connected to the VBAT and
VBAUX pin. If either supply is above the internal voltage
threshold, VRTTRIP, the bit will be high. This bit is not
writeable and should always be a 1 when read. If a 0 is
ever present, an exhausted internal lithium energy source
is indicated and both the contents of the RTC data and
RAM data are questionable.
Bits 6 to 0: Unused. These bits cannot be written and,
when read, always read 0.
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IRQF PF AF UF 0 0 0 0
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VRT 0 0 0 0 0 0 0
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Register C (0Ch)
Register D (0Dh)
Nonvolatile RAM
The user RAM bytes are not dedicated to any special
function within the DS17x85. They can be used by the
processor program as battery-backed memory and are
fully available during the update cycle.
The user RAM is divided into two separate memory
banks. When the bank 0 is selected, the 14 real-time
clock registers and 114 bytes of user RAM are acces-
sible. When bank 1 is selected, an additional 2kbytes,
4kbytes, or 8kbytes of user RAM are accessible through
the extended RAM address and data registers.
Interrupts
The RTC includes six separate, fully automatic sources of
interrupt for a processor:
1) Alarm Interrupt
2) Periodic Interrupt
3) Update-Ended Interrupt
4) Wake-Up Interrupt
5) Kickstart Interrupt
6) RAM Clear Interrupt
The conditions that generate each of these independent
interrupt conditions are described in detail in other sec-
tions of this data sheet. This section describes the overall
control of the interrupts.
The application software can select which interrupts, if
any, are to be used. There are 6 bits, including 3 bits
in Register B and 3 bits in Extended Register 4B, that
enable the interrupts. The extended register locations
are described later. Writing logic 1 to an interruptenable
bit permits that interrupt to be initiated when the event
occurs. A logic 0 in the interrupt-enable bit prohibits the
IRQ pin from being asserted from that interrupt condi-
tion. If an interrupt flag is already set when an interrupt
is enabled, IRQ is immediately set at an active level,
although the event initiating the interrupt condition might
have occurred much earlier. Therefore, there are cases
where the software should clear these earlier generated
interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C or in Extended Register 4A.
These flag bits are set regardless of the setting of the
corresponding enable bit located either in Register B or in
Extended Register 4B. The flag bits can be used in a poll-
ing mode without enabling the corresponding enable bits.
However, care should be taken when using the flag bits of
Register C as they are automatically cleared to 0 immedi-
ately after they are read. Double latching is implemented
on these bits so that set bits remain stable throughout the
read cycle. All bits that were set are cleared when read
and new interrupts that are pending during the read cycle
are held until after the cycle is completed. One, two, or
three bits can be set when reading Register C. Each used
flag bit should be examined when read to ensure that no
interrupts are lost.
The flag bits in Extended Register 4A are not automati-
cally cleared following a read. Instead, each flag bit can
be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts,
the IRQ line is driven low when an interrupt flag bit is set
and its corresponding enable bit is also set. IRQ is held
low as long as at least one of the six possible interrupt
sources has its flag and enable bits both set. The IRQF
bit in Register C is 1 whenever the IRQ pin is being driven
low as a result of one of the six possible active sources.
Therefore, determination that the DS17x85/DS17x87 initi-
ated an interrupt is accomplished by reading Register C
and finding IRQF = 1. IRQF remains set until all enabled
interrupt flag bits are cleared to 0.
Oscillator Control Bits
A pattern of 01X in bits 4 to 6 of Register A turns the oscil-
lator on and enables the countdown chain. A pattern of
11X (DV2 = 1, DV1 = 1, DV0 = X) turns the oscillator on,
but holds the countdown chain of the oscillator in reset.
All other combinations of bits 4 to 6 keep the oscillator off.
When the DS17x87 is shipped from the factory, the
internal oscillator is turned off. This feature prevents the
lithium energy cell from being used until it is installed in
a system.
Square-Wave Output Selection
Thirteen of the 15 divider taps are made available to a
1-of-16 multiplexer, as shown in Figure 1. The square
wave and periodic interrupt generators share the output of
the multiplexer. The RS0–RS3 bits in Register A establish
the output frequency of the multiplexer. These frequen-
cies are listed in Table 4. Once the frequency is selected,
the output of the SQW pin can be turned on and off under
program control with the square-wave enable bit (SQWE).
If E32K = 0, the square-wave output is determined by the
RS3 to RS0 bits. If E32K = 1, a 32kHz square wave is
output on the SQW pin, regardless of the RS3 to RS0 bits’
state. If E32K = ABE = 1 and a valid voltage is applied to
VBAUX, a 32kHz square wave is output on SQW when
VCC is below VTP.
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Periodic Interrupt Selection
The periodic interrupt causes the IRQ pin to go to an
active state from once every 500ms to once every 122μs.
This function is separate from the alarm interrupt, which
can be output from once per second to once per day. The
periodic interrupt rate is selected using the same Register
A bits that select the squarewave frequency (see Table 4).
Changing the Register A bits affects both the square-wave
frequency and the periodic interrupt output. However,
each function has a separate enable bit in Register B.
The SQWE and E32k bits control the square-wave output.
Similarly, the periodic interrupt is enabled by the PIE bit in
Register B. The periodic interrupt can be used with soft-
ware counters to measure inputs, create output intervals,
or await the next needed software function.
Update Cycle
The DS17x85 executes an update cycle once per second
regardless of the SET bit in Register B. When the SET
bit in Register B is set to 1, the user copy of the double-
buffered time, calendar, and alarm bytes is frozen and
does not update as the time increments. However, the
time countdown chain continues to update the internal
copy of the buffer. This feature allows time to maintain
accuracy independent of reading or writing the time, cal-
endar, and alarm buffers, and also guarantees that time
and calendar information is consistent. The update cycle
also compares each alarm byte with the corresponding
time byte and issues an alarm if a match or if a don’t care
code is present in all alarm locations.
There are three methods that can handle access of the
RTC that avoid any possibility of accessing inconsistent
time and calendar data. The first method uses the update-
ended interrupt. If enabled, an interrupt occurs after every
update cycle that indicates that over 999ms are available
to read valid time and date information. If this interrupt is
used, the IRQF bit in Register C should be cleared before
leaving the interrupt routine.
A second method uses the update-in-progress (UIP) bit in
Register A to determine if the update cycle is in progress.
The UIP bit pulses once per second. After the UIP bit goes
high, the update transfer occurs 244μs later. If a low is
read on the UIP bit, the user has at least 244μs before the
time/calendar data is changed. Therefore, the user should
avoid interrupt service routines that would cause the time
needed to read valid time/calendar data to exceed 244μs.
The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A
is set high between the setting of the PF bit in Register C
(see Figure 4). Periodic interrupts that occur at a rate of
greater than tBUC allow valid time and date information to
be reached at each occurrence of the periodic interrupt.
The reads should be complete within 1 (tPI/2 + tBUC) to
ensure that data is not read during the update cycle.
Figure 4. UIP and Periodic Interrupt Timing
UIP
UF
PF
tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244µs.
1 SECOND
tPI
tPI/2 tPI/2
tBUC
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Extended Functions
The extended functions provided by the DS17x85/
DS17x87 that are new to the RAMified RTC family
are accessed by a software-controlled bank-switching
scheme, as illustrated in Table 5. In bank 0, the clock/
calendar registers and 50 bytes of user RAM are in the
same locations as for the DS1287. As a result, existing
routines implemented within BIOS, DOS, or application
software packages can gain access to the DS17x85/
DS17x87 clock registers with no changes. Also in bank
0, an extra 64 bytes of RAM are provided at addresses
just above the original locations for a total of 114 directly
addressable bytes of user RAM.
When bank 1 is selected, the clock/calendar registers and
the original 50 bytes of user RAM still appear as bank 0.
However, the extended registers that provide control and
status for the extended functions are accessed in place of
the additional 64 bytes of user RAM. The major extended
functions controlled by the extended registers are listed
below:
• 64-Bit Silicon Serial Number
• Century Counter
• RTC Write Counter
Date Alarm
Auxiliary Battery Control/Status
• Wake-Up
• Kickstart
• RAM Clear Control/Status
• Extended RAM Access
The bank selection is controlled by the state of the DV0 bit in
register A. To access bank 0 the DV0 bit should be written to
a 0. To access bank 1, DV0 should be written to 1. Register
locations designated as reserved in the bank 1 map are
reserved for future use by Dallas Semiconductor. Bits in
these locations cannot be written and return a 0 if read.
Silicon Serial Number
A unique 64-bit lasered serial number is located in bank 1,
registers 40h–47h. This serial number is divided into three
parts. The first byte in register 40h contains a model num-
ber to identify the device type of the DS17x85/DS17x87.
Registers 41h–46h contain a unique binary number.
Register 47h contains a CRC byte used to validate the
data in registers 40h–46h. The CRC polynomial is X8 +
X5 + X4 + 1. See Figure 5. All 8 bytes of the serial number
are read-only registers. The DS17x85/DS17x87 is manu-
factured such that no two devices contain an identical
number in locations 41h–47h.
Figure 5. CRC Polynomial
DEVICE MODEL NUMBER
DS17285/87 72h
DS17485/87 74h
DS17885/87 78h
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
8TH
STAGE
INPUT DATA
POLYNOMIAL = X8 + X5 + X4 + 1
X0 X1 X2 X3 X4 X5 X6 X7 X8
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Note: Reserved bits can be written to any value, but always read back as zeros.
Table 5. Extended Bank Register Bank Definition
Bank 0 Bank 1
DV0 = 0 DV0 = 1
00h
0Dh
Timekeeping and Control
00h
0Dh
Timekeeping and Control
0Eh
3Fh
50 Bytes – User RAM
0Eh
3Fh
50 Bytes – User RAM
40h 40h Model Number Byte
41h 1st Byte Serial Number
42h 2nd Byte Serial Number
43h 3rd Byte Serial Number
44h 4th Byte Serial Number
45h 5th Byte Serial Number
46h 6th Byte Serial Number
47h CRC Byte
48h Century Byte
49h Date Alarm
4Ah Extended Control Register 4A
4Bh Extended Control Register 4B
4Ch Reserved
4Dh Reserved
4Eh RTC Address – 2
4Fh RTC Address – 3
64 Bytes – User RAM 50h Extended RAM Address LSB
51h Extended RAM Address MSB
52h Reserved
53h Extended RAM Data Port
54h Reserved
55h Reserved
56h Reserved
57h Reserved
58h Reserved
59h Reserved
5Ah Reserved
5Bh Reserved
5Ch Reserved
5Dh Reserved
5Eh RTC Write Counter
7Fh
5Fh
7Fh
Reserved
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Century Counter
A register has been added in bank 1, location 48H, to
keep track of centuries. The value is read in either binary
or BCD according to the setting of the DM bit.
RTC Write Counter
An 8-bit counter located in extended register bank 1, 5Eh,
counts the number of times the RTC is written to. This
counter is incremented on the rising edge of the WR sig-
nal every time that the CS signal qualifies it. This counter
is a read-only register and rolls over after 256 RTC write
pulses. This counter can be used to determine if and how
many RTC writes have occurred since the last time this
register was read.
Auxiliary Battery
The VBAUX input is provided to supply power from an
auxiliary battery for the DS17x85/DS17x87 kickstart,
wake-up, and SQW output in the absence of VCC func-
tions. This power source must be available to use these
auxiliary functions when no VCC is applied to the device.
The auxiliary battery enable (ABE; bank 1, register 04BH)
bit in Extended Control Register 4B is used to turn the
auxiliary battery on and off for the above functions in the
absence of VCC. When set to 1, VBAUX battery power
is enabled; when cleared to 0, VBAUX battery power is
disabled to these functions.
In the DS17x85/DS17x87, this auxiliary battery can be
used as the primary backup power source for maintain-
ing the clock/calendar, user RAM, and extended external
RAM functions. This occurs if the VBAT pin is at a lower
voltage than VBAUX. If the DS17x85 is to be backed
up using a single battery with any auxiliary functions
enabled, then VBAUX should be used and VBAT should
be grounded. If VBAUX is not to be used, it should be
grounded and ABE should be cleared to 0.
Wake-Up/Kickstart
The DS17x85/DS17x87 incorporates a wake-up feature
that powers on the system at a predetermined date and
time through activation of the PWR output pin. In addition,
the kickstart feature allows the system to be powered up
in response to a low-going transition on the KS pin, with-
out operating voltage applied to the VCC pin.
As a result, system power can be applied upon such
events as a key closure or modem ring-detect signal.
To use either the wake-up or the kickstart functions, the
DS17x85/DS17x87 must have an auxiliary battery con-
nected to the VBAUX pin, the oscillator must be running, and
the countdown chain must not be in reset (Register A DV2,
DV1, DV0 = 01X). If DV2 and DV1 are not in this required
state, the PWR pin is not driven low in response to a kick-
start or wake-up condition while in battery-backed mode.
The wake-up feature is controlled through the wake-up
interrupt-enable bit in Extended Control Register 4B (WIE,
bank 1, 04BH). Setting WIE to 1 enables the wake-up
feature, clearing WIE to 0 disables it. Similarly, the kick-
start interrupt-enable bit in Extended Control Register 4B
(KSE, bank 1, 04BH) controls the kickstart feature.
A wake-up sequence occurs as follows: When wake-up
is enabled through WIE = 1 while the system is powered
down (no VCC voltage), the clock/calendar monitors the
current date for a match condition with the date alarm reg-
ister (bank 1, register 049H). With the date alarm register,
the hours, minutes, and seconds alarm bytes in the clock/
calendar register map (bank 0, registers 05H, 03H, and
01H) are also monitored. As a result, a wake-up occurs at
the date and time specified by the date, hours, minutes,
and seconds alarm register values. This additional alarm
occurs regardless of the programming of the AIE bit (bank
0, register B, 0BH). When the match condition occurs,
the PWR pin is automatically driven low. This output can
be used to turn on the main system power supply that
provides VCC voltage to the DS17x85/DS17x87 as well
as the other major components in the system. Also at this
time, the wake-up flag (WF, bank 1, register 04AH) is set,
indicating that a wake-up condition has occurred.
A kickstart sequence occurs when kickstarting is enabled
through KSE = 1. While the system is powered down,
the KS input pin is monitored for a low-going transition of
minimum pulse width tKSPW. When such a transition is
detected, the PWR line is pulled low, as it is for a wake-up
condition. Also at this time, the kickstart flag (KF, bank 1,
register 04AH) is set, indicating that a kickstart condition
has occurred.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
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(TA = +25°C)
The timing associated with both the wake-up and kick-
starting sequences is illustrated in the Wake-Up/Kickstart
Timing Diagram (Figure 6). The timing associated with
these functions is divided into five intervals, labeled 1 to
5 on the diagram.
The occurrence of either a kickstart or wake-up condition
causes the PWR pin to be driven low, as described above.
During interval 1, if the supply voltage on the DS17x85/
DS17x87 VCC pin rises above the greater of VBAT or VPF
before the power-on timeout period (tPOTO) expires, then
PWR remains at the active-low level. If VCC does not
rise above the greater of VBAT or VPF in this time, then
the PWR output pin is turned off and returns to its high-
impedance level. In this event, the IRQ pin also remains
tri-stated. The interrupt flag bit (either WF or KF) associ-
ated with the attempted power-on sequence remains set
until cleared by software during a subsequent system
power-on.
If VCC is applied within the timeout period, then the sys-
tem power-on sequence continue as shown in intervals 2
to 5 in the timing diagram. During interval 2, PWR remains
active and IRQ is driven to its active-low level, indicating
that either WF or KF was set in initiating the power-on.
In the diagram KS is assumed to be pulled up to the
VBAUX supply. Also at this time, the PAB bit is automati-
cally cleared to 0 in response to a successful power-on.
The PWR line remains active as long as the PAB remains
cleared to 0.
Figure 6. Wake-Up/Kickstart Timing Diagram
Note: Wake-up/kickstart timeout is generated only when the oscillator is enabled and the countdown chain is not reset.
Table 6. Wake-Up/Kickstart Timing
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Kickstart-Input Pulse Width tKSPW 2 µs
Wake-Up/Kickstart Power-On
Timeout tPOTO 2 s
VBAT
VBAT
VIH tKSPW
tPOTP
VIH
VIH
1234 5
VIL
VIL
HIGH-IMPEDANCE
HIGH-IMPEDANCE
VIL
VPF
VPF
0V
0V
*CONDITION
VPF < VBAT
*THIS CONDITION CAN OCCUR WITH THE 3V DEVICE.
NOTE: THE TIME INTERVALS SHOWN ABOVE ARE REFERENCED IN THE WAKE-UP/KICKSTART SECTION.
*CONDITION
VBAT > VPF
WF/KF
(INTERNAL)
KS
PWR
IRQ
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
23
At the beginning of interval 3, the system processor has
begun code execution and clears the interrupt condition
of WF and/or KF by writing zeros to both of these control
bits. As long as no other interrupt within the DS17x85/
DS17x87 is pending, the IRQ line is taken inactive once
these bits are reset. Execution of the application software
can proceed. During this time, the wake-up and kickstart
functions can be used to generate status and interrupts.
WF is set in response to a date, hours, minutes, and
seconds match condition. KF is set in response to a low-
going transition on KS. If the associated interrupt-enable
bit is set (WIE and/or KSE), the IRQ line is driven active
low in response to enabled event. In addition, the other
possible interrupt sources within the DS17885/DS17887
can cause IRQ to be driven low. While system power is
applied, the on-chip logic always attempts to drive the
PWR pin active in response to the enabled kickstart or
wake-up condition. This is true even if PWR was previ-
ously inactive as the result of power being applied by
some means other than wake-up or kickstart.
The system can be powered down under software control
by setting the PAB bit to logic 1. This causes the open-
drain PWR pin to be placed in a high-impedance state, as
shown at the beginning of interval 4 in the timing diagram.
As VCC voltage decays, the IRQ output pin is placed in
a high-impedance state when VCC goes below VPF. If
the system is to be again powered on in response to a
wake-up or kickstart, then the WF and KF flags should be
cleared, and WIE and/or KSE should be enabled prior to
setting the PAB bit.
During interval 5, the system is fully powered down.
Battery backup of the clock calendar and NV RAM is in
effect and IRQ is tri-stated, and monitoring of wake-up
and kickstart takes place. If PRS = 1, PWR stays active;
otherwise, if PRS = 0, PWR is high impedance.
RAM Clear
The DS17x85/DS17x87 provide a RAM clear function for
the 114 bytes of user RAM. When enabled, this function can
be performed regardless of the condition of the V
CC
pin.
The RAM clear function is enabled or disabled through
the RAM clear-enable bit (RCE; bank 1, register 04BH).
When this bit is set to logic 1, the 114 bytes of user RAM
is cleared (all bits set to 1) when an active-low transition
is sensed on the RCLR pin. This action has no effect on
either the clock/calendar settings or the contents of the
extended RAM. The RAM clear flag (RF, bank 1, register
04AH) is set when the RAM clear operation has been
completed. If VCC is present at the time of the RAM clear
and RIE = 1, the IRQ line is also driven low upon comple-
tion. Writing a zero to the RF bit clears the interrupt con-
dition. The IRQ line then returns to its inactive high level,
provided there are no other pending interrupts. Once the
RCLR pin is activated, all read/write accesses are locked
out for a minimum recover time, specified as tREC in
Electrical Characteristics.
When RCE is cleared to 0, the RAM clear function is
disabled. The state of the RCLR pin has no effect on the
contents of the user RAM, and transitions on the RCLR
pin have no effect on RF.
Extended RAM
The DS17x85/DS17x87 provide 2k, 4k, or 8k x 8 of onchip
SRAM that is controlled as nonvolatile storage sustained
from a lithium battery. On power-up, the RAM is taken
out of write-protect status by the internal power-OK sig-
nal (POK) generated from the write-protect circuitry. The
on-chip SRAM is accessed through the eight multiplexed
address/data lines AD7 to AD0. Three on-chip latch regis-
ters control access to the SRAM. Two registers are used
to hold the SRAM address, and the other register is used
to hold read/write data.
Access to the extended RAM is controlled by three of
the registers shown in Table 5. The extended registers in
bank 1 must first be selected by setting the DV0 bit in reg-
ister A to logic 1. The address of the RAM location to be
accessed must be loaded into the extended RAM address
registers located at 50h and 51h. The least significant
address byte should be written to location 50h, and the
most significant bits (right-justified) should be loaded in
location 51h. Data in the addressed location can be read
by performing a read operation from location 53h, or writ-
ten to by performing a write operation to location 53h.
Data in any addressed location can be read or written
repeatedly without changing the address in location 50h
and 51h.
To read or write consecutive extended RAM locations,
a burst mode feature can be enabled to increment the
extended RAM address. To enable the burst mode fea-
ture, set the BME bit in the Extended Control Register
4Ah to logic 1. With burst mode enabled, write the
extended RAM starting address location to registers 50h
and 51h. Then read or write the extended RAM data from/
to register 53h. The extended RAM address locations are
automatically incremented on the rising edge of RD or
WR only when register 53h is being accessed. See the
Burst Mode Timing Waveform.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
www.maximintegrated.com Maxim Integrated
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