54109 ,/74109 Dual J-K Positive-Edge-Triggered Flip-Flop 137 with Preset and Clear Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL Package Package . Package . Package . Package Device Type Device Type Device Type Device Type Device Type yp CiP{MI|CF yP CLP |MICF cj; P|MICF c/P[M|cr C}| P| MCF SNS4L.S109 J wit | SN54109 du Wor TA. SN74L S109 JU[No} SN74109 JanINey FMSALS105// FMSUS109 FAIRCHILD FC7AL S109. FCSLS 109 MOTOROLA C. DMSAL. S103 DMS4109 ay N.S.C. OM74L $109 QD DM74i09 D PHILIPS N74L S109 a N74109 o) SIGNETICS $54109 FujBuy} Wal: N74L S109 AD} N74109 FuBu Wor FUJITSU HITACH HD74LS109 PO! MITSUBISH| [- MTL 5 109 Pa NEC 74. Si09 eo} TOSHIBA Electrical Characteristics SN54LS109 SN74LSI09 Pin Assignment (Top View) absolute maximum ratings over operating free-air temperature range Supply voliage. YEG W Operaing tree-ar | SNsacs =SC to 125C @ Inout _voitage v temperate rage SN7ALS oe to 70C vog CLR 2) 2K 2K aPR 20 20 Storage temperature cange =85'C to 5NC jel_f1s|_fial_ fiat fiz 1 fio 9 recommended operating conditions SNS4LS109 SN74LS109 unit LI MIN NOM MAX | MIN. NOM MAX Supply voitage. Yor as 5 5.5 | ars 5 5.28 v High-level output owrent. (On 400 =400 | ua Low-level output current, 1OL 4 8 mA Pee width, Ve Seek nen 2 a ns Preset or clear tow 2 2s > 1 Ww aR CK TPR ale) 10 GND input setup tine, teu High level data 20+ zot cur Low level data zt 20t 8 Trmt BOrd Wie, teow St St 98 Function Table Operating free-ar temperature, Ts -55 1s 0 70 c 109, LS109 (See Note 2) electrical characteristics over recommended operating INPUTS OUTPUTS free-air temperature range PRESET CLEAR CLOCK 4 K [ai @ PARAMETER TEST CONDITIONS tf MIN TYP MAX } UNIT L H x x x H L Vind High-level input voltage 2 v H L x x x L H a aoe ma voltage Z aN Su 0.8 . t L x x x H* H* l nput clamp voltage oc= . 1) == 8m, oS * Voc=MIN vin 2V 4 4 ' tok t " = . 1H . vi High-ievel output voita 2.7 3.4 v t OH 9 utp ge Vin =0.8V, H H HL | TOGGLE Voo=MIN. Vin= 2V, 4 Hq , LH | QQ VoL Low-level oulput voltage Vit =0.8V, fo. =4ma 0.25 0.4; V H 4 + 4 H H L input current at Dik o n 4 L x x 90 Qo Clear 0.2 4 "UI TE reset Voc =MAX, Viz IV a2] . Functional Block Diagrams voltage Clock 0.) e OK. 20 High-level Clear 40 PRESET 4 tit VoG=MAX, Wy =2.7V nh o input current Preset 40 | Clock 20 eLock OK 0.4 +5 | Low-levet Clear Voc=MAX, Vi =0.4V 0.8 A a tt input current Preset ce 7 wes 0.8) . Clock 0.4 Short-cireuit Series S418 -20 100 4 Voc=MA CLEAR OS output current #{ Sories 7418 Go=MAX 20 voo| "A Supply current Voo=MAX, See Note 1 4 | ma x SC (Average per flip-flop) ce=MAX, See Note m "108 LS109-DUAL J-K WITH CLEAR AND PRESET f, maximum clock frequenc: 5 IH max mum cloct a y Vec= 5V. 2 33 MHz 'PLH Ta =25C (3 25 from clear, Preset or clock to oe Q 3 CL =i5pF. ns NOTES. 1. With all outputs open, icg is measured with the @ and G outputs high in turn. CPHL oF AL = 2k 25 40 At the time of measurement, the clock input is grounded. 2.H = high level (steady state), L = iow level (steady state), X = irrelevant t = transition from low to high level Qo = the level of O before the indicated input conditions were established. TOGGLE: Each output changes to the complement of its previous level On each active transition (pulse) of the clock. * This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) state. t For conditions shown as MIN of MAX, use the appropriate value specified under recommended operating conditions. TAI typical values are at Voc= 5V, Ta=25C @Not more than one output should be shorted at a time. w (PLH= propagation delay time, iow to-high-level output. TPHL=propagation delay time, high-to-low-level output. t The arrow marcales that the r g edge of the clock pulse is used for refence.