General Description
The DS1843 is a sample-and-hold circuit useful for cap-
turing fast signals where board space is constrained. It
includes a differential, high-speed switched capacitor
input sample stage, offset nulling circuitry, and an out-
put buffer. The DS1843 is optimized for use in optical
line transmission (OLT) systems for burst-mode RSSI
measurement in conjunction with an external sense
resistor.
Applications
Gigabit Passive Optical Network (GPON) OLT
Gigabit Ethernet Passive Optical Network (GEPON) OLT
GPON Optical Network Unit
Sample and Hold
Features
♦Fast Sample Time < 300ns
♦Hold Time > 100µs
♦Low Input Offset
♦Buffered Output
♦Small, 8-Pin µDFN (2mm x 2mm) Pb-Free Package
DS1843
Fast Sample-and-Hold Circuit
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
VOUTN
MAIN MEMORY
EEPROM/SRAM
A/D CONFIG/RESULTS,
SYSTEM STATUS BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
CONTROLLER
VINP
VCC
VINN
SEN
GND
VOUTP
VCC
DEN
SDA
SCL
MON1
BIAS
DAC
12-BIT
ADC
MOD
DAC
BMD
SEN
STROBE
STROBE
MON4
MON3P
MON3N
ANALOG MUX
3.3V
3.3V
TEMP
SENSOR
I2C
INTERFACE
DS1843
DS1842/
MAX4007
RIN
CS
CS
CIN
CIN
CONTROL
LOGIC
Typical Operating Circuit
19-4539; Rev 0; 5/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
TRL = Tape and reel.
PART TEMP RANGE PIN-PACKAGE
DS1843D+ -40°C to +85°C 8 μDFN
DS1843D+TRL -40°C to +85°C 8 μDFN
Pin Configuration appears at end of data sheet.
DS1843
Fast Sample-and-Hold Circuit
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC .............................................-0.5V to +6V
Voltage Range on VOUTP, VOUTN,
VINP, VINN, SEN, DEN ............................-0.5V to (VCC + 0.5V)*
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature ..............................................Refer to the
IPC/JEDEC J-STD-020 Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC (Note 1) +2.97 +5.5 V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA= -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC (Note 1) 5.7 9 mA
Input Capacitance CIN All pins (Note 2) 7 pF
Sample Capacitance CSVINN and VINP (Note 2) 5 pF
Logic-Input Low VIL SEN and DEN inputs 0.3 x
VCC V
Logic-Input High VIH SEN and DEN inputs 0.7 x
VCC V
Input Leakage IIN VINN or VINP, SEN = 0 1 μA
Input Voltage VIN VIN = VINP - VINN 0 1.0 V
Output Voltage VOUT VOUT = VOUTP - VOUTN; 100k load on
each output pin 0 1.0 V
Output Impedance ROUTMAX (Note 2) 1 1.3 k
Output Capacitive Load COUT Capacitance for stable operation 50 pF
VCC = 2.9V, 1μs sample time, VIN = 6mV 3.6 6.1 mV
Total Input Referenced Voltage
Offset: Differential VOS-DIFF Voltco (VCC = 2.9V to 5.5V) 1 mV/V
VCC = 2.9V, 1μs sample time, VIN = 6mV 3.4 8 mV
Total Input Referenced Voltage
Offset: Single-Ended VOS-SE Voltco (VCC = 2.9V to 5.5V) 1 mV/V
*
Subject to not exceeding +6V.
DS1843
Fast Sample-and-Hold Circuit
_______________________________________________________________________________________ 3
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Guaranteed by design.
Note 3: VOUT at the end of the 10μs hold time is within specified % of VIN during the sample window; a 2.5kΩresistor connected in
series to both VINP and VINN (VINP - VINN = 1V). External capacitance to ground for both VINP and VINN is approximately 10pF.
Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
must be low for a short period of time, tDEL, before the input changes.
Note 5: VOUT at the end of the hold time is within 1% of VIN during the sample window (VINP - VINN = 1V).
Note 6: Voltage step applied across VOUTP to VOUTN through a 5pF capacitor connected to each pin. This models the load presented
by an ADC while it is sampling the DS1843’s output. See the
Output Buffer
section. Settled within 1% of initial voltage.
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA= -40°C to +85°C, unless otherwise noted.) (See the
Timing Diagram
.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VOUT is within 1% 300
Sample Time Minimum (Note 3) tSVOUT is within 35% 260 ns
Delay Time Minimum tDEL (Note 4) 10 ns
Output Time tOUT Delay from SEN falling edge until valid
output at VOUT to 1% accuracy 2 μs
Hold Time tHOLD (Note 5) tOUT 100 μs
1V step, DEN = high 2
Output Step Recovery Time
(Note 6) tREC 3V step, DEN = high or low 3.5 μs
Timing Diagram
VINP - VINN
VOUTP - VOUTN
EXTERNAL
ADC DATA
tADC:ST = EXTERNAL ADC SAMPLING TIME.
tADC:CT = EXTERNAL ADC CONVERSION TIME.
DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT.
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
SEN
tStDEL
tOUT
tADC:ST
DATA VALID
tADC:CT
tREC
tHOLD
VOLTAGE INVALID
DS1843
Fast Sample-and-Hold Circuit
4 _______________________________________________________________________________________
ICC vs. VCC
DS1843 toc01
VCC (V)
ICC (mA)
5.04.54.03.53.0
5.4
5.5
5.6
5.7
5.8
5.9
5.3
2.5 5.5
DEN = GND
DEN = VCC
ICC vs. TEMPERATURE
DS1843 toc02
TEMPERATURE (°C)
ICC (mA)
603510-15
5.5
5.7
5.9
6.1
6.3
6.5
5.3
-40 85
DEN = VCC
VCC = 5V
VCC = 3.3V
ICC vs. TEMPERATURE
DS1843 toc03
TEMPERATURE (°C)
ICC (mA)
603510-15
5.5
5.7
5.9
6.1
6.3
6.5
5.3
-40 85
DEN = GND
VCC = 5V
VCC = 3.3V
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc04
TEMPERATURE (°C)
OUTPUT HOLD TIME (SECONDS)
603510-15
10
100
1000
1
-40 85
DEN = VCC
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc05
TEMPERATURE (°C)
OUTPUT HOLD TIME (SECONDS)
603510-15
10
100
1000
1
-40 85
DEN = GND
DIFFERENTIAL OUTPUT DURING SAMPLING
(VINP = 6mV)
DS1843 toc06
500ns/div
5mV/div
VOUTP VOUTN
VSEN
VOUTP - VOUTN
100mV/div
1.5V/div
SINGLE-ENDED OUTPUT DURING SAMPLING
(VINP = 6mV)
DS1843 toc07
20ns/div
2mV/div
1.5V/div
100mV/div
VOUTP
VSEN
ZOOMED
VOUTP ZOOM
500ns/div
DIFFERENTIAL OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 6mV)
DS1843 toc08
100
μ
s/div
5mV/div
VOUTP VOUTN
VSEN
VOUTP - VOUTN
100mV/div
VCC = 3.3V
1V/div
VCC = 3.0V
SINGLE-ENDED OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 6mV)
DS1843 toc09
100
μ
s/div
2.0V/div
100mV/div
VCC = 3.0V
VCC = 3.3V
VOUTP
VSEN
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
DS1843
Fast Sample-and-Hold Circuit
_______________________________________________________________________________________
5
DIFFERENTIAL OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 1V)
DS1843 toc10
100
μ
s/div
200mV/div
2V/div
1V/div
VCC = 3.3V
VCC = 3.0V
VOUTP
VOUTN
VSEN
VOUTP - VOUTN
SINGLE-ENDED OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 1V)
DS1843 toc11
100
μ
s/div
2V/div
1V/div
VCC = 3V
VCC = 3.3V
VOUTP
VSEN
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 6mV)
DS1843 toc12
50
μ
s/div
10mV/div
200mV/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTN (200mV/div)
VOUTP - VOUTN
SINGLE-ENDED STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V)
DS1843 toc13
50
μ
s/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTP STEP (200mV/div)
SINGLE-ENDED OUTPUT, STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc14
50ns/div
500mV/div
500mV/div
VOUTP
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V)
DS1843 toc15
50
μ
s/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTP - VOUTN
OUTPUT STEP (200mV/div)
VOUTN (200mV/div)
200mV/div
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc16
50ns/div
VOUTP
VOUTP - VOUTN
(200mV/div)
VOUTN (200mV/div)
200mV/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DS1843
Fast Sample-and-Hold Circuit
6 _______________________________________________________________________________________
Detailed Description
The DS1843 consists of a fully differential sampling
capacitor, switches, and a differential output buffer. It is
designed to operate in fiber optic burst-mode systems;
however, it can be used in other applications requiring
a fast sample-and-hold circuit. The output can be con-
figured for single-ended operations.
Input Sampling Capacitor
The input voltage is sampled using a 5pF capacitor on
the positive input and another on the negative input.
The capacitors are connected to the input when SEN is
high. In addition to the sampling capacitors, the inputs
also have parasitic capacitance (CIN). These capaci-
tors must fully charge before SEN is switched to low in
order to ensure accurate sampling. An RC time con-
stant is created by the resistance of the voltage source
connected to the DS1843’s input and the capacitances
on this node. See the
Applications Information
section
for details.
Output Buffer
After sampling is complete, the sampling capacitor is
switched to the output buffer. This buffer requires a
small amount of time to settle, tOUT. When an ADC is
used to measure the DS1843’s output, a step occurs at
the ADC’s input caused by the ADC’s internal sampling
capacitor. The DS1843’s recovery time, tREC, is depen-
dent on the size of the ADC’s sampling capacitor and
the voltage applied across the ADC. To maximize
accuracy, the ADC’s sampling speed (ADC clock fre-
quency) should be reduced until the ADC’s conversion
window (tADC:ST, as shown in the
Timing Diagram
) is
larger than the DS1843’s recovery time. Refer to the
ADC’s documentation for tADC:ST.
Sampling Time and Output Error
As the sampling time (tS) is decreased, the output error
increases. The output error is largely dependent on the
settling time of the sampling capacitor and, to a lesser
degree, the output buffer’s gain error and offset volt-
age. Settling time can be reduced by driving the
DS1843 with a lower impedance. In a typical fiber optic
application, a current is applied across a 5kΩresistor.
By using a stronger current source, the resistance and
the settling time can be reduced (see the
Applications
Information
section for details).
Pin Description
PIN NAME FUNCTION
1 VCC Power-Supply Input
2 VINP Positive Voltage Input. Input to sample circuit.
3 VINN Negative Voltage Input. Input to sample circuit.
4 DEN Differential Output Enable. Connect to VCC for differential output or GND for single-ended output.
5 GND Ground Terminal
6 VOUTN Sampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or
connect to GND for single-ended output mode.
7 VOUTP Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor.
8 SEN Sample Enable. Enables input sampling. This input is pulsed.
Block Diagram
DS1843
VOUTN
CS
CS
VCC
VINP
VINN
SEN
GND
CIN
CIN VOUTP
CONTROL
LOGIC
DEN
DS1843
Fast Sample-and-Hold Circuit
_______________________________________________________________________________________ 7
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1843,
decouple the power-supply pin, VCC, with a 0.01μF or
0.1μF capacitor. Use a high-quality X7R or equivalent
ceramic surface-mount capacitor.
DS1843 Estimated Settling Time
The settling time is dependent on the gain ratio of the
current mirror used at the input of the DS1843. For
example, the MAX4007 includes a 10:1 ratio current
mirror. This requires a 5kΩresistor to create a 1V full-
scale output with 2mA current input to the MAX4007.
This resistor can be decreased to 2.5kΩby using the
DS1842, which has a 5:1 ratio current mirror.
Variable Definitions:
RIN: Input resistor. The current mirror creates a voltage
across this resistor.
RSW: Resistance of series switch that connects internal
circuitry to input pins after tIST time.
CIN: 7pF parasitic (ESD) capacitor.
CPAR: External parasitic capacitance. A current mirror's
output and typical trace capacitance are less than
10pF.
CS: 5pF sample capacitor.
tIST: Internal settling time based on tSfrom the AC elec-
trical specification. The minimum tSincludes one time
constant. tIST removes this time constant.
tRC: RC settling time of the input.
Figure 1 shows the simplified diagram of input imped-
ances for settling time calculations. Sample time is
divided into two parts:
1) tIST: Internal settling time (max 250ns). During this
time, voltage VIN (VINP - VINN) rises with a time con-
stant of:
RIN x (CIN + CPAR)
2) tRC: During this period two things happen:
a. Input VIN keeps increasing from its value at tIST
to its final value with a new time constant of:
b. RSW and CStrack this VIN (input) with a time con-
stant of RSW x CS, which is 12.5ns (worst case).
Example:
Approximate accuracy calculations can be done for an
input voltage based on the above impedance values.
These calculations can be divided into three parts.
1) Accuracy of input at tIST (250ns):
where t1= tIST = 250ns.
At tIST the internal circuit tags input impedance.
This causes charge redistribution to occur, which
causes a dip in the input voltage. The worst-case
value of the input voltage at tIST is:
VC
CC C e
IN t S
IN PAR S
t
IST
IST
@=− ++
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥×−
−
11
RRCC
IN
IN IN PAR V
×+
()
⎡
⎣⎤
⎦
⎡
⎣
⎢
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
⎥
×
Accuracy e
t
RCC
IN IN PAR
=−
−
×+
()
⎡
⎣⎤
⎦
1
1
RCC RC
IN IN PAR SW S
×+
()
()
+×
()
⎧
⎨
⎩
⎫
⎬
⎭
22
DS1843
CS
CS
CIN
CPAR
CIN
INPUT MODEL
RSW
VINP
VINN RSW
RIN
CURRENT
MIRROR OUTPUT
Figure 1. Input Impedances for Settling Time Calculations Diagram
2) Accuracy of internal circuitry between tS- tIST:
where t2= (tS- tIST) and (RSW x CS) ~ = 12ns.
3) Total accuracy of input at sampling time, tS:
where newRC R C C R C
IN IN PAR SW S
=×+
()
()
+×
()
⎧
⎨
⎩
⎫
22⎬⎬
⎭
Accuracy V e
IN t
t
newRC
IST
=−−
()
×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥×
−
11 1
2
@−−
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
−
×
()
e
t
RC
SW S
2
Accuracy e
t
RC
SW S
=−
−
×
()
1
2
1
2
3
8
7
4
6
5
SEN
VOUTP
VOUTN
+
VCC
VINP
VINN
DEN GND
TOP VIEW
DS1843
μ
DFN
(2mm
×
2mm)
Pin Configuration
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 μDFN L822+1 21-0164
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Fast Sample-and-Hold Circuit
DS1843
