LTC2281IUP#PBF - LINEAR TECHNOLOGY

LTC2281

2281fb

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual 10-Bit, 125Msps

Low Power 3V ADC

The LTC

2281 is a 10-bit 125Msps, low power dual 3V

A/D converter designed for digitizing high frequency,

wide dynamic range signals. The LTC2281 is perfect for

demanding imaging and communications applications

with AC performance that includes 61.6dB SNR and 82dB

SFDR for signals at the Nyquist frequency.

Typical DC specs include ±0.1LSB INL, ±0.1LSB DNL. The

transition noise is a low 0.08LSBRMS.

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic.

A single-ended CLK input controls converter operation.

An optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

A data ready output clock (CLKOUT) can be used to latch

the output data.

SNR vs Input Frequency,

–1dB, 2V Range

n Integrated Dual 10-Bit ADCs

n Sample Rate: 125Msps

n Single 3V Supply (2.85V to 3.4V)

n Low Power: 790mW

n 61.6dB SNR, 88dB SFDR

n 110dB Channel Isolation at 100MHz

n Flexible Input: 1VP-P to 2VP-P Range

n 640MHz Full Power Bandwidth S/H

n Clock Duty Cycle Stabilizer

n Shutdown and Nap Modes

n Data Ready Output Clock

n Pin Compatible Family

125Msps: LTC2283 (12-Bit), LTC2281 (10-Bit)

105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit)

80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)

65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)

40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)

n 64-Pin (9mm × 9mm) QFN Package

n Wireless and Wired Broadband Communication

n Imaging Systems

n Spectral Analysis

n Portable Instrumentation

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

–

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

10-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

OVDD

OGND

MUX

CLKOUT

D9A

D0A

•

OVDD

OGND

2281 TA01

D9B

D0B

–

+OUTPUT

DRIVERS

INPUT

S/H

10-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

INPUT FREQUENCY (MHz)

SNR (dBFS)

100 200 250

2281 TA01b

50 150 300 350

LTC2281

2281fb

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ..................................................4V

Digital Output Ground Voltage (OGND) ........ –0.3V to 1V

Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)

Digital Input Voltage ......................–0.3V to (VDD + 0.3V)

Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)

Power Dissipation .............................................1500mW

Operating Temperature Range

LTC2281C ................................................ 0°C to 70°C

LTC2281I.............................................. –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

OVDD = VDD (Notes 1, 2)

TOP VIEW

UP PACKAGE

64-LEAD (9mm s 9mm) PLASTIC QFN

AINA+1

AINA– 2

REFHA 3

REFHA 4

REFLA 5

REFLA 6

VDD 7

CLKA 8

CLKB 9

VDD 10

REFLB 11

REFLB 12

REFHB 13

REFHB 14

AINB– 15

AINB+ 16

48 DA3

47 DA2

46 DA1

45 DA0

44 NC

43 NC

42 NC

41 NC

40 CLKOUT

39 DB9

38 DB8

37 DB7

36 DB6

35 DB5

34 DB4

33 DB3

64 GND

63 VDD

62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OF

56 DA9

55 DA8

54 DA7

53 DA6

52 DA5

51 DA4

50 OGND

49 OVDD

GND 17

VDD 18

SENSEB 19

VCMB 20

MUX 21

SHDNB 22

OEB 23

NC 24

NC 25

NC 26

NC 27

DB0 28

DB1 29

DB2 30

OGND 31

OVDD 32

TJMAX = 150°C, θJA = 20°C/W

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2281CUP#PBF LTC2281CUP#TRPBF LTC2281UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2281IUP#PBF LTC2281IUP#TRPBF LTC2281UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2281CUP LTC2281CUP#TR LTC2281UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2281IUP LTC2281IUP#TR LTC2281UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ●10 Bits

Integral Linearity Error Differential Analog Input (Note 5) ●–0.7 ±0.1 0.7 LSB

Differential Linearity Error Differential Analog Input ●–0.7 ±0.1 0.7 LSB

Offset Error (Note 6) ●–12 ±2 12 mV

Gain Error External Reference ●–2.5 ±0.5 2.5 %FS

Offset Drift ±10 µV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°C

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

CONVERTER CHARACTERISTICS

LTC2281

2281fb

ANALOG INPUT

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise

speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ –AIN–) 2.85V < VDD < 3.4V (Note 7) ●±0.5V to ±1V V

VIN,CM Analog Input Common Mode (AIN+ +AIN–)/2 Differential Input Drive (Note 7)

Single Ended Input Drive (Note 7)

●

0.5

1.5

1.9

IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD ●–1 1 µA

ISENSE SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ●–3 3 µA

IMODE MODE Input Leakage Current 0V < MODE < VDD ●–3 3 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Full Power Bandwidth Figure 8 Test Circuit 640 MHz

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 61.6 dB

30MHz Input 61.6 dB

70MHz Input ●60 61.5 dB

140MHz Input 61.4 dB

SFDR Spurious Free Dynamic Range

2nd or 3rd Harmonic

5MHz Input 85 dB

30MHz Input 85 dB

70MHz Input ●69 82 dB

140MHz Input 77 dB

SFDR Spurious Free Dynamic Range

4th Harmonic or Higher

5MHz Input 85 dB

30MHz Input 85 dB

70MHz Input ●75 85 dB

140MHz Input 85 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio

5MHz Input 61.5 dB

30MHz Input 61.5 dB

70MHz Input ●60 61.4 dB

140MHz Input 61.2 dB

IMD Intermodulation Distortion fIN = 40MHz, 41MHz 80 dB

Crosstalk fIN = 100MHz –110 dB

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

CONVERTER CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Gain Matching External Reference ±0.3 %FS

Offset Matching ±2 mV

Transition Noise SENSE = 1V 0.08 LSBRMS

LTC2281

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INTERNAL REFERENCE CHARACTERISTICS

(Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V

VCM Output Tempco ±25 ppm/°C

VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V

VCM Output Resistance

IOUT

< 1mA 4

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, SHDN, MUX)

VIH High Level Input Voltage VDD = 3V ●2V

VIL Low Level Input Voltage VDD = 3V ●0.8 V

IIN Input Current VIN = 0V to VDD ●–10 10 µA

CIN Input Capacitance (Note 7) 3 pF

LOGIC OUTPUTS

OVDD = 3V

COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF

ISOURCE Output Source Current VOUT = 0V 50 mA

ISINK Output Sink Current VOUT = 3V 50 mA

VOH High Level Output Voltage IO = –10µA

IO = –200µA ●2.7

2.995

2.99

VOL Low Level Output Voltage IO = 10µA

IO = 1.6mA ●

0.005

0.09 0.4

OVDD = 2.5V

VOH High Level Output Voltage IO = –200µA 2.49 V

VOL Low Level Output Voltage IO = 1.6mA 0.09 V

OVDD = 1.8V

VOH High Level Output Voltage IO = –200µA 1.79 V

VOL Low Level Output Voltage IO = 1.6mA 0.09 V

LTC2281

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The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 8)

POWER REQUIREMENTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Analog Supply Voltage (Note 9) ●2.85 3 3.4 V

OVDD Output Supply Voltage (Note 9) ●0.5 3 3.6 V

IVDD Supply Current Both ADCs at fS(MAX) ●263 305 mA

PDISS Power Dissipation Both ADCs at fS(MAX) ●790 915 mW

PSHDN Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW

PNAP Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

TIMING CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fsSampling Frequency (Note 9) ●1 125 MHz

tLCLK Low Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

●

3.8

500

tHCLK High Time Duty Cycle Stabilizer Off (Note 7)

Duty Cycle Stabilizer On (Note 7)

●

3.8

500

tAP Sample-and-Hold Aperture Delay 0 ns

tDCLK to DATA Delay CL = 5pF (Note 7) ●1.4 2.7 5.4 ns

tCCLK to CLKOUT Delay CL = 5pF (Note 7) ●1.4 2.7 5.4 ns

DATA to CLKOUT Skew (tD – tC) (Note 7) ●–0.6 0 0.6 ns

tMD MUX to DATA Delay CL = 5pF (Note 7) ●1.4 2.7 5.4 ns

Data Access Time After OE↓CL = 5pF (Note 7) ●4.3 10 ns

BUS Relinquish Time (Note 7) ●3.3 8.5 ns

Pipeline Latency 5 Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3V, fSAMPLE = 125MHz, input range = 2VP-P with differential

drive, unless otherwise noted.

Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

the output code ﬂ ickers between 00 0000 0000 and 11 1111 1111.

Note 7: Guaranteed by design, not subject to test.

Note 8: VDD = 3V, fSAMPLE = 125MHz, input range = 1VP-P with differential

drive. The supply current and power dissipation are the sum total for both

channels with both channels active.

Note 9: Recommended operating conditions.

LTC2281

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TYPICAL PERFORMANCE CHARACTERISTICS

Crosstalk vs Input Frequency Typical INL, 2V Range, 125Msps Typical DNL, 2V Range, 125Msps

8192 Point FFT, fIN = 5MHz,

–1dB, 2V Range, 125Msps

8192 Point FFT, fIN = 30MHz,

–1dB, 2V Range, 125Msps

8192 Point FFT, fIN = 70MHz,

–1dB, 2V Range, 125Msps

8192 Point FFT, fIN = 140MHz,

–1dB, 2V Range, 125Msps

8192 Point 2-Tone FFT,

fIN = 28.2MHz and 26.8MHz,

–1dB, 2V Range, 125Msps

Grounded Input

Histogram, 125Msps

INPUT FREQUENCY (MHz)

–130

CROSSTALK (dB)

–125

–120

–115

–110

–105

–100

20 40 60 80

2281 G01

100

CODE

INL ERROR (LSB)

768

2281 G02

256 512 1024

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

CODE

DNL ERROR (LSB)

768

2281 G03

256 512 1024

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

FREQUENCY (MHz)

AMPLITUDE (dB)

2281 G04

10 20 30 40 50 60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

FREQUENCY (MHz)

AMPLITUDE (dB)

2281 G05

10 20 30 40 50 60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

FREQUENCY (MHz)

AMPLITUDE (dB)

2281 G06

10 20 30 40 50 60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

FREQUENCY (MHz)

AMPLITUDE (dB)

2281 G07

10 20 30 40 50 60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

FREQUENCY (MHz)

AMPLITUDE (dB)

2281 G08

10 20 30 40 50 60

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

CODE

70000

60000

50000

40000

30000

20000

10000

0511

65528

512

2281 G09

510

COUNT

LTC2281

2281fb

TYPICAL PERFORMANCE CHARACTERISTICS

SNR vs Input Frequency,

–1dB, 2V Range, 125Msps

SFDR vs Input Frequency,

–1dB, 2V Range, 125Msps

SNR and SFDR vs Sample Rate,

2V Range, fIN = 5MHz, –1dB

SNR vs Input Level,

fIN = 70MHz, 2V Range, 125Msps

SFDR vs Input Level,

fIN = 70MHz, 2V Range, 125Msps

IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dB

IOVDD vs Sample Rate, 5MHz Sine

Wave Input, –1dB, 0VDD = 1.8V SNR vs SENSE, fIN = 5MHz, –1dB

INPUT FREQUENCY (MHz)

SNR (dBFS)

100 200 250

2281 G10

50 150 300 350

INPUT FREQUENCY (MHz)

SFDR (dBFS)

150 250

2281 G11

50 100 200 300 350

SAMPLE RATE (Msps)

SNR AND SFDR (dBFS)

20 40 60 80

2281 G12

100 120 140 160

SFDR

SNR

INPUT LEVEL (dBFS)

–50

SNR (dBc AND dBFS)

–20 0

2281 G13

0–40 –30

dBFS

dBc

–10

INPUT LEVEL (dBFS)

–50

SFDR (dBc AND dBFS)

100

–10

2281 G14

0–40 –30 –20 0

dBFS

dBc

SAMPLE RATE (Msps)

IVDD (mA)

260

280

2281 G15

240

220

250

270

290

230

210

200

190

20 40 60 100 120 140

2V RANGE

1V RANGE

SAMPLE RATE (Msps)

IOVDD (mA)

2281 G16

20 40 80

100 120 140

SENSE PIN (V)

0.4

SNR (dBFS)

61.6

0.7

2281 G17

61.0

60.6

0.5 0.6 0.8

60.4

60.2

61.8

61.4

61.2

60.8

0.9 1 1.1

LTC2281

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PIN FUNCTIONS

AINA+ (Pin 1): Channel A Positive Differential Analog

Input.

AINA– (Pin 2): Channel A Negative Differential Analog

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short to-

gether and bypass to Pins 5, 6 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 5, 6 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short to-

gether and bypass to Pins 3, 4 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 3, 4 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample

starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample

starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short

together and bypass to Pins 13, 14 with a 0.1µF ceramic

chip capacitor as close to the pin as possible. Also by-

pass to Pins 13, 14 with an additional 2.2µF ceramic

chip capacitor and to ground with a 1µF ceramic chip

capacitor.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1µF ceramic

chip capacitor as close to the pin as possible. Also by-

pass to Pins 11, 12 with an additional 2.2µF ceramic

chip capacitor and to ground with a 1µF ceramic chip

capacitor.

AINB– (Pin 15): Channel B Negative Differential Analog

Input.

AINB+ (Pin 16): Channel B Positive Differential Analog

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to VCMB selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input

range of ±VSENSEB. ±1V is the largest valid input range.

VCMB (Pin 20): Channel B 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to VCMA.

MUX (Pin 21): Digital Output Multiplexer Control. If MUX is

High, Channel A comes out on DA0-DA9; Channel B comes

out on DB0-DB9. If MUX is Low, the output busses are

swapped and Channel A comes out on DB0-DB9; Channel

B comes out on DA0-DA9. To multiplex both channels

onto a single output bus, connect MUX, CLKA and CLKB

together. (This is not recommended at clock frequencies

above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection

Pin. Connecting SHDNB to GND and OEB to GND results

in normal operation with the outputs enabled. Connecting

SHDNB to GND and OEB to VDD results in normal operation

with the outputs at high impedance. Connecting SHDNB

to VDD and OEB to GND results in nap mode with the

outputs at high impedance. Connecting SHDNB to VDD

and OEB to VDD results in sleep mode with the outputs

at high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

NC (Pins 24 to 27, 41 to 44): Do not connect these

pins.

DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital

Outputs. DB9 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Drivers.

Bypass to ground with 0.1µF ceramic chip capacitor.

CLKOUT (Pin 40): Data Ready Clock Output. Latch data

on the falling edge of CLKOUT. CLKOUT is derived from

CLKB. Tie CLKA to CLKB for simultaneous operation.

DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital

Outputs. DA9 is the MSB.

OF (Pin 57): Overﬂ ow/Underﬂ ow Output. High when an

overﬂ ow or underﬂ ow has occurred on either channel A

or channel B.

LTC2281

2281fb

PIN FUNCTIONS

OEA (Pin 58): Channel A Output Enable Pin. Refer to

SHDNA pin function.

SHDNA (Pin 59): Channel A Shutdown Mode Selection

Pin. Connecting SHDNA to GND and OEA to GND results

in normal operation with the outputs enabled. Connecting

SHDNA to GND and OEA to VDD results in normal operation

with the outputs at high impedance. Connecting SHDNA

to VDD and OEA to GND results in nap mode with the

outputs at high impedance. Connecting SHDNA to VDD

and OEA to VDD results in sleep mode with the outputs

at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects offset binary

output format and turns the clock duty cycle stabilizer

off. 1/3 VDD selects offset binary output format and turns

the clock duty cycle stabilizer on. 2/3 VDD selects 2’s

complement output format and turns the clock duty cycle

stabilizer on. VDD selects 2’s complement output format

and turns the clock duty cycle stabilizer off.

VCMA (Pin 61): Channel A 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to VCMB.

SENSEA (Pin 62): Channel A Reference Programming Pin.

Connecting SENSEA to VCMA selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input

range of ±VSENSEA. ±1V is the largest valid input range.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The

Exposed Pad on the bottom of the package needs to be

soldered to ground.

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram (Only One Channel is Shown)

SHIFT REGISTER

AND CORRECTION

DIFF

REF

AMP

REF

BUF

2.2µF

1µF 1µF

0.1µF

INTERNAL CLOCK SIGNALSREFH REFL

CLOCK/DUTY

CYCLE

CONTROL

RANGE

SELECT

1.5V

REFERENCE

FIRST PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

REFH REFL

CLK OEMODE

OGND

OVDD

2281 F01

INPUT

S/H

SENSE

VCM

AIN–

AIN+

2.2µF

THIRD PIPELINED

ADC STAGE

OUTPUT

DRIVERS

CONTROL

LOGIC

SHDN

OF*

CLKOUT*

•

*OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS.

LTC2281

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TIMING DIAGRAMS

Dual Digital Output Bus Timing

(Only One Channel is Shown)

Multiplexed Digital Output Bus Timing

tAP

N + 1

N + 2 N + 4

N + 3 N + 5

ANALOG

INPUT

N – 4 N – 3 N – 2 N – 1

CLKA = CLKB

D0-D9, OF

2281 TD01

CLKOUT

N – 5 N

tAPB

B + 1

B + 2 B + 4

B + 3

ANALOG

INPUT B

tAPA

A + 1

A – 5

B – 5

A – 5

A – 4

B – 4

A – 4

A – 3

B – 3

A – 3

A – 2

B – 2

A – 2

A – 1

B – 1

A + 2 A + 4

A + 3

ANALOG

INPUT A

tMD

CLKA = CLKB = MUX

D0A-D9A

2281 TD02

CLKOUT

D0B-D9B

LTC2281

2281fb

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is

the ratio between the RMS amplitude of the fundamen-

tal input frequency and the RMS amplitude of all other

frequency components at the ADC output. The output is

band limited to frequencies above DC to below half the

sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the ﬁ rst ﬁ ve harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD =20log (V22+V32+V42+...Vn2)/V1







where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the second

through nth harmonics. The THD calculated in this data

sheet uses all the harmonics up to the ﬁ fth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are ap-

plied to the ADC input, nonlinearities in the ADC transfer

function can create distortion products at the sum and

difference frequencies of mfa ± nfb, where m and n = 0,

1, 2, 3, etc. The 3rd order intermodulation products are

APPLICATIONS INFORMATION

2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-

tion distortion is deﬁ ned as the ratio of the RMS value of

either input tone to the RMS value of the largest 3rd order

intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spuri-

ous noise that is the largest spectral component excluding

the input signal and DC. This value is expressed in decibels

relative to the RMS value of a full-scale input signal.

Input Bandwidth

The input bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced

by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches midsupply to the in-

stant that the input signal is held by the sample and hold

circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

Crosstalk

Crosstalk is the coupling from one channel (being driven

by a full-scale signal) onto the other channel (being driven

by a –1dBFS signal).

CONVERTER OPERATION

As shown in Figure 1, the LTC2281 is a dual CMOS

pipelined multistep converter. The converter has six

pipelined ADC stages; a sampled analog input will result

in a digitized value ﬁ ve cycles later (see the Timing Dia-

gram section). For optimal AC performance the analog

inputs should be driven differentially. For cost sensitive

applications, the analog inputs can be driven single-ended

LTC2281

2281fb

APPLICATIONS INFORMATION

with slightly worse harmonic distortion. The CLK input is

single-ended. The LTC2281 has two phases of operation,

determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue ampliﬁ er.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is ampliﬁ ed and

output by the residue ampliﬁ er. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

When CLK is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the Block Diagram. At the instant

that CLK transitions from low to high, the sampled input is

held. While CLK is high, the held input voltage is buffered

by the S/H ampliﬁ er which drives the ﬁ rst pipelined ADC

stage. The ﬁ rst stage acquires the output of the S/H dur-

ing this high phase of CLK. When CLK goes back low, the

ﬁ rst stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back to

acquiring the analog input. When CLK goes back high, the

second stage produces its residue which is acquired by the

third stage. An identical process is repeated for the third,

fourth and ﬁ fth stages, resulting in a ﬁ fth stage residue

that is sent to the sixth stage ADC for ﬁ nal evaluation.

Each ADC stage following the ﬁ rst has additional range to

accommodate ﬂ ash and ampliﬁ er offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2281 CMOS

differential sample-and-hold. The analog inputs are con-

nected to the sampling capacitors (CSAMPLE) through NMOS

transistors. The capacitors shown attached to each input

(CPARASITIC) are the summation of all other capacitance

associated with each input.

During the sample phase when CLK is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to and track the differential input voltage. When

CLK transitions from low to high, the sampled input voltage

is held on the sampling capacitors. During the hold phase

when CLK is high, the sampling capacitors are disconnected

Figure 2. Equivalent Input Circuit

VDD

15

CPARASITIC

1pF

CPARASITIC

1pF

CSAMPLE

3.5pF

CSAMPLE

3.5pF

LTC2281

AIN+

AIN–

CLK

2281 F02

LTC2281

2281fb

APPLICATIONS INFORMATION

from the input and the held voltage is passed to the ADC

core for processing. As CLK transitions from high to low,

the inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional to

the change in voltage between samples will be seen at this

time. If the change between the last sample and the new

sample is small, the charging glitch seen at the input will

be small. If the input change is large, such as the change

seen with input frequencies near Nyquist, then a larger

charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, AIN+

should be driven with the input signal and AIN– should be

connected to 1.5V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing ±0.5V for the

2V range or ±0.25V for the 1V range, around a common

mode voltage of 1.5V. The VCM output pin may be used

to provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic

performance of the LTC2281 can be inﬂ uenced by the input

drive circuitry, particularly the second and third harmonics.

Source impedance and reactance can inﬂ uence SFDR. At

the falling edge of CLK, the sample-and-hold circuit will

connect the 3.5pF sampling capacitor to the input pin and

start the sampling period. The sampling period ends when

CLK rises, holding the sampled input on the sampling

capacitor. Ideally the input circuitry should be fast enough

to fully charge the sampling capacitor during the sampling

period 1/(2FENCODE); however, this is not always possible

and the incomplete settling may degrade the SFDR. The

sampling glitch has been designed to be as linear as pos-

sible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a

source impedance of 100 or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2281 being driven by an RF trans-

former with a center tapped secondary. The secondary

center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Terminating on the trans-

former secondary is desirable, as this provides a common

mode path for charging glitches caused by the sample and

hold. Figure 3 shows a 1:1 turns ratio transformer. Other

turns ratios can be used if the source impedance seen

by the ADC does not exceed 100 for each ADC input.

A disadvantage of using a transformer is the loss of low

frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Figure 3. Single-Ended to Differential

Conversion Using a Transformer

25

0.1µF

AIN+

AIN–

12pF

2.2µF

VCM

LTC2281

ANALOG

INPUT

0.1µF T1

1:1

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2281 F03

LTC2281

2281fb

APPLICATIONS INFORMATION

Figure 4 demonstrates the use of a differential ampliﬁ er to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides

low frequency input response; however, the limited gain

bandwidth of most op amps will limit the SFDR at high

input frequencies.

Figure 5 shows a single-ended input circuit. The impedance

seen by the analog inputs should be matched. This circuit

is not recommended if low distortion is required.

The 25 resistors and 12pF capacitor on the analog

inputs serve two purposes: isolating the drive circuitry

from the sample-and-hold charging glitches and limiting

the wideband noise at the converter input.

For input frequencies above 70MHz, the input circuits of

Figure 6, 7 and 8 are recommended. The balun transformer

gives better high frequency response than a ﬂ ux coupled

center tapped transformer. The coupling capacitors allow

the analog inputs to be DC biased at 1.5V. In Figure 8, the

series inductors are impedance matching elements that

maximize the ADC bandwidth.

Figure 4. Differential Drive with an Ampliﬁ er

Figure 5. Single-Ended Drive

Figure 6. Recommended Front End Circuit for

Input Frequencies Between 70MHz and 170MHz

Figure 7. Recommended Front End Circuit for

Input Frequencies Between 170MHz and 300MHz

Figure 8. Recommended Front End Circuit for

Input Frequencies Above 300MHz

25

12pF

2.2µF

VCM

2281 F04

––

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER AIN+

AIN–

LTC2281

25

0.1µF

ANALOG

INPUT

VCM

AIN+

AIN–

12pF

2281 F05

2.2µF

25

0.1µF

LTC2281

25

25 12

12

0.1µF

AIN+

AIN–

8pF

2.2µF

VCM

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2281 F06

LTC2281

25

0.1µF

AIN+

AIN–

2.2µF

VCM

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2281 F07

LTC2281

25

0.1µF

AIN+

AIN–

2.2µF

VCM

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13

RESISTORS, CAPACITORS, INDUCTORS

ARE 0402 PACKAGE SIZE

2281 F08

8.2nH

LTC2281

2281fb

APPLICATIONS INFORMATION

Reference Operation

Figure 9 shows the LTC2281 reference circuitry consisting

of a 1.5V bandgap reference, a difference ampliﬁ er and

switching and control circuit. The internal voltage reference

can be conﬁ gured for two pin selectable input ranges of

2V (±1V differential) or 1V (±0.5V differential). Tying the

SENSE pin to VDD selects the 2V range; tying the SENSE

pin to VCM selects the 1V range.

The 1.5V bandgap reference serves two functions: its

output provides a DC bias point for setting the common

mode voltage of any external input circuitry; additionally,

the reference is used with a difference ampliﬁ er to gener-

ate the differential reference levels needed by the internal

ADC circuitry. An external bypass capacitor is required

for the 1.5V reference output, VCM. This provides a high

frequency low impedance path to ground for internal and

external circuitry.

Figure 9. Equivalent Reference Circuit

VCM

REFH

SENSE

TIE TO VDD FOR 2V RANGE;

TIE TO VCM FOR 1V RANGE;

RANGE = 2 • VSENSE FOR

0.5V < VSENSE < 1V

1.5V

REFL

2.2µF

INTERNAL ADC

HIGH REFERENCE

BUFFER

0.1µF

2281 F09

DIFF AMP

1µF

INTERNAL ADC

LOW REFERENCE

1.5V BANDGAP

REFERENCE

1V 0.5V

RANGE

DETECT

AND

CONTROL

LTC2281

The difference ampliﬁ er generates the high and low

reference for the ADC. High speed switching circuits are

connected to these outputs and they must be externally

bypassed. Each output has two pins. The multiple output

pins are needed to reduce package inductance. Bypass

capacitors must be connected as shown in Figure 9. Each

ADC channel has an independent reference with its own

bypass capacitors. The two channels can be used with the

same or different input ranges.

Other voltage ranges between the pin selectable ranges

can be programmed with two external resistors as shown

in Figure 10. An external reference can be used by ap-

plying its output directly or through a resistor divider to

SENSE. It is not recommended to drive the SENSE pin

with a logic device. The SENSE pin should be tied to the

appropriate level as close to the converter as possible. If

the SENSE pin is driven externally, it should be bypassed

to ground as close to the device as possible with a 1µF

ceramic capacitor. For the best channel matching, connect

an external reference to SENSEA and SENSEB.

Figure 10. 1.5V Range ADC

VCM

SENSE

1.5V

0.75V

2.2µF

12k

1µF

12k

2281 F10

LTC2281

Input Range

The input range can be set based on the application.

The 2V input range will provide the best signal-to-noise

performance while maintaining excellent SFDR. The 1V

input range will have better SFDR performance, but the

SNR will degrade by 0.9dB. See the Typical Performance

Characteristics section.

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or

TTL level signal. A sinusoidal clock can also be used

along with a low jitter squaring circuit before the CLK pin

(Figure 11).

LTC2281

2281fb

APPLICATIONS INFORMATION

Figure 11. Sinusoidal Single-Ended CLK Drive Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

Figure 13. LVDS or PECL CLK Drive Using a Transformer

CLK

50

0.1µF

4.7µF

FERRITE

BEAD

CLEAN

SUPPLY

SINUSOIDAL

CLOCK

INPUT

2281 F11

NC7SVU04

LTC2281 CLK

100

0.1µF

4.7µF

FERRITE

BEAD

CLEAN

SUPPLY

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

2281 F12

LTC2281

CLK

5pF-30pF

ETC1-1T

0.1µF

VCM

FERRITE

BEAD

DIFFERENTIAL

CLOCK

INPUT

2281 F13

LTC2281

The noise performance of the LTC2281 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

In applications where jitter is critical, such as when digi-

tizing high input frequencies, use as large an amplitude

as possible. Also, if the ADC is clocked with a sinusoidal

signal, ﬁ lter the CLK signal to reduce wideband noise and

distortion products generated by the source.

It is recommended that CLKA and CLKB are shorted to-

gether and driven by the same clock source. If a small time

delay is desired between when the two channels sample

the analog inputs, CLKA and CLKB can be driven by two

different signals. If this delay exceeds 1ns, the performance

of the part may degrade. CLKA and CLKB should not be

driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting a

differential clock to the single-ended CLK input. The use

of a transformer provides no incremental contribution

to phase noise. The LVDS or PECL to CMOS translators

provide little degradation below 70MHz, but at 140MHz will

degrade the SNR compared to the transformer solution.

The nature of the received signals also has a large bear-

ing on how much SNR degradation will be experienced.

For high crest factor signals such as WCDMA or OFDM,

where the nominal power level must be at least 6dB to

8dB below full scale, the use of these translators will have

a lesser impact.

The transformer in the example may be terminated with

the appropriate termination for the signaling in use. The

use of a transformer with a 1:4 impedance ratio may be

desirable in cases where lower voltage differential signals

are considered. The center tap may be bypassed to ground

through a capacitor close to the ADC if the differential

signals originate on a different plane. The use of a ca-

pacitor at the input may result in peaking, and depending

on transmission line length may require a 10 to 20

ohm series resistor to act as both a low pass ﬁ lter for

high frequency noise that may be induced into the clock

line by neighboring digital signals, as well as a damping

mechanism for reﬂ ections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2281 is 125Msps.

The lower limit of the LTC2281 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

LTC2281

2281fb

APPLICATIONS INFORMATION

small valued capacitors. Junction leakage will discharge

the capacitors. The speciﬁ ed minimum operating frequency

for the LTC2281 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures

high performance even if the input clock has a non

50% duty cycle. Using the clock duty cycle stabilizer is

recommended for most applications. To use the clock

duty cycle stabilizer, the MODE pin should be connected

to 1/3VDD or 2/3VDD using external resistors.

This circuit uses the rising edge of the CLK pin to sample

the analog input. The falling edge of CLK is ignored and

the internal falling edge is generated by a phase-locked

loop. The input clock duty cycle can vary from 40% to 60%

and the clock duty cycle stabilizer will maintain a constant

50% internal duty cycle. If the clock is turned off for a

long period of time, the duty cycle stabilizer circuit will

require a hundred clock cycles for the PLL to lock onto the

input clock.

For applications where the sample rate needs to be changed

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken to

make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overﬂ ow bit. Note that

OF is high when an overﬂ ow or underﬂ ow has occured on

either channel A or channel B.

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

(2V Range) OF

D9 – D0

(Offset Binary)

D9 – D0

(2’s Complement)

>+1.000000V

+0.998047V

+0.996094V

11 1111 1111

11 1111 1110

01 1111 1111

01 1111 1110

+0.001953V

0.000000V

–0.001953V

–0.003906V

10 0000 0001

10 0000 0000

01 1111 1111

01 1111 1110

00 0000 0001

00 0000 0000

11 1111 1111

11 1111 1110

–0.998047V

–1.000000V

<–1.000000V

00 0000 0001

00 0000 0000

10 0000 0001

10 0000 0000

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single out-

put buffer. Each buffer is powered by OVDD and OGND,

isolated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50 to external

circuitry and may eliminate the need for external damping

resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2281 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. For full speed

operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Figure 14. Digital Output Buffer

LTC2281

2281 F14

OVDD

VDD VDD

0.1µF

43 TYPICAL

DATA

OUTPUT

OGND

OVDD 0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Data Format

Using the MODE pin, the LTC2281 parallel digital output

can be selected for offset binary or 2’s complement format.

Connecting MODE to GND or 1/3VDD selects offset binary

output format. Connecting MODE to 2/3VDD or VDD selects

2’s complement output format. An external resistor divider

can be used to set the 1/3VDD or 2/3VDD logic values.

Table 2 shows the logic states for the MODE pin.

LTC2281

2281fb

APPLICATIONS INFORMATION

Table 2. MODE Pin Function

MODE PIN OUTPUT FORMAT

CLOCK DUTY

CYCLE STABILIZER

0 Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overﬂ ow Bit

When OF outputs a logic high the converter is either

overranged or underranged on channel A or channel B.

Note that both channels share a common OF pin, which

is not the case for slower pin compatible parts such as

the LTC2280 or LTC2289. OF is disabled when channel A

is in sleep or nap mode.

Output Clock

The ADC has a delayed version of the CLKB input available

as a digital output, CLKOUT. The falling edge of the CLKOUT

pin can be used to latch the digital output data. CLKOUT

is disabled when channel B is in sleep or nap mode.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven.

For example, if the converter is driving a DSP powered

by a 1.8V supply, then OVDD should be tied to that same

1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND

up to 1V and must be less than OVDD. The logic outputs

will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE high disables all data outputs including OF. The

data access and bus relinquish times are too slow to

allow the outputs to be enabled and disabled during full

speed operation. The output Hi-Z state is intended for use

during long periods of inactivity. Channels A and B have

independent output enable pins (OEA, OEB).

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to

conserve power. Connecting SHDN to GND results in normal

operation. Connecting SHDN to VDD and OE to VDD results

in sleep mode, which powers down all circuitry including

the reference and typically dissipates 1mW. When exiting

sleep mode it will take milliseconds for the output data

to become valid because the reference capacitors have to

recharge and stabilize. Connecting SHDN to VDD and OE

to GND results in nap mode, which typically dissipates

30mW. In nap mode, the on-chip reference circuit is kept

on, so that recovery from nap mode is faster than that

from sleep mode, typically taking 100 clock cycles. In both

sleep and nap modes, all digital outputs are disabled and

enter the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA,

SHDNB). Channel A is controlled by SHDNA and OEA,

and Channel B is controlled by SHDNB and OEB. The

nap, sleep and output enable modes of the two channels

are completely independent, so it is possible to have one

channel operating while the other channel is in nap or

sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2281 can be multiplexed onto

a single data bus if the sample rate is 80Msps or less. The

MUX pin is a digital input that swaps the two data bus-

ses. If MUX is High, Channel A comes out on DA0-DA9;

Channel B comes out on DB0-DB9. If MUX is Low, the

output busses are swapped and Channel A comes out on

DB0-DB9; Channel B comes out on DA0-DA9. To multiplex

both channels onto a single output bus, connect MUX,

CLKA and CLKB together (see the Timing Diagram for

the multiplexed mode). The multiplexed data is available

on either data bus—the unused data bus can be disabled

with its OE pin.

Grounding and Bypassing

The LTC2281 requires a printed circuit board with a clean,

unbroken ground plane. A multilayer board with an internal

ground plane is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

LTC2281

2281fb

APPLICATIONS INFORMATION

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

tors must be located as close to the pins as possible. Of

particular importance is the 0.1µF capacitor between REFH

and REFL. This capacitor should be placed as close to the

device as possible (1.5mm or less). A size 0402 ceramic

capacitor is recommended. The large 2.2µF capacitor be-

tween REFH and REFL can be somewhat further away. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

The LTC2281 differential inputs should run parallel and

close to each other. The input traces should be as short

as possible to minimize capacitance and to minimize

noise pickup.

Heat Transfer

Most of the heat generated by the LTC2281 is transferred

from the die through the bottom-side Exposed Pad and

package leads onto the printed circuit board. For good

electrical and thermal performance, the Exposed Pad

should be soldered to a large grounded pad on the PC

board. It is critical that all ground pins are connected to

a ground plane of sufﬁ cient area.

Clock Sources for Undersampling

Undersampling is especially demanding on the clock

source, and the higher the input frequency, the greater the

sensitivity to clock jitter or phase noise. A clock source that

degrades SNR of a full-scale signal by 1dB at 70MHz will

degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is

relatively unimportant and only a single ADC is required,

a 3V canned oscillator from vendors such as Saronix

or Vectron can be placed close to the ADC and simply

connected directly to the ADC. If there is any distance to

the ADC, some source termination to reduce ringing that

may occur even over a fraction of an inch is advisable.

You must not allow the clock to overshoot the supplies or

performance will suffer. Do not ﬁ lter the clock signal with

a narrow band ﬁ lter unless you have a sinusoidal clock

source, as the rise and fall time artifacts present in typical

digital clock signals will be translated into phase noise.

The lowest phase noise oscillators have single-ended

sinusoidal outputs, and for these devices the use of a ﬁ lter

close to the ADC may be beneﬁ cial. This ﬁ lter should be

close to the ADC to both reduce roundtrip reﬂ ection times,

as well as reduce the susceptibility of the traces between

the ﬁ lter and the ADC. If the circuit is sensitive to close-

in phase noise, the power supply for oscillators and any

buffers must be very stable, or propagation delay variation

with supply will translate into phase noise. Even though

these clock sources may be regarded as digital devices, do

not operate them on a digital supply. If your clock is also

used to drive digital devices such as an FPGA, you should

locate the oscillator, and any clock fan-out devices close to

the ADC, and give the routing to the ADC precedence. The

clock signals to the FPGA should have series termination at

the driver to prevent high frequency noise from the FPGA

disturbing the substrate of the clock fan-out device. If you

use an FPGA as a programmable divider, you must re-time

the signal using the original oscillator, and the re-timing

ﬂ ip-ﬂ op as well as the oscillator should be close to the

ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the

clock source originates some distance away, differential

clock distribution is advisable. This is advisable both from

the perspective of EMI, but also to avoid receiving noise

from digital sources both radiated, as well as propagated in

the waveguides that exist between the layers of multilayer

PCBs. The differential pairs must be close together and

distanced from other signals. The differential pair should

be guarded on both sides with copper distanced at least

3x the distance between the traces, and grounded with

vias no more than 1/4 inch apart.

LTC2281

2281fb

APPLICATIONS INFORMATION

Evaluation Circuit Schematic of the LTC2281

C21

0.1µF

C27

0.1µF

VDD

OVDD

VCMB

C20

2.2µF

C18 1µF

C23 1µF

C34

0.1µF

C31

C17

0.1µF

C14

0.1µF

C25

0.1µF

C28

2.2µF

C35

0.1µF

C24

0.1µF

C36

4.7µF

VDD

PWR

GND

VDD OVDD

2281 AI01

0.1µF

R32

OPT

R39

R10

R14

49.9

R20

24.9

R18

R24

R17

OPT

R22

24.9

R23

51

C29

0.1µF

C33

0.1µF

CLOCK

INPUT

NC7SVU04

NC7SV86P5X

C15

0.1µF

C12

4.7µF

6.3V

BEAD

VDD

C19

0.1µF

C11

0.1µF

2.2µF

C10

2.2µF

C9 1µF

C13 1µF

R15

ANALOG

INPUT B

QDVDD

••

VCMB

0.1µF

C44

0.1µF

24.9

OPT

24.9

51

0.1µF

ANALOG

INPUT A

••

VCMA

VDD

2/3VDD

1/3VDD

GND

JP1 MODE

R34

4.7k

C39

1µF

VDD

OVDD

BYP

OUT

U12

LT1761ES5-BYP

ADJ C38

0.01µF

C46

0.1µF

GND

C45

100µF

6.3V

OPT

C40

0.1µF

C48

0.1µF

C47

0.1µF

EXT

REF B

VDD

VCM

VDD

VCMB

EXT REF

JP3 SENSEB

EXT

REF A

VDD

VCM

VDD

EXT REF

JP2 SENSEA

0.1µF

OVDD

FXLH42245MPX

24LC025

VCC

SCL

SDA

100

QDVDD

VSS

SCL

SDA

R33

4.7k

ENABLE

VCCIN

EDGE-CON-100

R35

100k

+C41

0.1µF

QDVDD

C52

0.1µF

C55

0.1µF

C54

0.1µF

C53

0.1µF

R38

4.99k

R37

4.99k

R36

4.99k

SCL

VCCIN

VSS

SDA

ASSEMBLY TYPE

DC1098A-A

DC1098A-B

DC1098A-C

DC1098A-D

DC1098A-E

DC1098A-F

LTC2281IUP

LTC2283IUP

LTC2285IUP

LTC2281IUP

LTC2283IUP

LTC2285IUP

R5, R9, R18, R24

24.9

12.4

C6, C31

12pF

8pF

T1, T2

MABAES0060

MABA-007159-000000

INPUT FREQUENCY

1MHz < AIN < 70MHz

70MHz < AIN < 140MHz

*VERSION TABLE

Msps

125

BITS

AINA+

AINA–

REFHA

REFLA

VDD

CLKA

CLKB

VDD

REFLB

REFHB

AINB–

AINB+

DA3

DA2

DA1

DA0

CLKOUT

DB9

DB8

DB7

DB6

DB5

DB4

DB3

GND

VDD

SENSEA

VCMA

MODE

SHDNA

OEA

DA9

DA8

DA7

DA6

DA5

DA4

OGND

OVDD

GND

VDD

SENSEB

VCMB

MUX

SHDNB

OEB

DB0

DB1

DB2

OGND

OVDD

LTC2281

124 23

VCCA VCCB VCCB

OVDD OVDD

QDVDD

T/R

GND GND GND GND

EXPOSED

PAD

11 12 13 25

U11

FXLH42245MPX

124 23

VCCA VCCB VCCB

OVDD QDVDD

T/R

GND GND GND GND

EXPOSED

PAD

11 12 13 25

U10

FXLH42245MPX

124 23

VCCA VCCB VCCB

OVDD QDVDD

T/R

GND GND GND GND

EXPOSED

PAD

11 12 13 25

FXLH42245MPX

124 23

VCCA VCCB VCCB

OVDD QDVDD

T/R

GND GND GND GND

EXPOSED

PAD

11 12 13 25

R42

GND

C37

10µF

6.3V

R25

105k

R25

105k

C51

1µF

VDD

QDVDD

BYP

OUT

U13

LT1761ES5-BYP

ADJ C49

0.01µF

GND

C50

10µF

6.3V

R40

105k

R41

100k

LTC2281

2281fb

APPLICATIONS INFORMATION

Silkscreen Top

Top Side

LTC2281

2281fb

APPLICATIONS INFORMATION

Inner Layer 2 GND Inner Layer 3 Power

Bottom Side

LTC2281

2281fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

9 .00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

PIN 1 TOP MARK

(SEE NOTE 5)

0.40 ± 0.10

6463

BOTTOM VIEW—EXPOSED PAD

7.15 ± 0.10

7.50 REF

(4-SIDES)

0.75 ± 0.05

R = 0.10

TYP

R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UP64) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

7.50 REF

(4 SIDES)

7.15 ±0.05

8.10 ±0.05 9.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

PIN 1

CHAMFER

C = 0.35

LTC2281

2281fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1207 REV B • PRINTED IN USA

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package

LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR

LTC1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain

LTC1994 Low Noise, Low Distortion Fully Differential Input/Output

Ampliﬁ er/Driver

Low Distortion: –94dB at 1MHz

LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN Package

LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package

LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN Package

LTC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN Package

LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN Package

LTC2255 14-Bit, 125Msps ADC, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN Package

LTC2280 10-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 320mW, 61.6dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2282 12-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN Package

LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN Package

LTC2286 10-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2287 10-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2288 10-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2289 10-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 422mW, 61.6dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2290 12-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk 120mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2291 12-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2292 12-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2293 12-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2294 12-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 422mW, 70.6dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2295 14-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk 120mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2296 14-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 74.5dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2297 14-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2298 14-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 74.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2299 14-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 444mW, 73dB SNR, 90dB SFDR, 64-Pin QFN Package

LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

LT5514 Ultralow Distortion IF Ampliﬁ er/ADC Driver with Digitally

Controlled Gain

450MHz to 1dB BW, 47dB OIP3, Digital Gain Control

10.5dB to 33dB in 1.5dB/Step

LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator

LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator

LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,

50Ω Single Ended RF and LO Ports