MX29SL402CTGBI-90G - Macronix International Co., Ltd.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

4M-BIT [512K x 8 / 256K x 16] SINGLE VOLTAGE

1.8V ONLY FLASH MEMORY

FEATURES

GENERAL FEA TURES

• Single P ower Supply Operatio n

- 1.65 to 2.2 volt fo r read, erase, and pro gram o peratio ns

• 524,288 x 8 / 262,144 x 16 switchable

• Boot Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Secto r Structure

- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 7

• Sector protection

- Hardware method to disable any combination of sectors from program or erase operations

- Temporary sector unprotected allows code changes in previously locked sectors

• Latch-up protected to 100mA fro m -1V to Vcc + 1V

• Co mpatible with JEDEC standard

- Pino ut and so ftware co mpatible to single power supply Flash

PERFORMANCE

• High Performance

- Access time: 90ns

- Byte/Wo rd pro gram time: 12us/18us (typical)

- Erase time: 1.3s/secto r, 9s/chip (typical)

• Low P ower Consumption

- Low active read current: 6mA (maximum) at 5MHz

- Low standby current: 1uA (typical)

• Typical 100,000 erase/pro gram cycle

• 10 years data retention

SOFTW ARE FEA TURES

• Erase Suspend/ Erase Resume

- Suspends secto r erase o peration to read data fro m o r program data to ano ther secto r which is not being erased

• Status Reply

- Data# Polling & T o ggle bits pro vide detectio n o f program and erase operation completio n

• Suppo rt Commo n Flash Interface (CFI)

HARDWARE FEATURES

• Ready/Busy# (R Y/BY#) Output

- Pro vides a hardware metho d of detecting pro gram and erase o peratio n completio n

• Hardware Reset (RESET#) Input

- Pro vides a hardware metho d to reset the internal state machine to read mode

PACKAGE

• 48-Pin TSOP

• 48-Ball FBGA (6x8x1.2mm, 6x8x1.3mm,4x6x0.75mm)

• 48-Ball XFLGA (4x6x0.5mm)

•All Pb-free devices are RoHS Compliant

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

PIN CONFIGURATIONS

48 TSOP (Standard T ype) (12mm x 20mm)

48-Ball CSP (6x8x1.2mm/6x8x1.3mm, Ball Pitch=0.8mm), Top View, Balls Facing Down

ABCDEFGH

WE#

RY/BY#

RE-

SET#

A17

A10

A11

Q14

Q12

Q10

CE#

Q13

VCC

Q11

OE#

GND

A13 A12 A14 A15 A16 BYTE# Q15/

A-1 GND

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

OE#

GND

CE#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

48-Ball CSP(4x6x0.75mm, Ball Pitch=0.5mm), T op View, Balls Facing Down

48-Ball XFLGA (4x6x0.5mm, Land Pitch=0.5mm), T op View , Balls Facing Down

AB CDEF HGJ

CE#

GND

OE#

Q10

Q2 Q3 VCC Q12

Q13

A10

A2 A4 A6 A17 NC NC WE# NC A9

Q14

A13

A11

A12

Q11

Q15

A14

A15

A16

GND

AB CDEF HGJ

CE#

GND

OE#

Q10

BYTE#

Q2 Q3 VCC Q12

Q13

A10

A2 A4 A6 A17 NC NC WE# RE-

SET# A9

Q14

A13

A11

A12

Q11

Q15/

A-1

A14

A15

A16

GND

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17 Address Input

Q0~Q14 Data Input/Output

Q15/A-1 Q15 (data input/o utput, word mo de)/

A-1(LSB address input, byte mo de)

CE# Chip Enable Input

WE# Write Enable Input

BYTE# Wo rd/Byte Selectio n input

RESET# Hardware Reset Pin

OE# Output Enable Input

R Y/BY# Ready/Busy Output

VCC P ower Supply Pin (1.65V~2.2V)

GND Ground Pin

LOGIC SYMBOL

16 or 8

Q0-Q15

(A-1)

RY/BY#

A0-A17

CE#

OE#

WE#

RESET#

BYTE#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-AM

AM: MSB address

CE#

OE#

WE#

RESET#

BYTE#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Table 1. BLOCK STRUCTURE

MX29SL402CT SECTOR ARCHITECTURE

Sector Sector Size Address range Sector Address

Byte Mode Word Mode Byte Mode (x8) W ord Mode (x16) A17 A16 A15 A14 A13 A12

SA0 64Kbytes 32Kwords 00000h-0FFFFh 00000h-07FFFh 0 0 0 X X X

SA1 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0 0 1 X X X

SA2 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0 1 0 X X X

SA3 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0 1 1 X X X

SA4 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 1 0 0 X X X

SA5 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 1 0 1 X X X

SA6 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 1 1 0 X X X

SA7 32Kbytes 16Kwords 70000h-77FFFh 38000h-3BFFFh 1110XX

SA8 8Kbytes 4Kwords 78000h-79FFFh 3C000h-3CFFFh 11110 0

SA9 8Kbytes 4Kwords 7A000h-7BFFFh 3D000h-3DFFFh 11110 1

SA10 16Kbytes 8Kwords 7C000h-7FFFFh 3E000h-3FFFFh 11111X

Sector Sector Size Address range Sector Address

Byte Mode Word Mode Byte Mode (x8) W ord Mode (x16) A17 A16 A15 A14 A13 A12

SA0 16Kbytes 8Kwords 00000h-03FFFh 00000h-01FFFh 00000X

SA1 8Kbytes 4Kwords 04000h-05FFFh 02000h-02FFFh 00001 0

SA2 8Kbytes 4Kwords 06000h-07FFFh 03000h-03FFFh 00001 1

SA3 32Kbytes 16Kwords 08000h-0FFFFh 04000h-07FFFh 0001XX

SA4 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0 0 1 X X X

SA5 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0 1 0 X X X

SA6 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0 1 1 X X X

SA7 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 1 0 0 X X X

SA8 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 1 0 1 X X X

SA9 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 1 1 0 X X X

SA10 64Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 1 1 1 X X X

MX29SL402CB SECTOR ARCHITECTURE

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

T able 2. BUS OPERA TION

Notes:

1. Vhv is the very high voltage, 10V to 11V.

2. X means input high (Vih) or input low (Vil).

3. SA means sector address: A12~A17.

4. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

ADDRESS

DESCRIPTION CE# OE# WE#RESET# A17 A11 A9 A8 A6 A5 A1 A 0 Q0~Q7 BYTE# BYTE#=Vil

A12 A10

Read L L H H AIN Dout Dout Q8~Q14

=High Z A-1

Vhv

Write L H L H AIN

Reset X X X L X High Z High Z High Z

Temporary sector

Unprotection

Output Disable L H H H X High Z High Z High Z

Standby VCC±X X VCC± X High Z High Z High Z

0.3V 0.3V

Secto r Pro tect L H L

Chip Unprotected L H L

Secto r Protectio n Verify L L H H SA X

=Vih Q8~Q14 Q15/A-1

Q8~Q15

XXX AIN DIN D IN High Z

X L X H L CODE(4) X X

SA X X X L X H L DIN X X

XXXXHXHL DIN X X

A7 A2

DINDIN

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

REQUIREMENTS FOR READING ARRAY DA T A

Read arra y action is to read the data sto red in the arra y out. While the memory device is in po wered up or has been

reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the

arra y , it has to drive CE# (de vice enable co ntro l pin) and OE# (Output co ntro l pin) as Vil, and input the address o f the

data to be read into address pin at the same time. After a perio d o f read cycle (Tce or Taa), the data being read o ut will

be displa yed o n o utput pin fo r micro pro cesso r to access. If CE# o r OE# is Vih, the o utput will be in tri-state, and there

will be no data displa yed on o utput pin at all.

After the memo ry device co mpletes embedded o peration (automatic Erase or Pro gram), it will auto matically return to

the status o f read arra y, and the device can read the data in any address in the arra y. In the pro cess o f erasing, if the

device receives the Erase suspend command, erase operation will be stopped after a per iod of time no more than

Tready1 and the de vice will return to the status o f read arra y. At this time , the device can read the data stored in any

address e xcept the secto r being erased in the arra y. In the status o f erase suspend, if user wants to read the data in

the secto rs being er ased, the device will output status data o nto the o utput. Similarly, if pro gram command is issued

after erase suspend, after pro gram o peratio n is completed, system can still read array data in any address except the

secto rs to be er ased.

The device needs to issue reset co mmand to enable read arra y operatio n again in order to arbitrarily read the data in

the arra y in the following two situatio ns:

1. In pro gram o r erase o peratio n, the programming o r erasing f ailure causes Q5 to go high.

2. The de vice is in auto select mode o r CFI mode.

In the two situations above, if reset command is not issued, the device is not in read array mode and system must

issue reset co mmand befo re reading array data.

WRITE COMMANDS/COMMAND SEQUENCES

To write a co mmand to the de vice, system must driv e WE# and CE# to Vil, and OE# to Vih. In a co mmand cycle, all

address are latched at the later falling edge o f CE# and WE#, and all data are latched at the earlier rising edge of CE#

and WE#.

Figure 1 illustrates the A C timing wavefo rm of a write command, and Table 3 defines all the valid co mmand sets o f the

device. System is not allowed to write invalid co mmands no t defined in this datasheet. Writing an invalid command will

bring the device to an undefined state.

RESET# OPERA TION

Driving RESET# pin low f or a perio d mo re than Trp will reset the device back to read mo de. If the device is in pro gram

o r erase o peration, the reset operatio n will take at mo st a period o f Tready1 fo r the device to return to read array mode.

Bef o re the de vice returns to read array mo d e, the R Y/BY# pin remains low (b usy status).

When RESET# pin is held at GND±0.3V, the de vice consumes standby current(Isb).However, device draws larger

current if RESET# pin is held at Vil b ut not within GND±0.3V.

It is reco mmended that the system to tie its reset signal to RESET# pin of flash memo ry , so that the flash memo ry will

be reset during system reset and allows system to read bo ot co de fro m flash memo ry.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

SECTOR PROTECT OPERA TION

When a secto r is protected, program o r erase o peratio n will be disabled o n these sectors. MX29SL402C T/B pro vides

two metho ds fo r secto r protectio n.

Once the secto r is pro tected, the sector remains pro tected until next chip unprotect, o r is tempo rarily unpro tected by

asserting RESET# pin at Vhv . Ref er to tempo rary secto r unpro tect o peratio n fo r further details.

The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the

algo rithm fo r this metho d.

The o ther method is asserting Vhv o n A9 and OE# pins, with A6 and CE# at Vil. The protection o peratio n begins at the

f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix f o r details.

CHIP UNPROTECT OPERA TION

MX29SL402C T/B pro vides two metho ds fo r chip unprotect. The chip unprotect o peration unprotects all secto rs within

the device. It is reco mmended to protect all sectors befo re activating chip unpro tect mo de. All secto rs are unprotected

when shipped fro m the facto ry.

The first metho d is by applying Vhv o n RESET# pin. Refer to Figure 12 fo r timing diagram and Figure 13 fo r algorithm

o f the operation.

The other method is asserting Vhv o n A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect

o peratio n begins at the f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix fo r details.

TEMPORAR Y SECTOR UNPROTECT OPERA TION

System can apply RESET# pin at Vhv to place the device in temporar y unprotect mode. In this mode, previously

pro tected sectors can be pro grammed o r erased just as it is unprotected. The devices returns to normal operatio n once

Vhv is remo v ed fro m RESET# pin and previo usly pro tected secto rs are again pro tected.

AUTOMA TIC SELECT OPERA TION

When the device is in Read array mo de, erase-suspended read arra y mode o r CFI mode, user can issue read silicon

ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs

continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix

Manufacture ID C2. When A0 is high, device will output Device ID . In read silicon ID mo de, issuing reset co mmand will

reset device back to read array mo de or erase-suspended read array mo de.

Ano ther way to enter read silico n ID is to apply high vo ltage o n A9 pin with CE#, OE#, A6 and A1 at Vil. While the high

v o ltage o f A9 pin is discharged, device will automatically leav e read silico n ID mo de and go back to read arra y mo de

or erase-suspended read arra y mo d e. When A0 is Lo w, de vice will o utput Macronix Manuf acture ID C2. When A0 is

high, de vice will output Device ID.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

VERIFY SECT OR PROTECT ST ATUS OPERA TION

MX29SL402C T/B pro vides hardware sector pro tection against Program and Erase o peratio n fo r protected sectors. The

secto r pro tect status can be read thro ugh Secto r Pro tect V erify co mmand. This metho d requires Vhv o n A9 pin, Vih o n

WE# and A1 pins, Vil o n CE#, OE#, A6 and A0 pins , and sector address on A12 to A17 pins. If the read o ut data is

01H, the designated secto r is protected. Oppo sitely , if the read o ut data is 00H, the designated sector is still not being

protected.

DA T A PROTECTION

To avoid accidental erasure o r pro gramming o f the device, the device is automatically reset to read arra y mode during

pow er up. Besides, o nly after successful co mpletio n o f the specified co mmand sets will the de vice begin its erase o r

program operation.

Other features to pro tect the data fro m accidental alternation are described as fo llowed.

WRITE PULSE "GLITCH" PRO TECTION

CE#, WE#, OE# pulses sho rter than 5ns are treated as glitches and will no t be regarded as an effectiv e write cycle.

LOGICAL INHIBIT

A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is igno red when either CE# at Vih,

WE# a Vih, o r OE# at Vil.

POWER-UP SEQUENCE

Upo n power up, MX29SL402C T/B is placed in read array mo de. Furthermo re, pro gram o r erase o peratio n will begin

o nly after successful co mpletio n of specified co mmand sequences.

POWER-UP WRITE INHIBIT

When WE#, CE# is held at Vil and OE# is held at Vih during pow er up , the device igno res the first command o n the

rising edge of WE#.

PO WER SUPPLY DECOUPLING

A 0.1uF capacito r sho uld be connected between the Vcc and GND to reduce the no ise effect.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

TABLE 3. MX29SL402C T/B COMMAND DEFINITIONS

Notes:

1. De vice ID: 2270H/70H fo r Top Bo o t Secto r device.

22F1H/F1H for Bottom Boot Sector device.

2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been

protected.

3. Sector Protect co mmand is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc

is for protect verify.

Hex Word Byte Word Byte Word Byte Word Byte

1st Bus Cyc Addr Addr XXX 555 AAA 555 AAA 555 AAA 555 AAA

Data Data F0 AA AA AA AA AA AA AA AA

2nd Bus Cyc Addr 2AA 555 2AA 555 2AA 555 2AA 555

Data 55 55 55 55 55 55 55 55

3rd Bus Cyc Addr 555 AAA 555 AAA 555 AAA 555 AAA

Data 90 90 90 90 90 90 A0 A0

4th B us Cy c A ddr X 00 X 00 X 01 X 02 (Sector)

X02 (Sector)

X04 Addr Addr

Data C2H C2H ID ID 00/01 00/01 Data Data

5th B us Cy c A ddr

Data

6th B us Cy c A ddr

Data

ProgramCommand Read

Mode Reset

Mode Silicon ID Device ID Sector Protect

Verify

Automatic S elect

Hex Word Byte Word Byte Word Byte Word/Byte W ord/Byte

1s t B us Cyc A ddr 555 A AA 555 A A A 55 A A XXX XXX

Data AA AA AA AA 98 98 B0 30

2nd B us Cy c A ddr 2A A 555 2A A 555

Data 55 55 55 55

3rd B us Cy c Addr 555 A AA 555 A A A

Data 80 80 80 80

4th B us Cy c A ddr 555 A A A 555 AA A

Data AA AA AA AA

5th B us Cy c Addr 2A A 555 2A A 555

Data 55 55 55 55

6th B us Cy c A ddr 555 A A A S ec t or Sec t or

Data 10 10 30 30

CFI Read Erase

Suspend Erase

Resume

Com m and Chip E ras e S ec t or Eras e

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

RESET

In the f ollowing situations, e x ecuting reset co mmand will reset device back to read arr a y mode:

•Amo ng erase command sequence (befo re the full command set is co mpleted)

•Secto r erase time-o ut perio d

•Erase fail (while Q5 is high)

•Among program command sequence (before the full command set is completed, erase-suspended program in-

cluded)

•Pro gram fail (while Q5 is high, and erase-suspended pro gram fail is included)

•Read silico n ID mo de

•Secto r protect verify

•CFI mo de

While de vice is at the status o f prog ram fail o r erase f ail (Q5 is high), user must issue reset co mmand to reset device

back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must

issue reset command to reset de vice back to read arra y mode.

When the de vice is in program mode (not pro gram f ail) or erase mo de (not erase f ail), de vice will ignore reset co m-

mand.

AUTOMA TIC SELECT COMMAND SEQUENCE

Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is

protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a

specific command. The fourth cycle is a no rmal read cycle, and user can read at any address any number of times

witho ut entering another command sequence. The reset command is necessary to exit the Auto matic Select mode and

back to read array. The fo llowing tab le shows the identificatio n co de with correspo nding address.

Address Data (Hex) Representation

Manufacturer ID W o rd X00 00C2

Byte X00 C2

Device ID W ord X01 2270/22F1 Top/Bo ttom Bo ot Sector

Byte X02 70/F1 Top/Bottom Bo ot Sector

Secto r Pro tect V erify Wo r d (Secto r address) X 02 00/01 Unprotected/protected

Byte (Secto r address) X 04 00/01 Unprotected/protected

There is an alternative metho d to that shown in Table 3, which is intended fo r EPROM pro grammers and requires Vhv

o n address bit A9.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

AUTOMA TIC PROGRAMMING

The MX29SL402C T/B can pro vide the user program functio n by the form o f Byte-Mode o r W ord-Mo de. As long as the

users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will

auto matically be programmed into the array.

Once the pro gram function is executed, the internal write state controller will auto matically execute the algo rithms and

timings necessary fo r pro gram and verificatio n, which includes generating suitable pro gram pulse, verifying whether

the threshold vo ltage of the pro grammed cell is high enough and repeating the program pulse if any o f the cells does not

pass verificatio n. Meanwhile, the internal co ntro l will pro hibit the programming to cells that pass verificatio n while the

o ther cells fail in verificatio n in o rder to avo id o v er-pro gramming.

Pro gramming will o nly change the bit status from "1" to "0". That is to say, it is impossible to co nvert the bit status fro m

"0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not

successfully pro grammed to "0".

Any co mmand written to the device during programming will be igno red except hardware reset, which will terminate the

pro gram o peration after a perio d of time no mo re than T ready1. When the embedded program algo rithm is complete o r

the pro gram o peratio n is terminated by hardware reset, the de vice will return to the reading array data mo de.

With the internal write state co ntroller , the device requires the user to write the pro gram co mmand and data only. The

typical chip pro gram time at ro om temperature o f the MX29SL402C T/B is 4.8 seconds. (Wo rd-Mo de)

When the embedded program o peration is on go ing, user can confirm if the embedded operation is finished or not by the

fo llowing metho ds:

Status Q7 Q6 Q5 RY/BY#*2

In progress*1 Q7# To ggling 0 0

Finished Q7 Stop toggling 0 1

Exceed time limit Q7# Toggling 1 0

*1: The status "in progress" means bo th pro gram mo de and erase-suspended program mo de.

*2: RY/BY# is an o pen drain o utput pin and should be weakly co nnected to VDD through a pull-up resisto r .

*3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to

toggle for about 1us or less and the device returns to read array state without programing the data in the protected

sector.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

SECTOR ERASE

Secto r Erase is to erase all the data in a secto r with "1" and "0" as all "1". It requires six co mmand cycles to issue. The

first two cycles are "unlock cycles", the third o ne is a configuratio n cycle, the f o urth and fifth are also "unlo ck cycles"

and the sixth cycle is the secto r erase command. After the sector erase co mmand sequence is issued, there is a time-

o ut period of 50us counted internally . During the time-o ut period, additional secto r address and sector erase co mmand

can be written multiply. Once user enters ano ther sector erase co mmand, the time-o ut perio d of 50us is reco unted. If

user enters any co mmand other than sector erase o r erase suspend during time-out period, the erase co mmand would

be abor ted and the device is reset to read array condition. The number of sectors could be from one sector to all

secto rs. After time-o ut perio d passing by, additional erase co mmand is no t accepted and erase embedded o peratio n

begins.

During sector erasing, all commands will not be accepted except hardw are reset and erase suspend and user can

check the status as chip erase.

When the embedded chip erase o peratio n is on go ing, user can confirm if the embedded operatio n is finished o r no t by

the fo llowing methods:

Status Q7 Q6 Q5 Q2 RY/BY#

In pro gress 0 To ggling 0 Toggling 0

Finished 1 Stop toggling 0 1 1

Exceed time limit 0 Toggling 1 Toggling 0

When the embedded erase o peration is o n go ing, user can confirm if the embedded o peratio n is finished or no t by the

fo llowing metho ds:

Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2

Time-out period 0 To ggling 0 0 Toggling 0

In pro gress 0 To ggling 0 1 Toggling 0

Finished 1 Stop toggling 0 1 1 1

Exceed time limit 0 Toggling 1 1 Toggling 0

CHIP ERASE

Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the actio n in, and the first two

cycles are "unlo ck" cycles , the third o ne is a co nfiguration cycle, the fourth and fifth are also "unlo ck" cycles , and the

sixth cycle is the chip erase operatio n.

During chip erasing, all the commands will not be accepted except hardware rests o r the wo rking voltage is to o low that

chip erase will be interrupted. After Chip Erase, the chip will return to the state o f Read Arra y.

*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to

ano ther secto r address to be erased. When Q3=1, the de vice is in erase o peratio n and o nly er ase suspend is valid.

*2: R Y/BY# is open drain o utput pin and sho uld be weakly co nnected to VDD thro ugh a pull-up resistor .

*3: When an attempt is made to erase a pro tected sector , Q7 will output its complement data o r Q6 continues to to ggle

f o r 100us o r less and the de vice returned to read arra y status witho ut erasing the data in the pro tected secto r .

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

When the device has suspended er asing, user can e x ecute the co mmand sets e xcept secto r erase and chip erase ,

such as read silico n ID , secto r pro tect v erify, pro gram, CFI query and erase resume.

SECTOR ERASE RESUME

Secto r erase resume co mmand is v alid only when the de vice is in erase suspend state. After erase resume, user can

issue another erase suspend command, but there should be a 10ms interval between erase resume and the next

erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for

erasing will increase.

Status Q7 Q6 Q5 Q3 Q2 RY/BY#

Erase suspend read in erase suspended secto r 1 1 0 0 To ggle 1

Erase suspend read in no n-erase suspended secto r Data Data Data Data Data 1

Erase suspend pro gram in no n-erase suspended sector Q7# Toggle 0 0 1 0

SECTOR ERASE SUSPEND

During sector erasure, secto r erase suspend is the o nly valid co mmand. If user issue erase suspend co mmand in the

time-o ut perio d o f sector erasure, device time-o ut period will be over immediately and the device will go back to erase-

suspended read array mo de. If user issue erase suspend co mmand during the sector erase is being o perated, device

will suspend the o ngo ing er ase o peratio n, and after the Tready1(<=20us) suspend finishes and the de vice will enter

erase-suspended read array mode. User can judge if the device has finished erase suspend thro ugh Q6, Q7, and R Y/

BY#.

After device has entered erase-suspended read array mo de, user can read other sectors not at erase suspend by the

speed o f Taa; while reading the secto r in erase-suspend mo de, device will o utput its status. User can use Q6 and Q2

to judge the secto r is erasing or the erase is suspended.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

QUER Y COMMAND AND COMMON FLASH INTERFACE (CFI) MODE

MX29SL402C T/B f eatures CFI mo de. Ho st system can retrie ve the o perating characteristics, structure and vendo r-

specified information such as identifying information, memory size , b yte/word configuration, oper ating vo ltages and

timing info rmation o f this device by CFI mo de. The device enters the CFI Query mo de when the system writes the CFI

Query command, 98H, to address 55H/AAH (depending on Word/Byte mode) any time the device is ready to read

array data. The system can read CFI info rmation at the addresses given in Table 4. A reset command is required to exit

CFI mo de and go back to ready arr ay mo de o r erase suspend mo de. The system can write the CFI Query co mmand

o nly when the de vice is in read mo de, erase suspend, standb y mo de o r auto matic select mode..

T ABLE 4-1. CFI mode: Identification Data V alues

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query-unique ASCII string "QRY" 2 0 10 0051

22 11 0052

24 12 0059

Primary vendor command set and control interface ID code 2 6 13 0002

28 14 0000

Address for primary algorithm extended query table 2A 15 0040

2C 16 0000

Alternate vendor command set and control interface ID code (none) 2E 1 7 0000

30 18 0000

Address for secondary algorithm extended query table (none) 32 1 9 0000

34 1A 0000

T ABLE 4-2. CFI Mode: System Interface Data V alues

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

VCC supply, minimum (1.65V) 3 6 1B 0016

VCC supply, maximum (2.2V) 3 8 1C 0022

VPP supply, minimum (none) 3A 1 D 0000

VPP supply, maximum (none) 3 C 1E 0000

Typical timeout for single word/byte write (2N us) 3E 1F 0004

Typical timeout for Minimum size buffer write (2N us) 4 0 2 0 0000

Typical timeout for individual block erase (2N ms) 4 2 2 1 000A

Typical timeout for full chip erase (2N ms) 4 4 22 0000

Maximum timeout for single word/byte write times (2N X Typ) 46 2 3 0005

Maximum timeout for buffer write times (2N X Typ) 4 8 24 0000

Maximum timeout for individual block erase times (2N X Typ) 4A 25 0004

Maximum timeout for full chip erase times (not supported) 4C 26 0000

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

T ABLE 4-3. CFI Mode: Device Geometry Data V alues

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Device size (2N bytes) 4E 27 0013

Flash device interface code (refer to the CFI publication 100) 5 0 2 8 0002

52 29 0000

Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000

56 2B 0000

Number of erase block regions 5 8 2 C 0004

Index for Erase Bank Area 1 (refer to the CFI publication 100) 5A 2 D 0000

5C 2E 0000

5E 2F 0040

60 30 0000

Index for Erase Bank Area 2 62 3 1 0001

64 32 0000

66 33 0020

68 34 0000

Index for Erase Bank Area 3 6A 35 0000

6C 36 0000

6E 37 0080

70 38 0000

Index for Erase Bank Area 4 72 3 9 0006

74 3A 0000

76 3B 0000

78 3C 0001

T ABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data V alues

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query - Primary extended table, unique ASCII string, PRI 8 0 4 0 0050

82 41 0052

84 42 0049

Major version number, ASCII 8 6 4 3 0031

Minor version number, ASCII 8 8 4 4 0030

Unlock recognizes address (0= recognize, 1= don't recognize) 8A 4 5 0000

Erase suspend (2= to both read and program) 8 C 4 6 0002

Sector protect (N= # of sectors/group) 8E 4 7 0001

Temporary sector unprotected (1=supported) 90 48 0001

Sector protect/unprotected scheme 92 49 0004

Simultaneous R/W operation (0=not supported) 94 4A 0000

Burst mode (0=not supported) 96 4B 0000

Page mode (0=not supported) 98 4C 0000

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

ABSOLUTE MAXIMUM STRESS RATINGS

Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC

Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 oC to +150oC

V oltage Range

Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.0 V

RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +11.5 V

The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to Vcc +0.5 V

Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA

OPERATING TEMPERATURE AND VOLTAGE

Industrial (I) Grade

Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

VCC Supply Voltages

VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65V to 2.2V

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

DC CHARACTERISTICS

Symbol Description Min Typ Max Remark

Iilk Input Leak ± 1.0uA

Iilk9 A9, OE#, RESET# 35uA A9, OE#,

Input Leak RESET#=11V

Iolk Output Leak ± 1.0uA

Icr1 Read Current(10MHz) 12mA CE#=Vil,

OE#=Vih

Icr2 Read Current(5MHz) 6mA CE#=Vil,

OE#=Vih

Icw Write Current 15mA 25mA CE#=Vil,

OE#=Vih,

WE#=Vil

Isb Standby Current 1uA 5uA Vcc=Vcc max,

other pin disable

Isbr Reset Current 1uA 5uA Vcc=Vccmax,

RESET# enable,

other pin disable

Isbs Sleep Mo de Current 1uA 5uA

Vil Input Low V oltage -0.5V 0.2 x Vcc

Vih Input High V o ltage 0.7xVcc Vcc+0.3V

Vhv V ery High V o ltage fo r hardware 10V 10.5V 11V

Protect/Unprotect/

Auto Select/Temporary

Unprotect

V o l Output Low V o ltage 0.25V Iol=2mA,

Vcc=Vcc min

0.1V Iol=100uA,

Vcc=Vcc min

V oh1 Ouput High V oltage (TTL) 0.85xVcc IOH1=-2mA

V oh2 Ouput High V o ltage (CMOS) Vcc-0.4V IOH2=-100uA

Notes:

When address is no t changed and remain stable f o r Taa + 30nS, the de vice auto matically enter A uto sleep Mo de.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

SWITCHING TEST CIRCUITS

Test Conditio n

Output Lo ad : 1 TTL gate

Output Lo ad Capacitance,CL : 30pF

Rise/Fall Times : 5ns

Input/Output reference levels :Vcc/2

SWITCHING TEST WAVEFORMS

R1=6.2K ohm

R2=2.7K ohm

TESTED DEVICE

DIODES=IN3064

OR EQUIVALENT

Vcc

0.1uF R2 Vcc

Test Points

Vcc

0.0V OUTPUT

INPUT

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

AC CHARACTERISTICS

Symbol Description Min Typ Max Unit

Ta a V alid data output after address 9 0 ns

Tce V alid data o utput after CE# low 9 0 ns

Toe V alid data o utput after OE# low 3 5 ns

Tdf Data o utput flo ating after OE# high 3 0 ns

Toh Data ho ld time after address rising 0 ns

Trc Read perio d time 9 0 ns

Twc Write period time 9 0 ns

Tcwc Command write period time 9 0 ns

Ta s Address setup time 0 ns

Ta h Address hold time 4 5 ns

Tds Data setup time 4 5 ns

Tdh Data hold time 0 ns

Tvcs Vcc setup time 50 us

Tcs CE# Setup time 0 ns

Tch CE# hold time 0 ns

Toe s OE# setup time 0 ns

Toeh Read 0 ns

Toe h OE# ho ld time To ggle & 10 ns

Data# Polling

Tw s WE# setup time 0 ns

Tw h WE# ho ld time 0 ns

Tcep CE# pulse width 4 5 ns

Tceph CE# pulse width high 3 0 ns

Tw p WE# pulse width 4 5 ns

Twp h WE# pulse width high 3 0 ns

Tbusy Pro g ram/Erase activ e time by R Y/BY# 90 ns

Tgh wl Read reco ver time befo re write 0 ns

Tghel Read recover time befo re write 0 ns

T whwh1 Program operation Byte 12 us

T whwh1 Program operation Word 18 us

Twhwh2 Sector erase o peration 1.3 sec

Tbal Secto r add load time 5 0 us

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 1. COMMAND WRITE OPERATION

Addresses

CE#

OE#

WE#

DIN

Tds

Tah

Data

Tdh

Tcs Tch

Tcwc

Twph

Twp

Toes

Tas

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

V A: Valid Address

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

READ/RESET OPERATION

Figure 2. READ TIMING WA VEFORMS

Addresses

CE#

OE#

Taa

WE#

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Voh

Vol

HIGH Z HIGH Z

D ATA V alid

Toe

Toeh Tdf

Tce

Trc

Outputs

Toh

ADD V alid

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 3. RESET# TIMING W AVEFORM

AC CHARACTERISTICS

Item Description Setup Speed Unit

Trp 1 RESET# Pulse Width (During Auto matic Algorithms) MIN 10 us

Trp 2 RESET# Pulse Width (NOT During Auto matic Algorithms) MIN 50 0 ns

Tr h RESET# High Time Befo re Read MIN 20 0 ns

Tr b 1 R Y/BY# Reco very Time (to CE#, OE# go low) M IN 0 ns

Trb 2 R Y/BY# Reco very Time (to WE# go lo w) MIN 5 0 ns

Tready1 RESET# PIN Low (During Auto matic Algorithms) MAX 2 0 us

to Read or Write

Tready2 RESET# PIN Low (NO T During Auto matic MAX 50 0 ns

Algo rithms) to Read or Write

Trh

Trb1

Trp2

Trp1

Tready2

Tready1

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

Trb2

WE#

RESET#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

ERASE/PROGRAM OPERATION

Figure 4. AUTOMA TIC CHIP ERASE TIMING W A VEFORM

Twc

Address

OE#

CE#

55h

2AAh SA

10h

Progress Complete

VA VA

Tas Tah

SA: 555h for chip erase

Tghwl

Tch

Twp

Tds Tdh

Read Status

Last 2 Erase Command Cycle

Tbusy Trb

Tcs Twph

WE#

Data

RY/BY#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 5. AUTOMA TIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO Data=FFh ?

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Data# Polling Algorithm or

Toggle Bit Algorithm

Auto Chip Erase Completed

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 6. A UTOMA TIC SECTOR ERASE TIMING W A VEFORM

Twc

Address

OE#

CE#

55h

2AAh Sector

Address 1

Sector

Address 0

30h

Progress Complete

VA VA

30h

Sector

Address n

Tas

Tah

Tbal

Tghwl

Tch

Twp

Tds Tdh

Twhwh2

Read Status

Last 2 Erase Command Cycle

Tbusy Trb

Tcs Twph

WE#

Data

RY/BY#

30h

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 7. A UTOMATIC SECTOR ERASE ALGORITHM FLO WCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Data# Polling Algorithm or

Toggle Bit Algorithm

Auto Sector Erase Completed

Last Sector

to Erase

YES

Data=FFh

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 8. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

ERASE SUSPEND

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

ERASE RESUME

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 9. AUTOMA TIC PROGRAM TIMING WA VEFORMS

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh1

Last 2 Read Status CycleLast 2 Program Command Cycle

Tbusy Trb

Tcs Twph

WE#

Data

RY/BY#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 10. CE# CONTROLLED WRITE TIMING WA VEFORM

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tcep

Tds Tdh

Twhwh1 or Twhwh2

Tbusy Trb

Tceph

WE#

Data

RY/BY#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 11. A UTOMA TIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Read Again Data:

Program Data?

YES

Auto Program Completed

Data# Polling Algorithm or

Toggle Bit Algorithm

next address

Last Word to be

Programed

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

SECTOR PROTECT/CHIP UNPROTECT

Figure 12. SECTOR PROTECT/CHIP UNPRO TECT WA VEFORM (RESET# Control)

150uS: Sector Protect

15mS: Chip Unprotect

1us

Vhv

Vih

Data

SA, A6

A1, A0

CE#

WE#

OE#

VA VA VA

Status

VA: valid address

40h60h60h

Verification

RESET#

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv

START

Retry count=0

RESET#=Vhv

Wait 1us

Write Sector Address

with [A6,A1,A0]:[0,1,0]

data: 60h

Write Sector Address

with [A6,A1,A0]:[0,1,0]

data: 40h

Read at Sector Address

with [A6,A1,A0]:[0,1,0]

Wait 150us

Reset

PLSCNT=1

Temporary Unprotect Mode

RESET#=Vih

Write RESET CMD

Sector Protect Done

Device fail

Temporary Unprotect Mode

Retry Count +1

First CMD=60h?

Data=01h?

Retry Count=25?

Yes

YesYes

Yes

Protect another

sector?

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 13-2. CHIP UNPRO TECT ALGORITHMS WITH RESET#=Vhv

Write [A6,A1,A0]:[1,1,0]

data: 60h

Write [A6,A1,A0]:[1,1,0]

data: 40h

Read [A6,A1,A0]:[1,1,0]

Wait 15ms

Temporary Unprotect

Write reset CMD

Chip Unprotect Done

Retry Count +1

Device fail

All sectors

protected?

Data=00h?

Retry Count=1000?

Yes

Protect All Sectors

START

Retry count=0

RESET#=Vhv

Wait 1us

Temporary Unprotect

First CMD=60h?

Yes

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 14. SECTOR PROTECT TIMING W A VEFORM (A9, OE# Control)

Notes: Tvlht (V o ltage transitio n time)=4us min.

Twpp1 (Write pulse width fo r sector pro tect)=100ns min, 10us(Typ.)

Twpp2 (Write pulse width fo r chip unpro tected)=100ns min, 12ms(Typ.)

To esp (OE# setup time to WE# activ e)=4us min.

Toe

Data

OE#

WE#

10.5V

1.8V

10.5V

1.8V

CE#

Toesp

Twpp1

Tvlht

TvlhtTvlht

Verify

01H F0H

A17-A12 Sector Address

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 15. SECTOR PRO TECTION ALGORITHM (A9, OE# Control)

START

Write Sector Addr

Retry Count=0

Retry Count+1

Sector Protect

Done

Data=01H?

Yes

OE#=Vhv, A9=Vhv, CE#=Vil

A6=Vil

Activate WE# Pulse

Time Out 150us

WE#=Vih, CE#=OE#=Vil

A9=Vhv

Read at Sector Address

with A1=1

Protect Another

Sector?

Remove Vhv from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 16. TIMING WA VEFORM FOR CHIP UNPROTECTION (A9, OE# Control)

No tes: Tvlht (V o ltage transitio n time)=4us min.

Twpp1 (Write pulse width fo r sector pro tect)=100ns min, 10us(Typ .)

Twpp2 (Write pulse width fo r chip unpro tected)=100ns min, 12ms(T yp.)

To esp (OE# setup time to WE# activ e)=4us min.

Toe

Data

WE#

10.5V

VCC

CE#

Toesp

Twpp2

OE#

10.5V

VCC

Tvlht Tvlht

Verify

00H

Sector Address

A17-A12

F0H

Tvlht

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

START

Protect All Sectors

Retry Count=0

Chip Unprotect

Done

Data=00H?

Yes

OE#=A9=Vhv

CE#=Vil, A6=Vih

Activate WE# Pulse

Time Out 50ms

Sector Protect Verify from

first sector with CE#=OE#=vil,

A9=Vhv, A1=1

All sectors have

been verified?

Remove Vhv from A9

Write Reset Command

Device Failed

PLSCNT=1000?

Retry Count +1

Yes

go to next sector

* Before chip unprotect, all sectors should be protected.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 18. TEMPORAR Y SECTOR UNPROTECT WA VEFORMS

T able 5. TEMPORARY SECTOR UNPROTECT

Parameter Alt Description Condition Speed Unit

Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns

Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us

RESET#

CE#

WE#

RY/BY#

Trpvhh

10.5V

Vhv

0 or 1.8V Vil or Vih

Tvhhwl

Trpvhh

Program or Erase Command Sequence

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 19. TEMPORARY SECTOR UNPROTECT FLOWCHART

Notes:

1. Temporary unprotect all pro tected sectors Vhv=10~11V.

2. After leaving tempo rary unpro tect mode, the pre viously pro tected secto rs are again pro tected.

Start

Apply RESET# pin Vhv Volt

Enter Program or Erase Mode

(1) Remove Vhv Volt from RESET#

(2) RESET# = Vih

Completed Temporary Sector

Unprotected Mode

Mode Operation Completed

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 20. SILICON ID READ TIMING W AVEFORM

Taa

Tce

Taa

Toe

Toh Toh

Tdf

DATA OUT

C2H 70H (TOP boot)

F1H (Bottom boot)

Vhv

Vih

Vil

ADD

CE#

OE#

WE#

DATA OUT

DATA

Q0-Q7

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

WRITE OPERATION STATUS

Figure 21. D A T A# POLLING TIMING W A VEFORMS (DURING AUTOMA TIC ALGORITHMS)

Tdf

Tce

Tch

Toe

Toeh

Toh

CE#

OE#

WE#

Q0-Q6

RY/BY#

Tbusy

Status Data Status Data

Status Data Complement True Valid Data

Taa

Trc

Address VAVA

High Z

Valid DataTrue

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 22. DA T A# POLLING ALGORITHM

Read Q7~Q0 at valid address

(Note 1)

Read Q7~Q0 at valid address

Start

Q7 = Data# ?

Q5 = 1 ?

Q7 = Data# ?

(Note 2)

FAIL Pass

Yes

Notes:

1 . Fo r programming, valid address means pro gram address.

F o r erasing, valid address means erase secto rs address .

2. Q7 sho uld be rechec ked ev en Q5="1" because Q7 ma y change simultaneo usly with Q5.

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 23. TOGGLE BIT TIMING W A VEFORMS (DURING AUTOMA TIC ALGORITHMS)

Tdf

Tce

Tch

Toe

Toeh

Taa

Trc

Toh

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

Tbusy

Valid Status

(first read)

Valid Status

(second read) (stops toggling)

Valid Data

VA VA

Notes:

1. VA : V alid Address

2. CE# must be toggled when toggle bit toggling.

Valid Data

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 24. TOGGLE BIT ALGORITHM

Notes:

1. Read to ggle bit twice to determine whether or no t it is to ggling.

2. Recheck toggle bit because it may stop to ggling as Q5 changes to "1".

Read Q7-Q0 Twice

Q5 = 1?

Read Q7~Q0 Twice

Program/Erase fail

Write Reset CMD Program/Erase Complete

Q6 Toggle ?

(Note1)

(Note1, 2)

YES

Start

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 25. BYTE# TIMING W AVEFORM FOR READ OPERATIONS (BYTE# switching fr om byte mode to wor d

mode)

AC CHARACTERISTICS

WORD/BYTE CONFIGURA TION (BYTE#)

Parameter Description Speed Unit

-90

Telfl/Telfh CE# to BYTE# Switching Low/High MAX 5 ns

Tflqz BYTE# fro m L to Output High-z MAX 30 ns

Tfhq v BYTE# from H to Output Active MI N 90 ns

Tfhqv

Telfh

DOUT

(Q0-Q7) DOUT

(Q0-Q14)

VA DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

Figure 26. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to

byte mode)

Figure 27. BYTE# TIMING W A VEFORM FOR PROGRAM OPERA TIONS

Tas Tah

The last WE# signal (falling edge)

CE#

WE#

BYTE#

Tflqz

Telfl

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

AC timing illustrated in Figure A is reco mmended fo r the supply vo ltages and the co ntro l signals at de vice power-up .

If the timing in the figure is igno red, the device may not o perate correctly.

Figure A. AC Timing at Device P ower-Up

Symbol Parameter Min. Max. Unit

Tvr Vcc Rise Time 20 500000 us/V

Tr Input Signal Rise Time 2 0 us/V

Tf Input Signal Fall Time 20 us/V

Vcc

ADDRESS

CE#

WE#

OE#

DATA

Tvr

Taa

Tr or Tf Tr or Tf

Tce

Vcc(min)

GND

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Voh High Z

Vol

WP#/ACC

Valid

Ouput

Valid

Address

Tvcs

Toe

Tf Tr

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

Parameter Symbol Parameter Description Test Set TYP MAX UNIT

CIN2 Control Pin Capacitance VIN=0 7.5 9 p F

COUT Output Capacitance VOUT=0 8.5 1 2 pF

CIN Input Capacitance VIN=0 6 7.5 pF

TSOP PIN CAPACITANCE

LIMITS

PARAMETER MIN. TYP. MAX. UNITS

Byte Programming Time 1 2 7 2 us

Word Programming Time 18 108 us

Sector Erase Time 1. 3 1 5 sec

Chip Erase Time 9 sec

Chip Programming Time Byte Mode 6. 3 sec

Word Mode 4.8 sec

Erase/Program Cycles 100,000 Cycles

Note : 1. Typical co ndition means 25°C, 1.8V.

2. Maximum conditio n means 85 °C , 1.65V, typical 100K cycles.

MIN. MAX.

Input Voltage difference with GND on OE#, RESET#, A9 -1.0V 11V

Input Voltage difference with GND on all power pins, Address pins, CE# and WE# -1.0V 2xVCC

Input Voltage difference with GND on all I/O pins -1.0V VCC + 1.0V

Vcc Current -100mA +100mA

Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin per testing

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

P ART NO. A CCESS OPERATING ST ANDBY PA CKA GE Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

MX29SL402CBTI-90G 90 12 5 48-Pin TSOP Pb-free

(Normal Type)

MX29SL402CTXBI-90G 90 12 5 48-ball CSP-TFBGA Pb-free

(6x8x1.2mm,

Ball Size:0.3mm)

MX29SL402CBXBI-90G 90 12 5 48-ball CSP-TFBGA Pb-free

(6x8x1.2mm,

Ball Size:0.3mm)

MX29SL402CTXEI-90G 90 12 5 48-ball CSP-LFBGA Pb-free

(6x8x1.3mm,

Ball Size:0.4mm)

MX29SL402CBXEI-90G 90 12 5 48-ball CSP-LFBGA Pb-free

(6x8x1.3mm,

Ball Size:0.4mm)

MX29SL402CTXHI-90G 90 12 5 48-ball CSP-WFBGA Pb-free

(4x6x0.75mm,

Ball Pitch:0.5mm,

Ball Size:0.3mm)

MX29SL402CBXHI-90G 90 12 5 48-ball CSP-WFBGA Pb-free

(4x6x0.75mm,

Ball Pitch:0.5mm,

Ball Size:0.3mm)

MX29SL402CTGBI-90G 90 12 5 48-ball XFLGA Pb-free

(4x6x0.5mm,

Land Pitch:0.5mm,

Land Opening:0.25mm)

MX29SL402CBGBI-90G 90 12 5 48-ball XFLGA Pb-free

(4x6x0.5mm,

Land Pitch:0.5mm,

Land Opening:0.25mm)

ORDERING INFORMATION

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

PART NAME DESCRIPTION

MX 29 SL 90C T T I G

OPTION:

G: Lead-free package

SPEED:

90: 90ns

TEMPERATURE RANGE:

I: Industrial (-40˚ C to 85˚ C)

PACKAGE:

T: TSOP

XB: TFBGA (6x8x1.2mm, 0.8mm ball pitch, 0.3mm ball size)

XE: LFBGA (6x8x1.3mm, 0.8mm ball pitch, 0.4mm ball size)

XH: WFBGA (4x6x0.75mm, 0.5mm ball pitch, 0.3mm ball size)

GB: XFLGA (4x6x0.5mm, 0.5mm land pitch, 0.25mm land opening)

BOOT BLOCK TYPE:

T: Top Boot

B: Bottom Boot

REVISION:

DENSITY & MODE:

402: 4M, x8/x16 Boot Block

TYPE:

SL: 1.8V

DEVICE:

29: Flash

402

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

PACKAGE INFORMATION

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

48-Ball CSP-TFBGA for MX29SL402C TXBI/BXBI

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

48-Ball CSP-LFBGA for MX29SL402C TXEI/BXEI

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

48-Ball CSP-WFBGA for MX29SL402C TXHI/BXHI

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

P/N:PM1362 REV. 1.0, JUN. 13, 2008

MX29SL402C T/B

REVISION HISTORY

Revision Description Page Date

1.0 1. Removed "Preliminary" P1 JUN/13/2008

2. Modified "Typical 100,000 erase/pro gram cycle" P1, 50

MX29SL402C T/B

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