Silicon SP4T Switch, Reflective, 100 MHz to 44 GHz ADRF5046 Data Sheet 1 GND GND GND 16 RF1 18 17 GND 19 ADRF5046 15 RF2 2 14 GND RFC 3 13 GND GND 4 12 GND VSS 5 11 RF3 8 9 10 GND GND 7 GND RF4 6 VDD DRIVER 16764-001 V1 V2 FUNCTIONAL BLOCK DIAGRAM Ultra wideband frequency range: 100 MHz to 44 GHz Reflective design Low insertion loss 1.5 dB to 18 GHz 2.5 dB to 40 GHz 3.0 dB to 44 GHz High isolation 46 dB to 18 GHz 33 dB to 40 GHz 31 dB to 44 GHz High input linearity P0.1dB: 27.5 dBm typical IP3: 50 dBm typical High RF input power handling Through path: 27 dBm Hot switching: 27 dBm No low frequency spurious 0.1 dB RF settling time: 50 ns 20-terminal, 3 mm x 3 mm, RoHS-compliant, LGA package 20 FEATURES Figure 1. APPLICATIONS Industrial scanner Test instrumentation Cellular infrastructure mmWave 5G Military radios, radars, and electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5046 is a reflective, single-pole four-throw (SP4T) switch manufactured in the silicon process. The ADRF5046 operates from 100 MHz to 44 GHz with insertion loss of lower than 3.0 dB and isolation of higher than 31 dB. The device has a radio frequency (RF) input power handling capability of 27 dBm for both the through path and hot switching. The device provides complementary metal-oxide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)compatible controls. The ADRF5046 comes in a 20-terminal, 3 mm x 3 mm, RoHScompliant, land grid array (LGA) package and can operate from -40C to +105C. The ADRF5046 draws a low current of 3 A on the positive supply of +3.3 V, and -110 A on the negative supply of -3.3 V. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5046 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept ............9 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 10 Specifications..................................................................................... 3 Applications Information .............................................................. 11 Absolute Maximum Ratings............................................................ 5 Evaluation Board ........................................................................ 11 Thermal Resistance ...................................................................... 5 Probe Matrix Board ................................................................... 14 Power Derating Curves ................................................................ 5 Outline Dimensions ....................................................................... 15 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 4/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 15 Data Sheet ADRF5046 SPECIFICATIONS Power supply voltage (VDD) = +3.3 V, negative supply voltage (VSS) = -3.3 V, digital control inputs voltage (VCTL) = 0 V or +3.3 V, and case temperature (TCASE) = 25C on a 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1 to RF4 (On) Symbol f ISOLATION Between RFC and RF1 to RF4 (Off) RETURN LOSS RFC and RF1 to RF4 (On) SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time RF Settling Time 0.1 dB 0.05 dB INPUT LINEARITY1 0.1 dB Power Compression Third-Order Intercept Second-Order Intercept VIDEO FEEDTHROUGH2 SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current Low High tRISE, tFALL tON, tOFF P0.1dB IP3 IP2 Test Conditions/Comments Min 100 Typ Max 44,000 Unit MHz 100 MHz to 18 GHz 1.5 dB 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 1.7 2.3 2.5 3.0 dB dB dB dB 100 MHz to 18 GHz 46 dB 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 42 38 33 31 dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 17 18 13 16 12 dB dB dB dB dB 10% to 90% of RF output 50% VCTL to 90% of RF output 3 16 ns ns 50% VCTL to 0.1 dB of final RF output 50% VCTL to 0.05 dB of final RF output 50 60 ns ns f = 200 MHz to 40 GHz Two-tone input power = 14 dBm each tone, f = 200 MHz to 40 GHz, f = 1 MHz Two-tone input power = 14 dBm each tone, f = 10 GHz, f = 1 MHz 27.5 50 dBm dBm 100 dBm 35 mV p-p 3 -110 A A VDD, VSS pins IDD ISS V1, V2 pins VINL VINH 0 1.2 IINL IINH 0.8 3.3 <1 35 Rev. 0 | Page 3 of 15 V V A A ADRF5046 Parameter RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Inputs Voltage RFx Input Power3 Through Path Data Sheet Symbol VDD VSS VCTL PIN Hot Switching Case Temperature Test Conditions/Comments Min 3.15 -3.45 0 f = 200 MHz to 40 GHz, TCASE = 85C4 RF signal is applied to RFC or through connected RF throw port RF signal is present at RFC while switching between RF throw port TCASE -40 1 Typ Max Unit 3.45 -3.15 VDD V V V 27 dBm 27 dBm +105 C For input linearity performance over frequency, see Figure 19 to Figure 22. Video feedthrough is the spurious dc transient measured at the RF ports in a 50 test setup, without an RF signal present while switching the control voltage. 3 For power derating over frequency, see Figure 2 and Figure 3. 4 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 2 Rev. 0 | Page 4 of 15 Data Sheet ADRF5046 ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. POWER DERATING CURVES 2 Table 2. 2 27.5 dBm 27.5 dBm POWER DERATING (dB) -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD +0.3 V -2 -4 -6 -8 -10 135C -65C to +150C 260C -14 10k 100k 10M 100M 1G 100G 10G FREQUENCY (Hz) Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 2 500 V 2000 V 0 For power derating over frequency, see Figure 2 and Figure 3. For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. -2 -4 -6 -8 -10 -12 -14 36 37 38 Only one absolute maximum rating can be applied at any one time. 39 40 41 42 43 44 45 FREQUENCY (GHz) 46 47 48 49 50 Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. ESD CAUTION JC is the junction to case bottom (channel to package bottom) thermal resistance. Table 3. Thermal Resistance Package Type CC-20-6, Through Path 1M 16764-002 -12 16764-003 1 0 Rating POWER DERATING (dB) Parameter Supply Voltage Positive Negative Digital Control Inputs Voltage RFx Input Power (f1 = 200 MHz to 40 GHz, TCASE = 85C2) Through Path Hot Switching Temperature Junction, TJ Storage Range Reflow Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) RFx Pins Supply and Digital Control Pins JC 240 Unit C/W Rev. 0 | Page 5 of 15 ADRF5046 Data Sheet GND GND 19 18 17 16 V1 1 15 RF2 GND 2 14 GND 6 7 8 9 10 GND 5 RF4 VSS TOP VIEW (Not to Scale) GND 4 VDD 3 GND RFC GND ADRF5046 13 GND 12 GND 11 RF3 NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 16764-004 GND 20 RF1 V2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2, 4, 7, 9, 10, 12 to 14, 16, 17, 19 3 Mnemonic V1 GND Description Control Input 1. See Figure 6 for the interface schematic. Ground. These pins must be connected to the RF and dc ground of the PCB. RFC 5 6 8 VSS VDD RF4 11 RF3 15 RF2 18 RF1 20 V2 EPAD RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. Negative Supply Voltage. Positive Supply Voltage. RF Throw Port 4. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. RF Throw Port 3. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. RF Throw Port 2. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. RF Throw Port 1. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. Control Input 2. See Figure 6 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF and dc ground. V1, V2 16764-006 RFC, RF1, RF2, RF3, RF4 16764-005 INTERFACE SCHEMATICS Figure 6. Control Input Pins Interface Schematic Figure 5. RF Pins (RFC and RF1 to RF4) Interface Schematic Rev. 0 | Page 6 of 15 Data Sheet ADRF5046 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION 0 -0.5 -0.5 -1.0 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 0 5 -3.5 10 15 20 25 30 35 40 45 50 -5.0 0 -10 -10 -15 -15 RETURN LOSS (dB) -5 -5 -20 -25 -30 -35 30 35 40 45 50 FREQUENCY (GHz) -50 16764-008 25 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) Figure 11. Return Loss for RFx On vs. Frequency 0 -10 -10 -20 -20 -30 -30 ISOLATION (dB) 0 -40 -50 -60 -70 -40 -50 -60 -70 -80 -80 RF2 RF3 RF4 -90 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) RF1 RF3 RF4 -90 50 16764-009 ISOLATION (dB) 30 RF1 RF2 RF3 RF4 Figure 8. Return Loss for RFC vs. Frequency, RFC to RF1 On -100 25 -35 -45 20 20 -30 -45 15 15 -25 -40 10 10 -20 -40 5 5 FREQUENCY (GHz) 0 0 0 = +105C = +85C = +25C = - 40C Figure 10. Insertion Loss for RF1 On vs. Frequency over Various Temperatures Figure 7. Insertion Loss for RFx On vs. Frequency -50 TCASE TCASE TCASE TCASE -4.5 FREQUENCY (GHz) RETURN LOSS (dB) -3.0 -100 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) Figure 12. Isolation for RFC vs. Frequency, RFC to RF2 On Figure 9. Isolation for RFC vs. Frequency, RFC to RF1 On Rev. 0 | Page 7 of 15 50 16764-012 -5.0 -2.5 -4.0 RF1 RF2 RF3 RF4 -4.5 -2.0 16764-011 -4.0 -1.5 16764-010 INSERTION LOSS (dB) 0 16764-007 INSERTION LOSS (dB) VDD = +3.3 V, VSS = -3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25C on a 50 system, unless otherwise noted. Insertion loss and return loss are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. However, isolation is measured on the evaluation board. See the Applications Information section for details on the evaluation and probe matrix boards. ADRF5046 Data Sheet 0 RF1 RF2 RF4 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -100 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) 16764-013 -90 -100 0 -10 -10 -20 -20 -30 -30 ISOLATION (dB) 0 -40 -50 -60 10 15 20 25 30 35 40 45 50 RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO RF2 RF3 RF4 RF3 RF4 RF4 -40 -50 -60 -70 RF1 TO RF2 RF1 TO RF3 RF1 TO RF4 RF2 TO RF3 RF2 TO RF4 RF3 TO RF4 -90 0 5 10 15 20 25 30 35 40 45 -80 -90 50 FREQUENCY (GHz) Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On 0 RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 -20 -100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) 16764-017 -80 16764-014 Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF2 On 0 RF2 RF3 RF4 RF3 RF4 RF4 RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 -20 -30 RF2 RF3 RF4 RF3 RF4 RF4 ISOLATION (dB) -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -100 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 16764-015 -90 -100 Figure 15. Channel to Channel Isolation vs. Frequency, RFC to RF3 On 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 16764-018 ISOLATION (dB) 5 Figure 16. Isolation for RFC vs. Frequency, RFC to RF4 On 0 -70 ISOLATION (dB) 0 FREQUENCY (GHz) Figure 13. Isolation for RFC vs. Frequency, RFC to RF3 On -100 RF1 RF2 RF3 -10 ISOLATION (dB) ISOLATION (dB) -10 16764-016 0 Figure 18. Channel to Channel Isolation vs. Frequency, RFC to RF4 On Rev. 0 | Page 8 of 15 Data Sheet ADRF5046 INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 30 28 28 INPUT POWER COMPRESSION (dBm) 30 26 24 22 20 18 16 14 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 22 20 18 16 14 10 10k 1M 10M 100M 1G Figure 21. Input Power Compression vs. Frequency, Low Frequency Detail 60 55 55 50 50 INPUT IP3 (dBm) 60 45 40 35 45 40 35 30 30 0 TCASE TCASE TCASE TCASE = +105C = +85C = +25C = - 40C 5 10 15 TCASE TCASE TCASE TCASE 25 20 25 30 35 40 FREQUENCY (GHz) 16764-020 25 20 100k FREQUENCY (Hz) Figure 19. Input Power Compression vs. Frequency INPUT IP3 (dBm) 24 12 P0.1dB P1dB 0 26 20 10k 100k 1M 10M = +105C = +85C = +25C = -40C 100M 1G FREQUENCY (Hz) Figure 22. Input IP3 vs. Frequency over Various Temperatures, Low Frequency Detail Figure 20. Input IP3 vs. Frequency over Various Temperatures Rev. 0 | Page 9 of 15 16764-022 10 P0.1dB P1dB 16764-019 12 16764-021 INPUT POWER COMPRESSION (dBm) VDD = +3.3 V, VSS = -3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25C on a 50 system, unless otherwise noted. Measured on the evaluation board. ADRF5046 Data Sheet THEORY OF OPERATION The ADRF5046 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. selected RF throw port. The isolation paths provide high loss between the insertion loss path and the unselected RF throw ports that are reflective. All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The RF ports are internally matched to 50 . Therefore, external matching networks are not required. 1. 2. The ideal power-up sequence is as follows: 3. The ADRF5046 integrates a driver to perform logic functions internally and to provide the user with the advantage of a simplified CMOS/LVTTL-compatible control interface. The driver features two digital control input pins (V1 and V2) that control the state of the RFx paths. The logic level applied to the V1 and V2 pins determines which RFx port is in the insertion loss state while the other three paths are in the isolation state (see Table 5). The insertion loss path conducts the RF signal between the selected RF throw port and the RF common port. The switch design is bidirectional with equal power handling capabilities. The RF input signal can be applied to the RFC port or the 4. Connect GND. Power up VDD and VSS. Power up VSS after VDD to avoid current transients on VDD during ramp up. Apply digital control inputs V1 and V2. Applying these digital control inputs before applying the VDD supply inadvertently forwards bias and damages the internal ESD protection structures. To avoid this damage, use a series 1 k resistor to limit the current flowing into the control pin. Use pull-up or pull-down resistors if the controller output is in a high impedance state after VDD is powered up and the control pins are not driven to a valid logic state. Apply an RF input signal to either the RFC port or the RF throw port. The ideal power-down sequence is the reverse order of the power-up sequence. Table 5. Control Voltage Truth Table Digital Control Inputs V1 V2 Low Low High Low Low High High High RF1 to RFC Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) RF2 to RFC Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Rev. 0 | Page 10 of 15 RFx Paths RF3 to RFC Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) RF4 to RFC Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Data Sheet ADRF5046 APPLICATIONS INFORMATION EVALUATION BOARD The ADRF5046-EVALZ is a 4-layer evaluation board. The outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. Figure 23 shows the evaluation board stackup. 1.5oz Cu (2.2mil) T = 2.2mil RO4003 16764-025 1.5oz Cu (2.2mil) H = 8mil Figure 25. RF Transmission Lines 0.5oz Cu (0.7mil) Two power supply ports are connected to the VDD and VSS test points, control voltages are connected to the V1 and V2 test points, and the ground reference is connected to the GND test point. On the supply traces, a 100 pF bypass capacitor is used to filter the high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors. 0.5oz Cu (0.7mil) 1.5oz Cu (2.2mil) 16764-023 TOTAL THICKNESS -62mil 8mil G = 7mil 7mil 1.5oz Cu (2.2mil) 7mil 14mil W = 14mil 8mil On the control traces, there are provisions for the resistor capacitor (RC) filter to eliminate dc-coupled noise, if needed, by the application. The resistor can also improve the isolation between the RF and the control signal. Figure 23. Evaluation Board Cross Sectional View All RF and dc traces are routed on the top copper layer, whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 8 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The total board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. Figure 24 shows the top view of the evaluation board. The RF input and output ports (RFC, RF1 to RF4) are connected through 50 transmission lines to the 2.4 mm RF launchers. These high frequency RF launchers are by contact and not soldered onto the board. A thru calibration line (THRU CAL) connects the unpopulated RF launchers. This transmission line is used to calibrate out the board loss effects from the ADRF5046-EVALZ evaluation board measurements to determine the device performance at the packaged pins. Figure 26 shows the typical board loss at room temperature, the embedded insertion loss, and the de-embedded insertion loss for the ADRF5046. 0 The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with trace width of 14 mil and ground clearance of 7 mil to have a characteristic impedance of 50 . The RF transmission lines are extended by 8 mil from package edge to the tapered line used for RF pin transition as shown in Figure 25. For optimal RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. -2 -3 -4 -5 -6 THRU LOSS EMBEDDED INSERTION LOSS DEEMBEDDED INSERTION LOSS -7 -8 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 45 50 16764-026 Figure 24. Evaluation Board Layout (Top View) INSERTION LOSS (dB) 16764-024 -1 Figure 26. Insertion Loss vs. Frequency Figure 27 shows the ADRF5046-EVALZ assembly drawing with component placement and Figure 28 shows the schematic. Rev. 0 | Page 11 of 15 Data Sheet 16764-027 ADRF5046 Figure 27. Evaluation Board Assembly Drawing Rev. 0 | Page 12 of 15 Data Sheet ADRF5046 VSS C1 10nF C3 DNI AGND AGND C2 10nF C4 DNI AGND AGND C7 DNI C8 DNI AGND AGND C5 DNI C6 DNI AGND AGND VDD R1 V1 0 R2 V2 0 GND RF2 AGND 1 2345 AGND RF1 1 2345 GND RF1 GND V2 GND PAD AGND V1 ADRF5046 RFC GND 1 2345 AGND THRU1_CAL 1 THRU2 2345 AGND GND VDD GND RF3 VSS RF4 AGND THRU1 GND GND 2345 GND RFC RF2 GND GND 1 U1 AGND RF4 1 2345 AGND RF3 1 16764-028 2345 AGND Figure 28. Evaluation Board Schematic Table 6. Evaluation Board Components Component C1, C2 C3, C4, C5, C7 C6, C8 RFC, RF1 to RF4 THRU1, THRU2 R1, R2 VDD, VSS, V1, V2, GND U1 PCB Default Value 10 nF Not applicable Not applicable Not applicable Not applicable 0 Not applicable ADRF5046 08-044567D Description Capacitors, C0402 package Capacitors, C0402 package, do not install (DNI) Capacitors, C0402 package, DNI 2.4 mm end launch connectors (Southwest Microwave 1492-04A-5) 2.4 mm end launch connectors, DNI Resistors, 0402 package Through-hole mount test points SP4T switch, Analog Devices(R), Inc. Evaluation PCB, Analog Devices, Inc. Rev. 0 | Page 13 of 15 ADRF5046 Data Sheet PROBE MATRIX BOARD The probe matrix board uses the same stackup as the evaluation board, but a different layout designed to perform measurements using GSG probes at close proximity to the RF pins. Probing eliminates the mismatch reflections caused by connectors, cables, and board layout. Therefore, the probe matrix board provides more accurate measurement of the device performance than the evaluation board. Figure 29 shows the top view of the probe matrix board layout. 16764-029 The probe matrix board includes a through reflect line (TRL) calibration kit allowing board loss de-embedding. The actual board duplicates the same layout in matrix form to assemble multiple devices at one time. All s parameters were measured on this board. Figure 29. Probe Matrix Board Layout (Top View) Rev. 0 | Page 14 of 15 ADRF5046 Data Sheet OUTLINE DIMENSIONS 0.250 0.200 0.150 0.325 0.275 0.225 16 CHAMFERED PIN 1 (0.25 x 45) 1 1.60 REF SQ 0.40 BSC SIDE VIEW 11 5 6 10 BOTTOM VIEW 0.530 REF 0.333 0.330 0.300 PKG-005368 1.60 1.50 SQ 1.40 EXPOSED PAD TOP VIEW 0.960 MAX 0.125 REF 20 15 FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET 01-19-2018-A PIN 1 CORNER AREA 3.10 3.00 SQ 2.90 Figure 30. 20-Terminal Land Grid Array [LGA] (CC-20-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5046BCCZN ADRF5046BCCZN-R7 ADRF5046-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 20-Terminal Land Grid Array [LGA] 20-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16764-0-4/19(0) Rev. 0 | Page 15 of 15 Package Option CC-20-6 CC-20-6 Marking Code 046 046