Silicon SP4T Switch,
Reflective, 100 MHz to 44 GHz
Data Sheet ADRF5046
Rev. 0 Document Feedback
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Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved.
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FEATURES
Ultra wideband frequency range: 100 MHz to 44 GHz
Reflective design
Low insertion loss
1.5 dB to 18 GHz
2.5 dB to 40 GHz
3.0 dB to 44 GHz
High isolation
46 dB to 18 GHz
33 dB to 40 GHz
31 dB to 44 GHz
High input linearity
P0.1dB: 27.5 dBm typical
IP3: 50 dBm typical
High RF input power handling
Through path: 27 dBm
Hot switching: 27 dBm
No low frequency spurious
0.1 dB RF settling time: 50 ns
20-terminal, 3 mm × 3 mm, RoHS-compliant, LGA package
APPLICATIONS
Industrial scanner
Test instrumentation
Cellular infrastructure mmWave 5G
Military radios, radars, and electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
FUNCTIONAL BLOCK DIAGRAM
GND
RF1
GND
V2
GND
GND
VDD
RF4
GND
GND
GND
V1
RFC
GND
VSS
GND
GND
RF2
ADRF5046
GND
RF3
DRIVER
16764-001
5
1
2
3
4
11
15
14
13
12
16
20
19
18
17
10
6
7
8
9
Figure 1.
GENERAL DESCRIPTION
The ADRF5046 is a reflective, single-pole four-throw (SP4T)
switch manufactured in the silicon process.
The ADRF5046 operates from 100 MHz to 44 GHz with
insertion loss of lower than 3.0 dB and isolation of higher than
31 dB. The device has a radio frequency (RF) input power
handling capability of 27 dBm for both the through path and
hot switching.
The ADRF5046 draws a low current of 3 µA on the positive
supply of +3.3 V, and −110 µA on the negative supply of −3.3 V.
The device provides complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor-transistor logic (LVTTL)-
compatible controls.
The ADRF5046 comes in a 20-terminal, 3 mm × 3 mm, RoHS-
compliant, land grid array (LGA) package and can operate from
−40°C to +105°C.
ADRF5046 Data Sheet
Rev. 0 | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Power Derating Curves ................................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input Power Compression and Third-Order Intercept ............9
Theory of Operation ...................................................................... 10
Applications Information .............................................................. 11
Evaluation Board ........................................................................ 11
Probe Matrix Board ................................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/2019—Revision 0: Initial Version
Data Sheet ADRF5046
Rev. 0 | Page 3 of 15
SPECIFICATIONS
Power supply voltage (VDD) = +3.3 V, negative supply voltage (VSS) = −3.3 V, digital control inputs voltage (VCTL) = 0 V or +3.3 V, and case
temperature (TCASE) = 25°C on a 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 100 44,000 MHz
INSERTION LOSS
Between RFC and RF1 to RF4
(On)
100 MHz to 18 GHz 1.5 dB
18 GHz to 26 GHz 1.7 dB
26 GHz to 35 GHz 2.3 dB
35 GHz to 40 GHz 2.5 dB
40 GHz to 44 GHz 3.0 dB
ISOLATION
Between RFC and RF1 to RF4
(Off)
100 MHz to 18 GHz 46 dB
18 GHz to 26 GHz 42 dB
26 GHz to 35 GHz 38 dB
35 GHz to 40 GHz 33 dB
40 GHz to 44 GHz 31 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 100 MHz to 18 GHz 17 dB
18 GHz to 26 GHz 18 dB
26 GHz to 35 GHz 13 dB
35 GHz to 40 GHz 16 dB
40 GHz to 44 GHz 12 dB
SWITCHING CHARACTERISTICS
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 3 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 16 ns
RF Settling Time
0.1 dB 50% VCTL to 0.1 dB of final RF output 50 ns
0.05 dB 50% VCTL to 0.05 dB of final RF output 60 ns
INPUT LINEARITY1
0.1 dB Power Compression P0.1dB f = 200 MHz to 40 GHz 27.5 dBm
Third-Order Intercept IP3 Two-tone input power = 14 dBm each tone,
f = 200 MHz to 40 GHz, Δf = 1 MHz
50 dBm
Second-Order Intercept IP2 Two-tone input power = 14 dBm each tone,
f = 10 GHz, Δf = 1 MHz
100 dBm
VIDEO FEEDTHROUGH2 35 mV p-p
SUPPLY CURRENT VDD, VSS pins
Positive IDD 3 μA
Negative ISS −110 μA
DIGITAL CONTROL INPUTS V1, V2 pins
Voltage
Low VINL 0 0.8 V
High VINH 1.2 3.3 V
Current
Low IINL <1 μA
High IINH 35 μA
ADRF5046 Data Sheet
Rev. 0 | Page 4 of 15
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Inputs Voltage VCTL 0 VDD V
RFx Input Power3 P
IN f = 200 MHz to 40 GHz, TCASE = 85°C4
Through Path RF signal is applied to RFC or through
connected RF throw port
27 dBm
Hot Switching RF signal is present at RFC while switching
between RF throw port
27 dBm
Case Temperature TCASE −40 +105 °C
1 For input linearity performance over frequency, see Figure 19 to Figure 22.
2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage.
3 For power derating over frequency, see Figure 2 and Figure 3.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Data Sheet ADRF5046
Rev. 0 | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Supply Voltage
Positive −0.3 V to +3.6 V
Negative −3.6 V to +0.3 V
Digital Control Inputs Voltage −0.3 V to VDD +0.3 V
RFx Input Power (f1 = 200 MHz to 40 GHz,
TCASE = 85°C2)
Through Path 27.5 dBm
Hot Switching 27.5 dBm
Temperature
Junction, TJ 135°C
Storage Range −65°C to +150°C
Reflow 260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFx Pins 500 V
Supply and Digital Control Pins 2000 V
1 For power derating over frequency, see Figure 2 and Figure 3.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
CC-20-6, Through Path 240 °C/W
POWER DERATING CURVES
2
–14
10k 100G
POWER DERATING (dB)
FREQUENCY (Hz)
–12
–10
–8
–6
–4
–2
0
100k 1M 10M 100M 1G 10G
16764-002
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
36 50
FREQUENCY (GHz)
2
–14
POWER DERATING (dB)
–12
–10
–8
–6
–4
–2
0
37 38 39 40 41 43 45 47 4942 44 46 48
16764-003
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
ESD CAUTION
ADRF5046 Data Sheet
Rev. 0 | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GN
D
RF1
GN
D
V2
GND
GND
VDD
RF4
GND
GND
GND
V1
RFC
GND
VSS
GND
GND
RF2
GND
RF3
1
2
3
4
5
678910
11
12
13
14
15
1617181920
ADRF5046
TOP VIEW
(Not to Scale)
16764-004
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF AND DC GROUND.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 V1 Control Input 1. See Figure 6 for the interface schematic.
2, 4, 7, 9, 10, 12 to
14, 16, 17, 19
GND Ground. These pins must be connected to the RF and dc ground of the PCB.
3 RFC
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
5 VSS Negative Supply Voltage.
6 VDD Positive Supply Voltage.
8 RF4
RF Throw Port 4. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
11 RF3
RF Throw Port 3. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
15 RF2
RF Throw Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
18 RF1
RF Throw Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc.
20 V2 Control Input 2. See Figure 6 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
16764-005
Figure 5. RF Pins (RFC and RF1 to RF4) Interface Schematic
V1, V2
16764-006
Figure 6. Control Input Pins Interface Schematic
Data Sheet ADRF5046
Rev. 0 | Page 7 of 15
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = +3.3 V, VSS = −3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Insertion loss and return loss are
measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. However, isolation is measured on the
evaluation board. See the Applications Information section for details on the evaluation and probe matrix boards.
0
–5.0
050
INSERTION LOSS (dB)
FREQUENCY (GHz)
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
5 1015202530354045
RF1
RF2
RF3
RF4
16764-007
Figure 7. Insertion Loss for RFx On vs. Frequency
0
–50
050
RETURN LOSS (dB)
FREQUENCY (GHz)
–45
–40
–35
–30
–25
–20
–15
–10
–5
5 1015202530354045
16764-008
Figure 8. Return Loss for RFC vs. Frequency, RFC to RF1 On
0
–100
ISOLATION (dB)
050
FREQUENCY (GHz)
5 1015202530354045
RF2
RF3
RF4
–90
–80
–70
–60
–50
–40
–30
–20
–10
16764-009
Figure 9. Isolation for RFC vs. Frequency, RFC to RF1 On
0
–5.0
050
INSERTION LOSS (dB)
FREQUENCY (GHz)
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
5 1015202530354045
T
CASE
= +105°C
T
CASE
=+85°C
T
CASE
= +25°C
T
CASE
=–40°C
16764-010
Figure 10. Insertion Loss for RF1 On vs. Frequency over Various Temperatures
0
–50
050
RETURN LOSS (dB)
FREQUENCY (GHz)
–45
–40
–35
–30
–25
–20
–15
–10
–5
5 1015202530354045
RF1
RF2
RF3
RF4
16764-011
Figure 11. Return Loss for RFx On vs. Frequency
0
–100
ISOLATION (dB)
050
FREQUENCY (GHz)
5 1015202530354045
RF1
RF3
RF4
–90
–80
–70
–60
–50
–40
–30
–20
–10
16764-012
Figure 12. Isolation for RFC vs. Frequency, RFC to RF2 On
ADRF5046 Data Sheet
Rev. 0 | Page 8 of 15
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISO
L
A
TION (dB)
FREQUENCY (GHz)
RF1
RF2
RF4
16764-013
Figure 13. Isolation for RFC vs. Frequency, RFC to RF3 On
16764-014
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISOL
A
TION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On
16764-015
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISOL
A
TION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
Figure 15. Channel to Channel Isolation vs. Frequency, RFC to RF3 On
16764-016
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISOL
A
TION (dB)
FREQUENCY (GHz)
RF1
RF2
RF3
Figure 16. Isolation for RFC vs. Frequency, RFC to RF4 On
16764-017
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISOL
A
TION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF2 On
16764-018
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50
ISOL
A
TION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
Figure 18. Channel to Channel Isolation vs. Frequency, RFC to RF4 On
Data Sheet ADRF5046
Rev. 0 | Page 9 of 15
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = +3.3 V, VSS = −3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation board.
16764-021
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20 25 30 35 40
INPUT POWER COMPRESSION (dBm)
FREQUENCY (GHz)
P0.1dB
P1dB
Figure 19. Input Power Compression vs. Frequency
60
20
040
INPUT IP3 (dBm)
FREQUENCY (GHz)
25
30
35
40
45
50
55
5 101520253035
TCASE = +105°C
TCASE = +85°C
TCASE = +25°C
TCASE = –40°C
16764-020
Figure 20. Input IP3 vs. Frequency over Various Temperatures
16764-019
10
12
14
16
18
20
22
24
26
28
30
10k 100k 1M 10M 100M 1G
INPUT POWER COMPRESSION (dBm)
FREQUENCY (Hz)
P0.1dB
P1dB
Figure 21. Input Power Compression vs. Frequency, Low Frequency Detail
60
20
INPUT IP3 (dBm)
25
30
35
40
45
50
55
TCASE = +105°C
TCASE = +85°C
TCASE = +25°C
TCASE = –40°C
10k 1G
FREQUENCY (Hz)
100k 1M 10M 100M
16764-022
Figure 22. Input IP3 vs. Frequency over Various Temperatures,
Low Frequency Detail
ADRF5046 Data Sheet
Rev. 0 | Page 10 of 15
THEORY OF OPERATION
The ADRF5046 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V. The RF ports are internally matched to
50 . Therefore, external matching networks are not required.
The ADRF5046 integrates a driver to perform logic functions
internally and to provide the user with the advantage of a simplified
CMOS/LVTTL-compatible control interface. The driver features
two digital control input pins (V1 and V2) that control the state
of the RFx paths. The logic level applied to the V1 and V2 pins
determines which RFx port is in the insertion loss state while
the other three paths are in the isolation state (see Table 5).
The insertion loss path conducts the RF signal between the
selected RF throw port and the RF common port. The switch
design is bidirectional with equal power handling capabilities.
The RF input signal can be applied to the RFC port or the
selected RF throw port. The isolation paths provide high loss
between the insertion loss path and the unselected RF throw
ports that are reflective.
The ideal power-up sequence is as follows:
1. Connect GND.
2. Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp up.
3. Apply digital control inputs V1 and V2. Applying these
digital control inputs before applying the VDD supply
inadvertently forwards bias and damages the internal ESD
protection structures. To avoid this damage, use a series 1
kΩ resistor to limit the current flowing into the control
pin. Use pull-up or pull-down resistors if the controller
output is in a high impedance state after VDD is powered
up and the control pins are not driven to a valid logic state.
4. Apply an RF input signal to either the RFC port or the RF
throw port.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 5. Control Voltage Truth Table
Digital Control Inputs RFx Paths
V1 V2 RF1 to RFC RF2 to RFC RF3 to RFC RF4 to RFC
Low Low Insertion loss (on) Isolation (off) Isolation (off) Isolation (off)
High Low Isolation (off) Insertion loss (on) Isolation (off) Isolation (off)
Low High Isolation (off) Isolation (off) Insertion loss (on) Isolation (off)
High High Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet ADRF5046
Rev. 0 | Page 11 of 15
APPLICATIONS INFORMATION
EVALUATION BOARD
The ADRF5046-EVALZ is a 4-layer evaluation board. The outer
copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil)
and are separated by dielectric materials. Figure 23 shows the
evaluation board stackup.
0.5oz Cu (0.7mil)
RO4003
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil)
W = 14mil G = 7mil
T = 2.2mil
H = 8mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
TOTAL THICKNESS
–62mil
16764-023
Figure 23. Evaluation Board Cross Sectional View
All RF and dc traces are routed on the top copper layer, whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 8 mil Rogers RO4003, offering optimal high
frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The total board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges. Figure 24 shows the top view of
the evaluation board.
16764-024
Figure 24. Evaluation Board Layout (Top View)
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with trace width of 14 mil and
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. The RF transmission lines are extended by 8 mil from
package edge to the tapered line used for RF pin transition as
shown in Figure 25. For optimal RF and thermal grounding, as
many plated through vias as possible are arranged around
transmission lines and under the exposed pad of the package.
16764-025
8mil
7mil
8mil
7mil
14mil
Figure 25. RF Transmission Lines
Two power supply ports are connected to the VDD and VSS test
points, control voltages are connected to the V1 and V2 test points,
and the ground reference is connected to the GND test point.
On the supply traces, a 100 pF bypass capacitor is used to filter
the high frequency noise. Additionally, unpopulated components
positions are available for applying extra bypass capacitors.
On the control traces, there are provisions for the resistor
capacitor (RC) filter to eliminate dc-coupled noise, if needed, by
the application. The resistor can also improve the isolation
between the RF and the control signal.
The RF input and output ports (RFC, RF1 to RF4) are
connected through 50 transmission lines to the 2.4 mm RF
launchers. These high frequency RF launchers are by contact
and not soldered onto the board.
A thru calibration line (THRU CAL) connects the unpopulated
RF launchers. This transmission line is used to calibrate out the
board loss effects from the ADRF5046-EVALZ evaluation board
measurements to determine the device performance at the
packaged pins. Figure 26 shows the typical board loss at room
temperature, the embedded insertion loss, and the de-embedded
insertion loss for the ADRF5046.
0
–8
050
INSERTION LOSS (dB)
FREQUENCY (GHz)
–7
–6
–5
–4
–3
–2
–1
5 1015202530354045
THRU LOSS
EMBEDDED INSERTION LOSS
DEEMBEDDED INSERTION LOSS
16764-026
Figure 26. Insertion Loss vs. Frequency
Figure 27 shows the ADRF5046-EVALZ assembly drawing with
component placement and Figure 28 shows the schematic.
Data Sheet ADRF5046
Rev. 0 | Page 13 of 15
GND
RF1
GND
V2
PAD
GND
GND
VDD
RF4
GND
GND
GND
V1
RFC
GND
VSS
GND
GND
RF2
U1
GND
RF3
ADRF5046
1
RF1
AGND
2345
1
RFC
AGND
2345
1
THRU1 THRU1_CAL
AGND
AGND
2345
1
THRU2
AGND
2345
1
RF3
AGND
2345
1
RF4
AGND
2345
1
RF2
AGND
2345
R2
0ΩC5
DNI
C6
DNI
V2
R1
0ΩC7
DNI
C8
DNI
V1
C2
10nF
C4
DNI
VDD
C1
10nF
C3
DNI
V
SS
GND
AGND
AGNDAGND
AGNDAGND
AGNDAGND
AGNDAGND
16764-028
Figure 28. Evaluation Board Schematic
Table 6. Evaluation Board Components
Component Default Value Description
C1, C2 10 nF Capacitors, C0402 package
C3, C4, C5, C7 Not applicable Capacitors, C0402 package, do not install (DNI)
C6, C8 Not applicable Capacitors, C0402 package, DNI
RFC, RF1 to RF4 Not applicable 2.4 mm end launch connectors (Southwest Microwave 1492-04A-5)
THRU1, THRU2 Not applicable 2.4 mm end launch connectors, DNI
R1, R2 0 Ω Resistors, 0402 package
VDD, VSS, V1, V2, GND Not applicable Through-hole mount test points
U1 ADRF5046 SP4T switch, Analog Devices®, Inc.
PCB 08-044567D Evaluation PCB, Analog Devices, Inc.
ADRF5046 Data Sheet
Rev. 0 | Page 14 of 15
PROBE MATRIX BOARD
The probe matrix board uses the same stackup as the evaluation
board, but a different layout designed to perform measurements
using GSG probes at close proximity to the RF pins. Probing
eliminates the mismatch reflections caused by connectors,
cables, and board layout. Therefore, the probe matrix board
provides more accurate measurement of the device performance
than the evaluation board. Figure 29 shows the top view of the
probe matrix board layout.
The probe matrix board includes a through reflect line (TRL)
calibration kit allowing board loss de-embedding. The actual
board duplicates the same layout in matrix form to assemble
multiple devices at one time. All s parameters were measured
on this board.
16764-029
Figure 29. Probe Matrix Board Layout (Top View)
ADRF5046 Data Sheet
Rev. 0 | Page 15 of 15
OUTLINE DIMENSIONS
01-19-2018-A
PKG-005368
3.10
3.00 SQ
2.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
5
6
10
11
15
16 20
1.60
1.50 SQ
1.40
0.40
BSC
0.125
REF
1.60 REF
SQ
0.325
0.275
0.225
0.250
0.200
0.150
0.333
0.330
0.300
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
EXPOSED
PAD
0.530 REF
0.960 MAX
CHAMFERED
PIN 1 (0.25 × 45°)
PIN 1
CORNER AREA
Figure 30. 20-Terminal Land Grid Array [LGA]
(CC-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADRF5046BCCZN −40°C to +105°C 20-Terminal Land Grid Array [LGA] CC-20-6 046
ADRF5046BCCZN-R7 −40°C to +105°C 20-Terminal Land Grid Array [LGA] CC-20-6 046
ADRF5046-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16764-0-4/19(0)
