LM4845
LM4845 Output Capacitor-less Audio Subsystem with Programmable National
3D
Literature Number: SNAS255K
LM4845
Output Capacitor-less Audio Subsystem with
Programmable National 3D
General Description
The LM4845 is an audio power amplifier capable of deliver-
ing 500mW of continuous average power into a mono 8Ω
bridged-tied load (BTL) with 1% THD+N, 25mW per channel
of continuous average power into stereo 32Ωsingle-ended
(SE) loads with 1% THD+N, or an output capacitor-less
(OCL) configuration with identical specification as the SE
configuration, from a 3.3V power supply.
The LM4845 features a 32-step digital volume control and
eight distinct output modes. The digital volume control, 3D
enhancement, and output modes (mono/SE/OCL) are pro-
grammed through a two-wire I
2
C or a three-wire SPI com-
patible interface that allows flexibility in routing and mixing
audio channels. The LM4845 has three input channels: one
pair for a two-channel stereo signal and the third for a
single-channel mono input.
The LM4845 is designed for cellular phone, PDA, and other
portable handheld applications. It delivers high quality output
power from a surface-mount package and requires only
seven external components in the OCL mode (two additional
components in SE mode).
Key Specifications
jTHD+N at 1kHz, 500mW
into 8ΩBTL (3.3V) 1.0% (typ)
jTHD+N at 1kHz, 30mW
into 32ΩSE (3.3V) 1.0% (typ)
jSingle Supply Operation (V
DD
) 2.7 to 5.5V
jI
2
C/SPI Single Supply Operation 2.2 to 5.5V
Features
nI
2
C/SPI Control Interface
nI
2
C/SPI programmable National 3D Audio
nI
2
C/SPI controlled 32 step digital volume control (-54dB
to +18dB)
nThree independent volume channels (Left, Right, Mono)
nEight distinct output modes
nmicroSMD surface mount packaging
n“Click and Pop” suppression circuitry
nThermal shutdown protection
nLow shutdown current (0.1uA, typ)
Applications
nMoblie Phones
nPDAs
Boomer®is a registered trademark of National Semiconductor Corporation.
July 2006
LM4845 Output Capacitor-less Audio Subsystem with Programmable National 3D
© 2006 National Semiconductor Corporation DS201059 www.national.com
Typical Application
20105966
FIGURE 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
LM4845
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Typical Application (Continued)
20105967
FIGURE 2. Typical Audio Amplifier Application Circuit-Single Ended
LM4845
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Connection Diagrams
25-Bump micro SMD
201059K1
Top View
201059K0
Top View
XY - Date Code
TT - Die Traceability
G - Boomer Family
E5 - LM4845ITL
Bump Name Description
1 A1 SDA I
2
C or SPI Data
2A2 I
2
CSPIV
DD
I
2
C or SPI Interface Power Supply
3A3 R
HP3D2
Right Headphone 3D Input 2
4A4 R
HP3D1
Right Headphone 3D Input 1
5 A5 VOC Center Amplifier Output
6 B1 MONO- Loudspeaker Negative Output
7 B2 SCL I
2
C or SPI Clock
8 B3 ID_ENB Address Identification/Enable Bar
9 B4 Phone_In Mono Input
10 B5 NC No Connect
11 C1 GND Ground
12 C2 V
DD
Power Supply
13 C3 V
DD
Power Supply
14 C4 V
DD
Power Supply
15 C5 GND GND
16 D1 MONO+ Loudspeaker Positive Output
17 D2 NC No Connect
18 D3 L
HP3D1
Left Headphone 3D Input 1
19 D4 R
IN
Right Input Channel
20 D5 R
OUT
Right Headphone Output
21 E1 I
2
C SPI_SEL I
2
C or SPI Select
22 E2 C
BYPASS
Half-Supply Bypass
23 E3 L
HP3D2
Left Headphone 3D Input 2
24 E4 L
IN
Left Input Channel
25 E5 L
OUT
Left Headphone Output
LM4845
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 6.0V
Storage Temperature −65˚C to +150˚C
Input Voltage −0.3 to V
DD
+0.3
ESD Susceptibility (Note 3) 2.0kV
ESD Machine model (Note 6) 200V
Junction Temperature (T
J
) 150˚C
Solder Information (Note 1)
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
Thermal Resistance
θ
JA
(typ) - TLA25CBA 65˚C/W (Note 8)
Operating Ratings (Note 2)
Temperature Range −40˚C to 85˚C
Supply Voltage (V
DD
) 2.7V ≤V
DD
≤5.5V
Supply Voltage (I
2
C/SPI) 2.2V ≤V
DD
≤5.5V
Electrical Characteristics 3.3V (Notes 2, 7)
The following specifications apply for V
DD
= 3.3V, T
A
= 25˚C unless otherwise specified. [A
V
= 2 (BTL), A
V
= 1 (SE)]
Symbol Parameter Conditions LM4845 Units
(Limits)
Typical
(Note 4)
Limits
(Note 5)
I
DD
Supply Current
Output Modes 2, 4, 6
V
IN
= 0V; No load,
OCL = 0 (Table 2)
3.3 6.5 mA (max)
Output Modes 1, 3, 5, 7
V
IN
= 0V; No load, BTL,
OCL = 0 (Table 2)
6 11 mA (max)
I
SD
Shutdown Current Output Mode 0 0.1 1 µA (max)
V
OS
Output Offset Voltage V
IN
= 0V, Mode 5 (Note 10) 10 50 mV (max)
P
O
Output Power
MONO
OUT
;R
L
=8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1 500 400 mW (min)
R
OUT
and L
OUT
;R
L
=32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4 42 20 mW (min)
THD+N Total Harmonic Distortion Plus
Noise
MONO
OUT
f = 20Hz to 20kHz
P
OUT
= 250mW; R
L
=8Ω, BTL, Mode 1
0.5 %
R
OUT
and L
OUT
f = 20Hz to 20kHz
P
OUT
= 12mW; R
L
=32Ω, SE, Mode 4
0.5 %
N
OUT
Output Noise A-weighted (Note 9), Mode 5, BTL
input referred
26 µV
PSRR
Power Supply Rejection Ratio
MONO
OUT
V
RIPPLE
= 200mV
PP
; f = 217Hz,
C
B
= 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
Output Mode 1,7 71 dB
Output Mode 3 68 dB
Output Mode 5 63 dB
Power Supply Rejection Ratio
R
OUT
and L
OUT
V
RIPPLE
= 200mV
PP
; f = 217Hz
C
B
= 2.2µF, SE, C
O
= 100µF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
Output Mode 2 88 dB
Output Mode 4 76 dB
Output Mode 6, 7 76 dB
LM4845
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Electrical Characteristics 3.3V (Notes 2, 7) (Continued)
The following specifications apply for V
DD
= 3.3V, T
A
= 25˚C unless otherwise specified. [A
V
= 2 (BTL), A
V
= 1 (SE)]
Symbol Parameter Conditions LM4845 Units
(Limits)
Typical
(Note 4)
Limits
(Note 5)
Digital Volume Range
(R
IN
and L
IN
)
Input referred maximum attenuation -54 –53.25
–54.75
dB (min)
dB (max)
Input referred maximum gain 18 17.25
18.75
dB (min)
dB (max)
Mute Attenuation Output Mode 1, 3, 5 80 dB
MONO_IN Input Impedance
R
IN
and L
IN
Input Impedance
Maximum gain setting 11 8
14
kΩ(min)
kΩ(max)
Maximum attenuation setting 100 75
125
kΩ(min)
kΩ(max)
T
WU
Wake-Up Time from Shutdown C
B
= 2.2µF, OCL
C
B
= 2.2µF, SE
90
138 ms
LM4845
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Electrical Characteristics 5.0V (Notes 3, 7)
The following specifications apply for V
DD
= 5.0V, T
A
= 25˚C unless otherwise specified. [A
V
= 2 (BTL), A
V
= 1 (SE)].
Symbol Parameter Conditions LM4845 Units
(Limits)
Typical
(Note 4)
Limits
(Notes 5,
10)
I
DD
Supply Current
Output Modes 2, 4, 6
V
IN
= 0V; No load,
OCL = 0 (Table 2)
3.6 mA
Output Modes 1, 3, 5, 7
V
IN
= 0V; No Load,
OCL = 0 (Table 2)
6.8 mA
I
SD
Shutdown Current Output Mode 0 0.1 µA
V
OS
Output Offset Voltage V
IN
= 0V, Mode 5 (Note 10) 10 mV
P
O
Output Power
MONO
OUT
;R
L
=8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1 1.15 W
R
OUT
and L
OUT
;R
L
=32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4 75 mW
THD+N Total Harmonic Distortion Plus
Noise
MONO
OUT
f = 20Hz to 20kHz
P
OUT
= 500mW; R
L
=8Ω, BTL, Mode 1
0.5 %
R
OUT
and L
OUT
f = 20Hz to 20kHz
P
OUT
= 30mW; R
L
=32Ω,SE, Mode 4
0.5 %
N
OUT
Output Noise A-weighted (Note 9), Mode 5, BTL
input referred
26 µV
PSRR
Power Supply Rejection Ratio
MONO
OUT
V
RIPPLE
= 200mV
PP
; f = 217Hz,
C
B
= 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
Output Mode 1, 7 71 dB
Output Mode 3 68 dB
Output Mode 5 63 dB
Power Supply Rejection Ratio
R
OUT
and L
OUT
V
RIPPLE
= 200mV
PP
; f = 217Hz,
C
B
= 2.2µF, SE, C
O
= 100µF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
Output Mode 2 88 dB
Output Mode 4 76 dB
Output Mode 6, 7 76 dB
Digital Volume Range
(R
IN
and L
IN
)
Input referred maximum attenuation -54 –53.25
–54.75
dB
dB
Input referred maximum gain 18 17.25
18.75
dB
dB
Mute Attenuation Output Mode 1, 3, 5 80 dB
MONO_IN Input Impedance
R
IN
and L
IN
Input Impedance
Maximum gain setting 11 kΩ
kΩ
Minimum gain setting 100 kΩ
kΩ
T
WU
Wake-Up Time from Shutdown C
B
= 2.2µF, OCL
C
B
= 2.2µ, SE
122
184 ms
LM4845
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I
2
C/SPI (Notes 2, 7)
The following specifications apply for V
DD
= 5.0V and 3.3V, T
A
= 25˚C unless otherwise specified.
Symbol Parameter Conditions LM4845 Units
(Limits)
Typical
(Note 4)
Limits
(Notes 5,
10)
t
1
I
2
C Clock Period 2.5 µs (max)
t
2
I
2
C Clock Setup Time 100 ns (min)
t
3
I
2
C Data Hold Time 100 ns (min)
t
4
Start Condition Time 100 ns (min)
t
5
Stop Condition Time 100 ns (min)
f
SPI
Maximum SPI Frequency 1000 kHz (max)
t
EL
SPI ENB Low Time 100 ns (min)
t
DS
SPI Data Setup Time 100 µs (max)
t
ES
SPI ENB Setup Time 100 ns (min)
t
DH
SPI Data Hold Time 100 ns (min)
t
EH
SPI Enable Hold Time 100 ns (min)
t
CL
SPI Clock Low Time 500 ns (min)
t
CH
SPI Clock High Time 500 ns (min)
t
CS
SPI Clock Transition Time 100 ns (min)
V
IH
I
2
C/SPI Input Voltage High 0.7xI
2
CSPI
V
DD
V (min)
V
IL
I
2
C/SPI Input Voltage Low 0.3xI
2
CSPI
V
DD
V (max)
Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: Human body model, 100pF discharged through a 1.5kΩresistor.
Note 4: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 7: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 8: The given θJA for an LM4845ITL mounted on a demonstration board with a 9in2area of 1oz printed circuit board copper ground plane.
Note 9: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis.
Note 10: Potentially worse case: All three input stages are DC coupled to the BTL output stage.
LM4845
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External Components Description
Components Functional Description
1C
IN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the
amplifier’s input terminals. C
IN
also creates a highpass filter with the internal resistor R
i
(Input
Impedance) at f
c
= 1/(2πR
i
C
IN
).
2C
SUPPLY
This is the supply bypass capacitor. It filters the supply voltage applied to the V
DD
pin.
3C
BYPASS
This is the BYPASS pin capacitor. It filters the 1/2V
DD
voltage.
4C
3DL
This is the left channel 3D capacitor.
5C
3DR
This is the right channel 3D capacitor.
6C
OL
This is the left channel DC blocking output capacitor.
7C
OR
This is the right channel DC blocking output capacitor.
8C
I2CSPI_SUPPLY
This is the I
2
C/SPI supply bypass capacitor. It filters the I
2
C/SPI supply voltage applied to the
I
2
C/SPI_V
DD
pin.
9R
3DL
This is the left channel 3D external resistor. OPTIONAL.
10 R
3DR
This is the right channel 3D external resistor. OPTIONAL.
Typical Performance Characteristics
THD+N vs Frequency
V
DD
= 3.3V, R
L
=8Ω,P
O
= 250mW
Mode 1, BTL
THD+N vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Mode 4, OCL
20105929 20105930
THD+N vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Mode 6, OCL
THD+N vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Mode 4, SE
20105939 20105931
LM4845
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Typical Performance Characteristics (Continued)
THD+N vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Mode 6, SE
THD+N vs Frequency
V
DD
= 3.3V, R
L
=8Ω,P
O
= 250mW
Mode 5
20105940 20105941
THD+N vs Frequency
V
DD
= 5V, R
L
=8Ω,P
O
= 500mW
Mode 1, BTL
THD+N vs Frequency
V
DD
= 5V, R
L
=32Ω,P
O
= 30mW
Mode 4, OCL
20105942 20105943
THD+N vs Frequency
V
DD
= 5V, R
L
=32Ω,P
O
= 30mW
Mode 4, SE
THD+N vs Frequency
V
DD
= 5V, R
L
=32Ω,P
O
= 30mW
Mode 6, OCL
20105944 20105945
LM4845
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Typical Performance Characteristics (Continued)
THD+N vs Frequency
V
DD
= 5V, R
L
=32Ω,P
O
= 30mW
Mode 6, SE
THD+N vs Frequency
V
DD
= 5V, R
L
=8Ω,P
O
= 500mW
Mode 5
20105946 20105947
THD+N vs Output Power
V
DD
= 3.3V, R
L
=8Ω, f = 1kHz
Mode 1, BTL
THD+N vs Output Power
V
DD
= 3.3V, R
L
=8Ω, f = 1kHz
Mode 5, BTL
20105948 20105949
THD+N vs Output Power
V
DD
= 3.3V, R
L
=32Ω, f = 1kHz
Mode 4, OCL
THD+N vs Output Power
V
DD
= 3.3V, R
L
=32Ω, f = 1kHz
Mode 4, SE
20105950 20105951
LM4845
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Typical Performance Characteristics (Continued)
THD+N vs Output Power
V
DD
= 3.3V, R
L
=32Ω, f = 1kHz
Mode 6, OCL
THD+N vs Output Power
V
DD
= 3.3V, R
L
=32Ω, f = 1kHz
Mode 6, SE
20105952 20105953
THD+N vs Output Power
V
DD
= 5V, R
L
=8Ω, f = 1kHz
Mode 1, BTL
THD+N vs Output Power
V
DD
= 5V, R
L
=8Ω, f = 1kHz
Mode 5, BTL
20105954 20105955
THD+N vs Output Power
V
DD
= 5V, R
L
=32Ω, f = 1kHz
Mode 4, OCL
THD+N vs Output Power
V
DD
= 5V, R
L
=32Ω, f = 1kHz
Mode 4, SE
20105956 20105957
LM4845
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Typical Performance Characteristics (Continued)
THD+N vs Output Power
V
DD
= 5V, R
L
=32Ω, f = 1kHz
Mode 6, OCL
THD+N vs Output Power
V
DD
= 5V, R
L
=32Ω, f = 1kHz
Mode 6, SE
20105958 20105959
PSRR vs Frequency
V
DD
= 3.3V, 0dB
Mode 4, OCL
PSRR vs Frequency
V
DD
= 3.3V, 0dB
Mode 4, SE
20105960 20105961
PSRR vs Frequency
V
DD
= 3.3V, 0dB
Mode 6, OCL
PSRR vs Frequency
V
DD
= 3.3V, 0dB
Mode 6, SE
20105962 20105963
LM4845
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Typical Performance Characteristics (Continued)
PSRR vs Frequency
V
DD
= 3.3V, 6dB
Mode 1, BTL
PSRR vs Frequency
V
DD
= 3.3V, 6dB
Mode 5, BTL
20105964 20105965
Noise
V
DD
= 3.3V, Mode 4, OCL
Noise
V
DD
= 3.3V, Mode 4, SE
20105968 20105969
Noise
V
DD
= 3.3V, Mode 6, SE
Noise
V
DD
= 3.3V, Mode 5, BTL
20105970 20105971
LM4845
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Typical Performance Characteristics (Continued)
Noise
V
DD
= 3.3V, Mode 1, BTL
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=8Ω
f = 1kHz, BTL, Mode 1, BTL
20105972 20105978
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=8Ω
f = 1kHz, BTL, Mode 5
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=32Ω
f = 1kHz, OCL, Mode 4
20105979 20105980
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=32Ω
f = 1kHz, OCL, Mode 6
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=32Ω
f = 1kHz, SE, Mode 4
20105981 20105982
LM4845
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Typical Performance Characteristics (Continued)
Power Dissipation vs Output Power
V
DD
= 3.3V, R
L
=32Ω
f = 1kHz, SE, Mode 6
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=8Ω
f = 1kHz, BTL, Mode 1
20105983 20105984
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=8Ω
f = 1kHz, BTL, Mode 5
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=32Ω
f = 1kHz, OCL, Mode 4
20105985 20105986
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=32Ω
f = 1kHz, OCL, Mode 6
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=32Ω
f = 1kHz, SE, Mode 4
20105987 20105988
LM4845
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Typical Performance Characteristics (Continued)
Power Dissipation vs Output Power
V
DD
= 5V, R
L
=32Ω
f = 1kHz, SE, Mode 6
Crosstalk vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Right-Left, OCL, Mode 4
20105989 20105990
Crosstalk vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Right-Left, OCL, Mode 6
Crosstalk vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Right-Left, SE, Mode 4
20105991 20105992
Crosstalk vs Frequency
V
DD
= 3.3V, R
L
=32Ω,P
O
= 12mW
Right-Left, SE, Mode 6
Supply Current vs Supply Voltage
R
L
=8Ω, Mode 1
20105993 20105996
LM4845
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Typical Performance Characteristics (Continued)
Supply Current vs Supply Voltage
R
L
=8Ω, Mode 5
Supply Current vs Supply Voltage
R
L
=32Ω, OCL, Mode 4
20105997 20105998
Supply Current vs Supply Voltage
R
L
=32Ω, OCL, Mode 6
Supply Current vs Supply Voltage
R
L
=32Ω, SE, Mode 4
201059A0 201059A1
Supply Current vs Supply Voltage
R
L
=32Ω, SE, Mode 6
Output Power vs Supply Voltage
R
L
=8Ω, Mode 1
201059A2 201059A3
LM4845
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Typical Performance Characteristics (Continued)
Output Power vs Supply Voltage
R
L
=8Ω, Mode 5
Output Power vs Supply Voltage
R
L
=32Ω, Mode 4
201059A4 201059A5
Output Power vs Supply Voltage
R
L
=32Ω, OCL, Mode 6
Output Power vs Supply Voltage
R
L
=32Ω, SE, Mode 4
201059A6 201059A7
Output Power vs Supply Voltage
R
L
=32Ω, SE, Mode 6
201059A8
LM4845
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Application Information
I
2
C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I
2
CSPI_SEL: This is tied LOW for I
2
C mode.
I
2
C COMPATIBLE INTERFACE
The LM4845 uses a serial bus which conforms to the I
2
C
protocol to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
2
C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4845.
The I
2
C address for the LM4845 is determined using the
ID_ENB pin. The LM4845’s two possible I
2
C chip addresses
are of the form 111110X
1
0 (binary), where X
1
= 0, if ID_ENB
is logic LOW; and X
1
= 1, if ID_ENB is logic HIGH. If the I
2
C
interface is used to address a number of chips in a system,
the LM4845’s chip address can be changed to avoid any
possible address conflicts.
The bus format for the I
2
C interface is shown in Figure 3. The
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is HIGH. The start signal will alert all
devices attached to the I
2
C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is HIGH.
For I
2
C interface operation, the I
2
CSPI_SEL pin needs to be
tied LOW (and tied high for SPI operation).
After the last bit of the address bit is sent, the master
releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the
LM4845 has received the address correctly, then it holds the
data line LOW during the clock pulse. If the data line is not
held LOW during the acknowledge clock pulse, then the
master should abort the rest of the data transfer to the
LM4845.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
HIGH.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4845 received the data.
If the master has more data bytes to send to the LM4845,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes HIGH while the clock signal is HIGH. The data
line should be held HIGH when not in use.
I
2
C INTERFACE POWER SUPPLY PIN (I
2
CV
DD
)
The LM4845’s I
2
C interface is powered up through the
I
2
CV
DD
pin. The LM4845’s I
2
C interface operates at a volt-
age level set by the I
2
CV
DD
pin which can be set indepen-
dent to that of the main power supply pin V
DD
. This is ideal
whenever logic levels for the I
2
C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
201059F5
FIGURE 3. I
2
C Bus Format
LM4845
www.national.com 20
Application Information (Continued)
SPI DESCRIPTION
0. I
2
CSPI_SEL: This pin is tied HIGH for SPI mode.
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 1MHz for the CLK pin.
3. CLK must remain HIGH for at least 500ns (t
CH
) after the
rising edge of CLK, and CLK must remain LOW for at least
500ns (t
CL
) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 100ns (t
DS
)
before the rising edge of CLK. Also, any transition on DATA
must occur at least 100ns (t
DH
) after the rising edge of CLK
and stabilize before the next rising edge of CLK.
5.ID_ENB should be LOW only during serial data transmis-
sion.
6. ID_ENB must be LOW at least 100ns (t
ES
) before the first
rising edge of CLK, and ID_ENB has to remain LOW at least
100ns (t
EH
) after the eighth rising edge of CLK.
7. If ID_ENB remains HIGH for more than 100ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ID_ENB is LOW for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when
ID_ENB transitions to logic-high.
9. ID_ENB must remain HIGH for at least 100ns (t
EL
) to latch
in the data.
10. Coincidental rising or falling edges of CLK and ID_ENB
are not allowed. If CLK is to be held HIGH after the data
transmission, the falling edge of CLK must occur at least
100ns (t
CS
) before ID_ENB transitions to LOW for the next
set of data.
201059F4
FIGURE 4. I
2
C Timing Diagram
20105924
FIGURE 5. SPI Timing Diagram
LM4845
www.national.com21
Application Information (Continued)
TABLE 1. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip
Address 111110EC0
ID_ENB = 0 11111000
ID_ENB = 1 11111010
TABLE 2. Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
Mode Control 0 0 0 0 OCL MC2 MC1 MC0
Programmable 3D 0 1 0 0 N3D3 N3D2 N3D1 N3D0
Mono Volume
Control
1 0 0 MVC4 MVC3 MVC2 MVC1 MVC0
Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0
Right Volume
Control
1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0
1. Bits MVC0 — MVC4 control 32 step volume control for MONO input
2. Bits LVC0 — LVC4 control 32 step volume control for LEFT input
3. Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
4. Bits MC0 — MC2 control 8 distinct modes
5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1=1a“narrower” aural effect
7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
8. N3D1 selects between two different 3D configurations
TABLE 3. Programmable National 3D Audio
N3D3 N3D2
Low 0 0
Medium 0 1
High 1 0
Maximum 1 1
TABLE 4. Output Mode Selection
Output
Mode
Number
MC2 MC1 MC0 Handsfree Speaker
Output
Right HP Output Left HP Output
0 0 0 0 SD SD SD
1 0 0 1 2xG
P
x P MUTE MUTE
2 0 1 0 SD G
P
xP G
P
xP
3 0 1 1 2x(G
L
xL+G
R
x R) MUTE MUTE
4 1 0 0 SD G
R
xR G
L
xL
5 1 0 1 2x(G
L
xL+G
R
xR+
G
P
xP)
MUTE MUTE
6 1 1 0 SD G
R
xR+G
P
xP G
L
xL+G
P
xP
7 1 1 1 2xG
P
xP G
R
xR+G
P
xP G
L
xL+G
P
xP
On initial POWER ON, the default mode is 000
P = Phone in
R=R
IN
L=L
IN
SD = Shutdown
MUTE = Mute Mode
GP= Phone In (Mono) volume control gain
GR= Right stereo volume control gain
GL= Left stereo volume control gain
LM4845
www.national.com 22
Application Information (Continued)
TABLE 5. Volume Control Table
Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Headphone
Gain, dB
Speaker
Gain, dB
(BTL)
100000–54.00 –48.00
200001–46.50 –40.50
300010–40.50 –34.50
400011–34.50 –28.50
500100–30.00 –24.00
600101–27.00 –21.00
700110–24.00 –18.00
800111–21.00 –15.00
901000–18.00 –12.00
1001001–15.00 –9.00
1101010–13.50 –7.50
1201011–12.00 –6.00
1301100–10.50 –4.50
1401101–9.00 –3.00
1501110–7.50 –1.50
1601111–6.00 0.00
1710000–4.50 1.50
1810001–3.00 3.00
1910010–1.50 4.50
20100110.00 6.00
21101001.50 7.50
22101013.00 9.00
23101104.50 10.50
24101116.00 12.00
25110007.50 13.50
26110019.00 15.00
271101010.50 16.50
281101112.00 18.00
291110013.50 19.50
301110115.00 21.00
311111016.50 22.50
321111118.00 24.00
1. x=M,L,orR
2. Gain / Attenuation is from input to output
LM4845
www.national.com23
Application Information (Continued)
NATIONAL 3D ENHANCEMENT
The LM4845 features a stereo headphone, 3D audio en-
hancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement
creates a perceived spatial effect optimized for stereo head-
phone listening. The LM4845 can be programmed for a
“narrow” or “wide” soundstage perception. The narrow
soundstage has a more focused approaching sound direc-
tion, while the wide soundstage has a spatial, theater-like
effect. Within each of these two modes, four discrete levels
of 3D effect that can be programmed: low, medium, high,
and maximum (Table 2), each level with an ever increasing
aural effect, respectively. The difference between each level
is 3dB.
The external capacitors, shown in Figure 6, are required to
enable the 3D effect. The value of the capacitors set the
cutoff frequency of the 3D effect, as shown by Equations 1
and 2. Note that the internal 20kΩresistor is nominal
(±25%).
f
3DL(-3dB)
=1/2π* 20kΩ*C
3DL
(1)
f
3DR(-3dB)
=1/2π* 20kΩ*C
3DR
(2)
Optional resistors R
3DL
and R
3DR
can also be added (Figure
7) to affect the -3dB frequency and 3D magnitude.
f
3DL(-3dB)
=1/2π* (20kΩ+R
3DL
)*C
3DL
(3)
f
3DR(-3dB)
=1/2π* 20kΩ+R
3DR
)*C
3DR
(4)
∆AV (change in AC gain)=1/1+M,where M represents
some ratio of the nominal internal resistor, 20kΩ(see ex-
ample below).
f
3dB
(3D)=1/2π(1 + M)(20kΩ*C
3D
) (5)
C
Equivalent
(new) = C
3D
/1+M (6)
TABLE 6. Pole Locations
R
3D
(kΩ)
(optional)
C
3D
(nF) M ∆AV (dB) f-3dB (3D)
(Hz)
Value of C
3D
to keep same
pole location
(nF)
new Pole
Location
(Hz)
0680 0117
1 68 0.05 –0.4 111 64.8 117
5 68 0.25 –1.9 94 54.4 117
10 68 0.50 –3.5 78 45.3 117
20 68 1.00 –6.0 59 34.0 117
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 8ΩLOAD
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ωtrace resistance reduces
the output power dissipated by an 8Ωload from 158.3mW to
156.4mW. The problem of decreased load dissipation is
exacerbated as load impedance decreases. Therefore, to
maintain the highest load dissipation and widest output volt-
age swing, PCB traces that connect the output pins to a load
must be as wide as possible.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
20105995
FIGURE 6. External 3D Effect Capacitors
20105994
FIGURE 7. External RC Network with Optional R
3DL
and R
3DR
Resistors
LM4845
www.national.com 24
Application Information (Continued)
and reduced output power. Even with tightly regulated sup-
plies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4845 drives a load, such as a speaker, connected
between outputs, MONO+ and MONO-.
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between MONO- and
MONO+ and driven differentially (commonly referred to as
”bridge mode”). This results in a differential or BTL gain of:
A
VD
= 2(R
f
/R
i
)=2 (7)
Bridge mode amplifiers are different from single-ended am-
plifiers that drive loads connected between a single amplifi-
er’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended con-
figuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
MONO- and MONO+ outputs at half-supply. This eliminates
the coupling capacitor that single supply, single-ended am-
plifiers require. Eliminating an output coupling capacitor in a
typical single-ended configuration forces a single-supply am-
plifier’s half-supply bias voltage across the load. This in-
creases internal IC power dissipation and may permanently
damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissi-
pation. The LM4845 has a pair of bridged-tied amplifiers
driving a handsfree speaker, MONO. The maximum internal
power dissipation operating in the bridge mode is twice that
of a single-ended amplifier. From Equation (8), assuming a
5V power supply and an 8Ωload, the maximum MONO
power dissipation is 634mW.
P
DMAX-SPKROUT
= 4(V
DD
)
2
/(2π
2
R
L
): Bridge Mode (8)
The LM4845 also has a pair of single-ended amplifiers driv-
ing stereo headphones, R
OUT
and L
OUT
. The maximum in-
ternal power dissipation for R
OUT
and L
OUT
is given by
equation (9) and (10). From Equations (9) and (10), assum-
ing a 5V power supply and a 32Ωload, the maximum power
dissipation for L
OUT
and R
OUT
is 40mW, or 80mW total.
P
DMAX-LOUT
=(V
DD
)
2
/(2π
2
R
L
): Single-ended Mode (9)
P
DMAX-ROUT
=(V
DD
)
2
/(2π
2
R
L
): Single-ended Mode(10)
The maximum internal power dissipation of the LM4845
occurs when all 3 amplifiers pairs are simultaneously on; and
is given by Equation (11).
P
DMAX-TOTAL
=
P
DMAX-SPKROUT
+P
DMAX-LOUT
+P
DMAX-ROUT
(11)
The maximum power dissipation point given by Equation
(11) must not exceed the power dissipation given by Equa-
tion (12):
P
DMAX
=(T
JMAX
-T
A
)/θ
JA
(12)
The LM4845’s T
JMAX
= 150˚C. In the ITL package, the
LM4845’s θ
JA
is 65˚C/W. At any given ambient temperature
T
A
, use Equation (12) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (12) and substituting P
DMAX-TOTAL
for P
DMAX
’ re-
sults in Equation (13). This equation gives the maximum
ambient temperature that still allows maximum stereo power
dissipation without violating the LM4845’s maximum junction
temperature.
T
A
=T
JMAX
-P
DMAX-TOTAL
θ
JA
(13)
For a typical application with a 5V power supply and an 8Ω
load, the maximum ambient temperature that allows maxi-
mum stereo power dissipation without exceeding the maxi-
mum junction temperature is approximately 104˚C for the
ITL package.
T
JMAX
=P
DMAX-TOTAL
θ
JA
+T
A
(14)
Equation (14) gives the maximum junction temperature T
J-
MAX
. If the result violates the LM4845’s 150˚C, reduce the
maximum junction temperature by reducing the power sup-
ply voltage or increasing the load resistance. Further allow-
ance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (11)
is greater than that of Equation (12), then decrease the
supply voltage, increase the load impedance, or reduce the
ambient temperature. If these measures are insufficient, a
heat sink can be added to reduce θ
JA
. The heat sink can be
created using additional copper area around the package,
with connections to the ground pin(s), supply pin and ampli-
fier output pins. External, solder attached SMT heatsinks
such as the Thermalloy 7106D can also improve power
dissipation. When adding a heat sink, the θ
JA
is the sum of
θ
JC
,θ
CS
, and θ
SA
.(θ
JC
is the junction-to-case thermal im-
pedance, θ
CS
is the case-to-sink thermal impedance, and
θ
SA
is the sink-to-ambient thermal impedance). Refer to the
Typical Performance Characteristics curves for power dissi-
pation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 1µF in parallel with a 0.1µF filter capacitors to stabilize
the regulator’s output, reduce noise on the supply line, and
improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.1µF
tantalum bypass capacitance connected between the
LM4845
www.national.com25
Application Information (Continued)
LM4845’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4845’s
power supply pin and ground as short as possible. Connect-
ing a 2.2µF capacitor, C
B
, between the BYPASS pin and
ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases turn-on time and can compromise
the amplifier’s click and pop performance. The selection of
bypass capacitor values, especially C
B
, depends on desired
PSRR requirements, click and pop performance (as ex-
plained in the section, Proper Selection of External Compo-
nents), system cost, and size constraints.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input coupling capacitor (C
i
in Figures 1 & 2). A high value
capacitor can be expensive and may compromise space
efficiency in portable designs. In many cases, however, the
speakers used in portable systems, whether internal or ex-
ternal, have little ability to reproduce signals below 150Hz.
Applications using speakers with this limited frequency re-
sponse reap little improvement by using large input capaci-
tor.
The internal input resistor (R
i
), nominal 20kΩ, and the input
capacitor (C
i
) produce a high pass filter cutoff frequency that
is found using Equation (15).
f
c
=1/(2πR
i
C
i
) (15)
As an example when using a speaker with a low frequency
limit of 150Hz, C
i
, using Equation (15) is 0.053µF. The
0.22µF C
i
shown in Figure 1 allows the LM4845 to drive high
efficiency, full range speaker whose response extends below
40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to value of C
B
, the capacitor con-
nected to the BYPASS bump. Since C
B
determines how fast
the LM4845 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4845’s
outputs ramp to their quiescent DC voltage (nominally V
DD
/
2), the smaller the turn-on pop. Choosing C
B
equal to 1.0µF
along with a small value of C
i
(in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown func-
tion. As discussed above, choosing C
i
no larger than neces-
sary for the desired bandwidth helps minimize clicks and
pops. C
B
’s value should be in the range of 5 times to 7 times
the value of C
i
. This ensures that output transients are
eliminated when power is first applied or the LM4845 re-
sumes operation after shutdown.
LM4845
www.national.com 26
Application Information (Continued)
LM4845 ITL DEMO BOARD ARTWORK
Top Overlay
201059E0
Top Layer
20105938
LM4845
www.national.com27
Application Information (Continued)
Bottom Layer
20105937
LM4845
www.national.com 28
Revision History
Rev Date Description
1.0 11/08/05 Fixed some typos, then re-released D/S to the WEB (per Allan).
1.1 12/21/05 Edited the X1, X2, and X3 in the mktg outline, then re-released D/S to the WEB.
1.2 01/10/06 Fixed typo, then re-released doc to the WEB.
1.3 01/11/06 Fixed more typo, then re-released doc to the WEB.
1.4 07/06/06 Added the Twu row in the 3.3V and 5.0V EC tables ( per Allan S.), then re-released D/S to the WEB.
LM4845
www.national.com29
Physical Dimensions inches (millimeters) unless otherwise noted
25 – Bump micro SMD
Order Number LM4845ITL
NS Package Number TLA25CBA
Dimensions are in millimeters
X
1
= 2.543 ±0.03 X
2
= 2.517 ±0.03 X
3
= 0.600 ±0.075
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
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Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
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Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
LM4845 Output Capacitor-less Audio Subsystem with Programmable National 3D
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