1 CGD15HB62LP Rev. -, 05-2016
CGD15HB62LP
Dual Channel Isolated Gate Driver
Cree CAS325M12HM2 C2M SiC Half Bridge Module Optimized
Features
Package
Optimized for Cree’s High Performance
CAS325M12HM2 Half Bridge Power Modules
High-Frequency, Ultra-Fast Switching
Operation
On Board 3 W or 6 W Isolated Power Supplies
Configurable UVLO with Hysteresis
Direct Mount Low Inductance Design
On-Board Overcurrent, Overlap, and Reverse
Polarity Protection
Part Number
Package
Marking
CGD15HB62LP
PCBA
CGD15HB62LP V1
For Use with Cree Module
CAS325M12HM2, 1200 V, 325 A Module Half
Bridge CPM2 Variants for Module Junction
Temperatures up to 150 °C
Applications
DC Bus Voltages up to 1000 V
Maximum Ratings
Parameter
Value
Unit
Test Conditions
Supply Voltage
-0.5 to 18
V
Logic Level Inputs
-0.5 to 5.5
Output Peak Current
±14
A
TA = 25 °C
Output Average Current
±4
Maximum Switching Frequency
100
kHz
3 W Power Supply + CAS325M12HM2
Ambient Operating Temperature
-50 to 95
°C
Storage Temperature
-50 to 125
VDrive
+20/-5 V
IG
±14 A
RG
5 Ω
2 CGD15HB62LP Rev. -, 05-2016
Gate Driver Electrical Characterization
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
VDC
Supply Voltage
9
12
18
V
VUVLO
Secondary UVLO
18
Inactive
16
Active
2
Hysteresis
VIH
High Level Logic Input Voltage
3.5
5.5
Single-Ended Inputs
VIL
Low Level Logic Input Voltage
0
1.5
VIDCM
Differential Input Common
Mode Range
-7
-
+12
Differential Inputs
VIDTH
Differential Input Threshold
Voltage
-200
-50
mV
VID = VPos-Line VNeg-Line
VOH
High Level Logic Output Voltage
VDD-
0.025
V
VOL
Low Level Logic Output Voltage
VSS +
0.025
VGATE,HIGH
High Level Output Voltage
+20
VGATE,LOW
Low Level Output Voltage
-5
VIOWM
Working Isolation Voltage
1500
VRMS
CISO
Isolation Capacitance
17
pF
Per Channel
CMTI
Common Mode Transient
Immunity
100
kV/µs
RGIC-ON
Output Resistance1
0.4
1.5
Ω
Gate Drive IC
RGIC-OFF
Output Resistance1
0.3
1.2
RGEXT-ON
External Output Resistance2
4.99
External SMD Resistor
RGEXT-OFF
External Output Resistance2
4.99
DVF-OFF
Turn-off Diode Forward Voltage
0.62
0.67
0.82
V
tON
Output Rise Time
250
ns
CLoad = 19 nF
From 10% to 90%
tOFF
Output Fall Time
140
tPHL/PLH
Propagation Delay
75
tPD
Over-current Propagation Delay
to FAULT Signal Low
40
Does Not Include
Blanking
RSS
Soft-Shutdown Resistance3
30.1
Ω
tOFF-SS
Output Fall Time Soft-Shutdown
1.5
µs
Output pulled low
through RSS
1
Output resistance of totem pole IC
2
Additional output resistance is added with SMD resistors. A diode is provided to allow control of turn-off separately. The diode makes the effective
turn-off resistance be the parallel combination of the RGEXT-ON and RGEXT-OFF while the turn-on effective resistance is RGEXT-ON. Standard value is 4.99 Ω for
both turn-on and turn-off. See Figure 1 for configuration.
3
Soft-Shutdown Resistor will safely turn off the Gate in the event an over-current is detected by the Desaturation Protection circuit.
3 CGD15HB62LP Rev. -, 05-2016
Input Connector Information
Pin Number
Name
Description
1
Power
Power Supply Input Pin
2
Common
Common
3
HS-P
Positive Line of 5 V Differential High Side PWM Signal Pair.
Terminated Into 250 Ω.
4
HS-N
Negative Line of 5 V Differential High Side PWM Signal Pair.
Terminated Into 250 Ω.
5
LS-P
Positive Line of 5 V Differential Low Side PWM Signal Pair.
Terminated Into 250 Ω.
6
LS-N
Negative Line of 5 V Differential Low Side PWM Signal Pair.
Terminated Into 250 Ω.
7
FAULT - P
Positive Line of 5 V Differential Fault Condition Signal Pair.
Drive Strength 20 mA.
8
FAULT - N
Negative Line of 5 V Differential Fault Condition Signal Pair.
Drive Strength 20 mA.
9
RTD-P
Positive Line of 5 V Temperature Dependent Resistor Output Signal Pair.
Drive Strength 20 mA. Temperature Measurement is Encoded Via PWM.
10
RTD-N
Negative Line of 5 V Temperature Dependent Resistor Output Signal Pair. Drive
Strength 20mA. Temperature Measurement is Encoded Via PWM.
11
PS-Dis
Pull Down to Disable Power Supply. Pull Up, or Leave Floating to Enable. Gate-
Source will be Connected with 10 kΩ when disabled.
12
Common
Common
13
PWM-EN
Pull Down to Disable PWM Input Logic. Pull Up/Leave floating to enable. Gate-
source will be held low through gate resistor if power supplies are enabled.
14
Common
Common
15
OC-EN
Over-current Protection Enable. Pull down to disable detection of over-current
fault. PWM and UVLO will continue to function. Pull up or leave floating to
enable detection of over-current fault.
16
Common
Common
Inputs 3 10 are differential pairs.
4 CGD15HB62LP Rev. -, 05-2016
Block Diagram
DC
DC
MGJ3T12150505
ISO7842
- 5 V
20 V
VDS Measure DC +
IXDD614YI
12 V
HS - Fault
Over-current
Enable
HS PWM
PWM Enable
PS-Disable
DC
DC
MGJ3T12150505
ISO7842
- 5 V
20 V
VDS Measure Midpoint
IXDD614YI
LS - Fault
LS - RTD
Over-current Enable
LS PWM
PWM Enable
PS-Disable
Fault
Fig 1. Block Diagram
5 CGD15HB62LP Rev. -, 05-2016
Driver Interface
Fig 2. Top View
Connector
Name
Description
JT2
Signal Input
Description in Input Connection Information
JT1
HS-Drain
High Side Over-current protection connector
Connect to DC +
JT3
LS-Drain
Low Side Over-current protection connector
Connect to the Midpoint or populate RT22 with a 0 resistor
JB1
HS-GS
Red Gate
Green Source
JB2
LS-GS
Red Gate
Green Source
Blue RTD
JT3
JB1
JB2
JT2
Pin 1
JT1
ITGD2-3001 V3B
CGD15HB62LP
6 CGD15HB62LP Rev. -, 05-2016
Signal Description
PWM Signals: High side and low side PWM must be differential signals
4
. The termination impedance of
the differential receiver is 250 Ω. A reference single-ended to differential converter is available as an
optimized companion product. Overlap protection is provided to prevent both the high side and low side
gates from turning on simultaneously. The overlap protection should not be used as a dead time
generator.
FAULT Signal: The fault signal is a differential output4 with a maximum drive strength of 20mA. A high
signal (positive line > negative line) means there are no fault conditions for either gate driver channel.
This signal will be low if a UVLO or over-current fault is detected on either channel. See below for further
description for what the individual faults indicate.
UVLO Fault: The UVLO circuit detects when the output rails of the isolated DC/DC converter falls below
safe operating conditions for the gate driver. A UVLO fault indicates that the potential between the split
output rails has fallen below the UVLO active level. The gate for the channel where the fault occurred will
be pulled low through RG for the duration of the fault regardless of the PWM input signal. The fault will
automatically clear once the potential has risen above the UVLO inactive level. There is hysteresis for
this fault to ensure safe operating conditions, and the inactive and active regions can be configured
through on-board resistors. The UVLO faults for both channels are combined along with the over-current
fault in the FAULT output signal.
Over-Current Fault: An over-current fault is an indication of an over-current event in the SiC power
module. The over-current protection circuit measures the drain-source voltage and the fault will indicate
if this voltage has risen above a level corresponding to the safe current limit. A drain sense connection
is provided by quick-connect spade connectors for both high side and low side. The low side drain
connection can optionally be connected on-board to the high side source through a jumper. When a fault
has occurred the corresponding gate driver channel will be disabled and the gate will be pulled down
through a soft-shutdown resistor, RSS3. The drain-source limit can be configured through on-board
resistors. The over-current protection is enabled by default, but it can be disabled by pulling the OC-EN
pin low. The gate driver will operate correctly with this protection disabled. The over-current fault is
latched upon detection and must be cleared by the user by a low pulse of the OC-EN signal.
RTD Signal: RTD output is a differential signal4 that measures the resistance of the RTD integrated into
XAS325M12HM2 modules. The signal is a 50 kHz PWM that encodes the resistance of the RTD. The
approximate temperature of the module can be determined from this resistance
5
. The module
temperature can be calculated using the formula,   󰇛󰇜 .
PS-Dis Signal: PS-DIS signal disables the output of the isolated DC/DC converters for the two channels.
It is a single-ended input that must be pulled low to turn off the power supplies. This can be used for
startup sequencing.
4
A single-ended to differential converter for both input and output is available as an optimized companion product.
5
See CAS325M12HM2 with Optional RTD Application Note for further description of the RTD measurements.
7 CGD15HB62LP Rev. -, 05-2016
PWM-EN Signal: This is a single-ended input that enables the PWM inputs for both channels. When this
signal is pulled down the differential receivers for both channels are disabled and the gates will both be
pulled low through RG. All protection circuitry and power supplies will continue to operate including FAULT
and RTD outputs.
Over-Voltage and Reverse Polarity Protection: Power input on pin 1 of connector JT2 features a Zener
diode to protect the gate driver from damage by connecting a power source that exceeds the voltage
rating of the gate driver. If over-voltage protection has occurred power should be removed to allow the
PTC fuse to reset. There is also a diode in-line with the power input to protect against connecting a power
source with positive and negative polarity reversed.
Input Connector
SBH11-PBPC-D08-ST-BK
Drain connector for Overcurrent Protection: TE Connectivity 735187-2
Suggested Mating Parts
SFH210-PPPC-D08-ID-BK
SFH11-PBPC-D08-ST-BK
SFH11-PBPC-D08-RA-BK
Drain connector for Overcurrent: TE Connectivity 2-520272-2
Power Estimates
The gate driver power required is calculated using the formula below. The gate charge is dependent on the
datasheets of the module being driven. The gate driver voltage (VGD) is 25V for this gate driver. Once the
required gate driver power is calculated the required input power can be calculated from the
MGJ3T12150505MC and MGJ6T12150505MC efficiency curves on the power supplies datasheet. This
calculation is for one channel of the gate driver.
 
 
8 CGD15HB62LP Rev. -, 05-2016
Dimensions [in(mm)]
Fig 3. Dimensions
Important Notes
Suitability of this product for any application may depend on product parameters not specified in this
document. Accordingly, buyers are cautioned to evaluate actual products against their needs and not to rely
solely on the data and information presented in this document.
The product described has not been designed or tested for use in, and is not intended for use in, applications
implanted into the human body or in applications in which failure of the product could lead to death, personal
injury or property damage, including but not limited to equipment used in the operation of nuclear facilities,
life-support machines, cardiac defibrillators or similar emergency medical equipment, vehicle navigation,
communication or control systems, or air traffic control systems.
The product described is not eligible for Distributor Stock Rotation or Inventory Price Protection.
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703
USA Tel: +1.919.313.5451
www.cree.com/power
Copyright © 2016 Cree, Inc. All rights reserved.
The information in this document is subject to change without notice.
Cree, the Cree logo, and Zero recovery are registered trademarks of Cree, Inc.
CGD15HB62LP