MSC23409C/CL-xxDS9¡ Semiconductor
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¡ Semiconductor
MSC23409C/CL-xxDS9
4,194,304-Word ¥ 9-Bit DRAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The OKI MSC23409C/CL-xxDS9 is a fully decoded 4,194,304-word ¥ 9-bit CMOS Dynamic
Random Access Memory Module composed of nine 4-Mb DRAMs (4M ¥ 1) in SOJ packages
mounted with nine decoupling capacitors on a 30-pin glass epoxy single-inline package. This
module is generally used for memory expansion in parity applications such as workstations. The
low-power version (CL) offers reduced power consumption for mobile computing applications
like laptops and palmtops.
FEATURES
• 4-Meg ¥ 9-bit organization
• 30-Pin Socket Insertable Module
MSC23409C/CL-xxDS9 : Solder tab
• Single 5 V supply ±10% tolerance
• Access times : 60, 70, 80 ns
• Input : TTL compatible
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms (128 ms : L-version)
•CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Fast Page Mode capability
PRODUCT FAMILY
Family Access Time (Max.) Cycle Time
(Min.)
Power Dissipation
Operating (Max.)
Standby (Max.)t
RAC
t
AA
t
CAC
MSC23409C/CL-60DS9
MSC23409C/CL-70DS9
MSC23409C/CL-80DS9
60 ns
70 ns
80 ns
30 ns
35 ns
40 ns
15 ns
20 ns
20 ns
110 ns
130 ns
150 ns
4950 mW
4455 mW
3960 mW
49.5 mW/
9.9 mW (L-version)
E2H0093-15-90
This version: Sep. 1995
MSC23409C/CL-xxDS9¡ Semiconductor
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PIN CONFIGURATION
MSC23409C/CL-xxDS9
Typ.
10.16 Typ.
6.35
82.14 Typ.3.38 Tpy.
88.9 ±0.2
73.66
2.03 Typ.
1.27 +0.1
–0.08
5.28 Max.
2.54 ±0.1
30
1
* 1
*1 The common size difference of the board width 12.5 mm of its height is
specified as ±0.2. The value above 12.5 mm is specified as ±0.5.
20.45 Max.
5.59 Typ.
1.78 Typ.
2.54 Min.
f 3.18
V
CC
Pin Name
CAS
DQ0
A0
A1
DQ1
A2
A3
V
SS
DQ2
A4
Pin Name
A5
DQ3
A6
A7
DQ4
A8
A9
A10
DQ5
WE
Pin Name
V
SS
DQ6
NC
DQ7
Q8
RAS
CAS8
D8
V
CC
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin No.
11
12
13
14
15
16
17
18
19
20
Pin No.
21
22
23
24
25
26
27
28
29
30
MSC23409C/CL-xxDS9¡ Semiconductor
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BLOCK DIAGRAM
A0 - A10
RAS0
CAS0
WE
VCC
VSS
C1 C9
RAS
CAS
WE
VCC
DQ0
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ1
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ2
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ3
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ4
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ5
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ6
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
DQ7
A0 - A10
D
Q
VSS
RAS
CAS
WE
VCC
Q8
A0 - A10
D
Q
VSS
D8
CAS8
MSC23409C/CL-xxDS9¡ Semiconductor
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
Capacitance
Voltage on Any Pin Relative to V
SS
Parameter Symbol Rating Unit
V
IN
, V
OUT
–1.0 to 7.0 V
Voltage V
CC
Supply Relative to V
SS
V
CC
–1.0 to 7.0 V
Short Circuit Output Current I
OS
50 mA
Power Dissipation P
D
9W
Operating Temperature T
opr
0 to 70 °C
Storage Temperature T
stg
–40 to 125 °C
Parameter Symbol Unit
Power Supply Voltage V
CC
Input High Voltage
Typ.
Min. Max.
4.5 5.0 5.5 V
(Ta = 0°C to 70°C)
V
SS
000V
V
IH
2.4 — 6.5 V
V
IL
–1.0 — 0.8 V
Input Low Voltage
Parameter Symbol Unit
C
IN1
pFInput Capacitance (A0 - A10)
Typ. Max.
—64
(Ta = 25°C, f = 1 MHz)
C
IN2
pFInput Capacitance (RAS, CAS, WE)—73
C
IN3
pFInput Capacitance (CAS8)—13
C
IN4
pFInput Capacitance (D8) — 12
C
OUT
pFOutput Capacitance (Q8) — 13
C
DQ
pFI/O Capacitance (DQ0 - DQ7) — 19
Note : Capacitance measured with Boonton Meter.
MSC23409C/CL-xxDS9¡ Semiconductor
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DC Characteristics
Notes: 1. Specified values are obtained with the output open.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
4. VCC - 0.2 V ≤ VIH ≤ 6.5 V, -1.0 V ≤ VIL ≤ 0.2 V.
5. L-version.
All other pins not
Parameter
MSC23409C/CL MSC23409C/CL
Unit
Condition
MSC23409C/CL
Input Leakage Current
Note
I
LI
µA
1, 2
Min.
–90
Max.
90
Min.
–90
Max.
90
Min.
–90
Max.
90
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C)
Symbol
0 V £ V
I
£ 6.5 V;
under test = 0 V
D
OUT
disable
0 V £ V
O
£ 5.5 V
I
OH
= –5.0 mA
I
OL
= 4.2 mA
RAS, CAS cycling,
t
RC
= Min.
RAS, CAS = V
IH
RAS, CAS
≥ V
CC
–0.2 V
RAS cycling,
CAS = V
IH
,
t
RC
= Min.
RAS cycling,
CAS before RAS,
t
RC
= Min.
RAS = V
IL
,
CAS cycling,
t
PC
= Min.
t
RC
= 125 µs,
CAS before
RAS cycling
Output Leakage Current
Output High Voltage
Output Low Voltage
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Supply Current
(RAS-only Refresh)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
Average Power
I
LO
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC6
I
CC7
I
CC10
µA–10 10 –10 10 –10 10
V2.4 V
CC
2.4 V
CC
2.4 V
CC
V0 0.4 0 0.4 0 0.4
mA— 900 — 810 — 720
mA— 18 — 18 — 18
mA—9—9—9
mA— 1.8 — 1.8 — 1.8
mA— 900 — 810 — 720
mA— 900 — 810 — 720
mA— 720 — 630 — 540
mA— 2.7 — 2.7 — 2.7
1
1
1, 5
1, 2
1, 2
1, 3
4, 5
1, 2
-60DS9 -70DS9 -80DS9
MSC23409C/CL-xxDS9¡ Semiconductor
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AC Characteristics (1/2)
—
Parameter
Symbol
MSC23409C/CL MSC23409C/CL
Unit
Min. Max.
MSC23409C/CL
Random Read or Write Cycle Time
Min. Max. Min. Max.
Note
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,9,10
tRC 110 — 130 150 — ns
4, 5, 6
—Fast Page Mode Cycle Time tPC 40 — 45 50 — ns
70Access Time from RAS tRAC —60— —80ns
20Access Time from CAS tCAC —15— —20ns
35Access Time from Column Address tAA —30— —40ns
40Access Time from CAS Precharge tCPA —35— —45ns
—
Output Low Impedance Time from CAS
tCLZ 0—0 0—ns
20Output Buffer Turn-off Delay Time tOFF 0150 020ns
50Transition Time tT3503 350ns
16Refresh Period tREF —16— —16ms
128Refresh Period (L-version) tREF — 128 — — 128 ms
—RAS Precharge Time tRP 40 — 50 60 — ns
10KRAS Pulse Width tRAS 60 10K 70 80 10K ns
100KRAS Pulse Width (Fast Page Mode) tRASP 60 100K 70 80 100K ns
—RAS Hold Time tRSH 15 — 20 20 — ns
—CAS Precharge Time tCP 10 — 10 10 — ns
10KCAS Pulse Width tCAS 15 10K 20 20 10K ns
—CAS Hold Time tCSH 60 — 70 80 — ns
—CAS to RAS Precharge Time tCRP 5—5 5—ns
50RAS to CAS Delay Time tRCD 20 45 20 20 60 ns
35RAS to Column Address Delay Time tRAD 15 30 15 15 40 ns
—Row Address Set-up Time tASR 0—0 0—ns
—Row Address Hold Time tRAH 10 — 10 10 — ns
—Column Address Set-up Time tASC 0—0 0—ns
—Column Address Hold Time tCAH 15 — 15 15 — ns
—Column Address Hold Time from RAS tAR 50 — 55 60 — ns
—Column Address to RAS Lead Time tRAL 30 — 35 40 — ns
4, 5
4, 6
4
4
7
3
5
6
-60DS9 -70DS9 -80DS9
MSC23409C/CL-xxDS9¡ Semiconductor
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AC Characteristics (2/2)
Parameter
Symbol
MSC23409C/CL MSC23409C/CL
Unit
Min. Max.
MSC23409C/CL
Read Command Set-up Time
Min. Max. Min. Max.
Note
t
RCS
0—0 0 ns
8
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,9,10
——
Read Command Hold Time t
RCH
0—0 0 ns——
Read Command Hold Time referenced to RAS
t
RRH
0—0 0 ns——
Write Command Set-up Time t
WCS
0—0 0 ns——
Write Command Hold Time t
WCH
10 — 10 10 ns——
Write Command Hold Time from RAS t
WCR
45 — 50 60 ns——
Write Command Pulse Width t
WP
10 — 10 10 ns——
Write Command to RAS Lead Time t
RWL
15 — 20 20 ns——
Write Command to CAS Lead Time t
CWL
15 — 20 20 ns——
Data-in Set-up Time t
DS
0—0 0 ns——
Data-in Hold Time t
DH
15 — 15 15 ns——
Data-in Hold Time from RAS t
DHR
50 — 55 60 ns——
CAS Active Delay Time from RAS Precharge
t
RPC
5—5 5 ns——
RAS to CAS Set-up Time (CAS before RAS)t
CSR
5—5 5 ns——
RAS to CAS Hold Time (CAS before RAS)t
CHR
10 — 10 10 ns——
CAS Precharge Time (Refresh Counter Test)
t
CPT
30 — 35 40 ns——
WE to RAS Precharge Time (CAS before RAS)
t
WRP
10 — 10 10 ns——
WE Hold Time from RAS (CAS before RAS)t
WRH
10 — 10 10 ns——
RAS to WE Set-up Time (Test Mode) t
WTS
10 — 10 10 ns——
RAS to WE Hold Time (Test Mode) t
WTH
10 — 10 10 ns——
8
-60DS9 -70DS9 -80DS9
MSC23409C/CL-xxDS9¡ Semiconductor
8/13
Notes: 1. A start-up delay of 200 µs is required after power-up followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
When using the internal refresh counter, a minimum of eight CAS before RAS
initialization cycles is required.
2. AC mesurement assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times are measured between VIH and VIL.
4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD
(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD
(Max.) limit, access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD
(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD
(Max.) limit, access time is controlled by tAA.
7. tOFF (Max.) defines the time at which the output achieves an open circuit condition
and is not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, then data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operational
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
10. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
MSC23409C/CL-xxDS9¡ Semiconductor
9/13
RAS
Address
WE
DQ0-7
V
IH
V
IL
–
–
,
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
OH
V
OL
–
–
t
RC
t
RAS
t
RP
t
CSH
t
CRP
t
RCD
t
RSH
t
CRP
t
CAS
t
RAD
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
Row Column
t
AR
t
RCS
t
RCH
t
RRH
t
CAC
t
AA
t
CLZ
t
RAC
t
OFF
Open Valid Data-out
"H" or "L"
,
CAS
CAS8
Q8
Write Cycle (Early Write)
RAS
Address
WE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
"H" or "L"
,
,
,,
V
IH
V
IL
–
–
t
RC
t
RAS
t
RP
t
CSH
t
CRP
t
RCD
t
RSH
t
CRP
t
CAS
t
AR
t
RAD
t
RAL
t
RAH
t
ASR
t
ASC
t
CAH
Row Column
t
CWL
t
WCR
t
WCS
t
WCH
t
RWL
t
DHR
t
DS
t
DH
Valid Data-in
t
WP
CAS
CAS8
DQ0-7
D8
Note: Q8
= "Open"
TIMING WAVEFORM
Read Cycle
MSC23409C/CL-xxDS9¡ Semiconductor
10/13
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle (Early Write)
RAS
Address
WE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
"H" or "L"
,
V
IH
V
IL
–
–
,
,
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
t
CP
t
PC
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
AR
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
Row Column Column Column
t
WCR
t
WCS
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid Data-in Valid Data-in Valid Data-in
t
DHR
t
WP
t
CWL
t
WP
t
WP
t
CWL
t
CWL
t
RWL
CAS
CAS8
DQ0-7
D8
t
CSH
Note: Q8
= "Open"
RAS
Address
WE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
OH
V
OL
–
–
"H" or "L"
,
t
RASP
t
RP
t
CSH
t
CRP
t
RCD
t
CAS
t
CP
t
PC
t
CAS
t
CP
t
RSH
t
CAS
t
CRP
t
AR
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
ASC
t
CAH
Row Column Column Column
t
RAD
t
RCS
t
RCH
t
RCS
t
RCH
t
RCS
t
RRH
t
RCH
t
CAC
t
AA
t
RAC
t
CAC
t
AA
t
CPA
t
CAC
t
AA
t
CPA
Valid
Data-out
Valid
Data-out
Valid
Data-out
t
CLZ
t
OFF
t
CLZ
t
OFF
t
CLZ
t
OFF
CAS
CAS8
DQ0-7
Q8
MSC23409C/CL-xxDS9¡ Semiconductor
11/13
RAS-Only Refresh Cycle
RAS
Address
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
OH
V
OL
–
–
"H" or "L"
t
RC
t
RP
t
RAS
t
RPC
t
CRP
t
RAH
t
ASR
Row
Open
Note: WE
= "H" or "L"
,
t
OFF
CAS
CAS8
DQ0-7
Q8
CAS before RAS Refresh Cycle
,,
V
IH
V
IL
RAS
V
IH
V
IL
–
–
–
–
t
RP
t
RAS
"H" or "L"
V
OH
V
OL
–
–
t
RPC
V
IH
V
IL
–
–
Open
WE
t
RC
t
WRH
t
WRP
t
RPC
t
WRP
t
CP
t
CSR
t
CHR
t
OFF
Note: Address = "H" or "L"
CAS
CAS8
DQ0-7
Q8
MSC23409C/CL-xxDS9¡ Semiconductor
12/13
Hidden Refresh Read Cycle
,
,,
t
ASR
Row Column
V
IH
V
IL
RAS
Address
V
IH
V
IL
V
IH
V
IL
–
–
–
–
–
–
t
CRP
t
RC
t
ASC
t
RP
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
RAH
t
AR
t
RAL
t
CHR
t
RAS
t
WRH
t
WRP
WE V
IH
V
IL
V
IH
V
IL
–
–
–
–
"H" or "L"
Valid Data-in
t
DS
t
DH
t
RWL
t
WP
t
DHR
t
WCH
t
WCS
t
WCR
CAS
CAS8
DQ0-7
D8
Note: Q8 = "Open"
Hidden Refresh Write Cycle
,
,,
t
ASR
Row Column
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
–
–
–
–
–
–
–
–
t
CRP
t
RC
t
ASC
t
RP
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
RAH
t
AR
t
RAL
"H" or "L"
V
OH
V
OL
–
–
t
RRH
t
RCS
Valid Data-out
t
RAC
t
AA
t
OFF
t
CLZ
t
CHR
t
RAS
t
WRH
t
WRP
t
CAC
RAS
Address
WE
CAS
CAS8
DQ0-7
Q8
MSC23409C/CL-xxDS9¡ Semiconductor
13/13
CAS before RAS Refresh Counter Test Cycle
,
,
V
IH
V
IL
RAS
Address
V
IH
V
IL
V
IH
V
IL
–
–
–
–
–
–
t
RAS
t
ASC
t
CPT
t
RSH
t
CAH
t
CAS
WE V
IH
V
IL
–
–
Q8
"H" or "L"
V
OH
V
OL
–
–
,
,
Valid Data-in
t
DS
t
DH
t
WP
t
CWL
t
WCS
t
RP
V
OH
V
OL
Valid Data-out
Open
t
RAL
t
AA
t
OFF
t
CAC
t
CLZ
t
WRP
Open
t
RRH
t
WRH
t
RCS
WE V
IH
V
IL
V
IH
V
IL
–
–
–
–
–
–
t
WRP
t
RWL
t
WCH
t
RCH
t
WRH
Read Cycle
Write Cycle
t
CHR
t
CSR
Column
CAS
CAS8
DQ0-7
Q8
DQ0-7
D8
V
IH
V
IL
RAS
CAS
CAS8
V
IH
V
IL
–
–
–
–
t
RAS
"H" or "L"
V
OH
V
OL
–
–
V
IH
V
IL
–
–
Open
t
RC
t
WTH
,
t
RPC
t
WTS
t
CP
t
CSR
t
CHR
t
OFF
Note : Address = "H" or "L"
t
RP
WE
DQ0-7
Q8
WE • CAS before RAS Refresh Cycle
