BC313143A-ds-001Pn
Production Information
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This material is subject to CSR’s non-disclosure agreement
Page 1 of 108
_äìÉ`çêÉ»PJolj Product Data Sheet
Device Features _äìÉ`çêÉ»PJolj
Single Chip Bluetooth® v1.2 System
Production Information Data Sheet for
BC313143A
July 2005
! Fully qualified Bluetooth v1.2 system
! Bluetooth v1.1 and v1.2 specification
compliant
! 1.8V core, 1.8 to 3.6V I/O
! Ultra low power consumption
! Excellent compatibility with cellular
telephones
! Minimum external components
! Integrated 1.8V regulator
! Dual UART ports
! Available in VFBGA
! Built-in self-test reduces production test times
! RoHS Compliant (BC313143AXX-IRK-E4)
! Software prototyping device available
(BlueCore3-ROM Flash)
BC313143AXX
BC31A159A-ES-ITK
General Description Applications
_äìÉ`çêÉPJolj is a single chip radio and
baseband chip for Bluetooth wireless technology
2.4GHz systems. It is implemented in 0.18μm
CMOS technology.
BlueCore3-ROM has the same pin out as
BlueCore2-ROM (VFBGA Package) but uses up
to 40% less power.
The 4Mbit ROM is metal programmable, which
enables a eight week turn-around from approval of
firmware to production samples.
! Cellular Handsets
! Personal Digital Assistants (PDAs)
! Mice and game pads
! Digital cameras and other high volume consumer
products
A Flash based prototyping device (BlueCore3-ROM Flash)
is available for functional verification and testing of the
firmware prior to committing the image to ROM.
BlueCore3-ROM has been designed to reduce the number
of external components required, which ensures
production costs are minimised.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth specification
v1.2.
BlueCore3-ROM System Architecture
Contents
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Production Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
Contents
Status Information ................................................................................................................................................7
1 Key Features ..................................................................................................................................................8
2 6 x 6mm Package Information ......................................................................................................................9
2.1 BC313143AXX-IEK and BC313143AXX-IRK Pinout Diagram .............................................................. 9
2.2 Device Terminal Functions ................................................................................................................. 10
3 6.5 x 6.5mm Package Information ..............................................................................................................14
3.1 BlueCore3-ROM Flash Pinout Diagram ..............................................................................................14
3.2 Device Terminal Functions ................................................................................................................. 15
4 Electrical Characteristics............................................................................................................................19
5 Radio Characteristics..................................................................................................................................24
5.1 Temperature +20°C ............................................................................................................................ 24
5.1.1 Transmitter........................................................................................................................... 24
5.1.2 Receiver............................................................................................................................... 26
5.2 Temperature -40°C ............................................................................................................................. 28
5.2.1 Transmitter........................................................................................................................... 28
5.2.2 Receiver............................................................................................................................... 28
5.3 Temperature -30°C ............................................................................................................................. 29
5.3.1 Transmitter........................................................................................................................... 29
5.3.2 Receiver............................................................................................................................... 29
5.4 Temperature -25°C ............................................................................................................................. 30
5.4.1 Transmitter........................................................................................................................... 30
5.4.2 Receiver............................................................................................................................... 30
5.5 Temperature +85°C ............................................................................................................................ 31
5.5.1 Transmitter........................................................................................................................... 31
5.5.2 Receiver............................................................................................................................... 33
5.6 Temperature +105°C .......................................................................................................................... 34
5.6.1 Transmitter........................................................................................................................... 34
5.6.2 Receiver............................................................................................................................... 34
5.7 Power Consumption ........................................................................................................................... 35
6 Device Diagrams..........................................................................................................................................36
6.1 BlueCore3-ROM ................................................................................................................................. 36
6.2 BlueCore3-ROM Flash ....................................................................................................................... 37
7 Description of Functional Blocks...............................................................................................................38
7.1 RF Receiver........................................................................................................................................ 38
7.1.1 Low Noise Amplifier .............................................................................................................38
7.1.2 Analogue to Digital Converter .............................................................................................. 38
7.2 RF Transmitter.................................................................................................................................... 38
7.2.1 IQ Modulator ........................................................................................................................ 38
7.2.2 Power Amplifier.................................................................................................................... 38
7.2.3 Auxiliary DAC....................................................................................................................... 38
7.3 RF Synthesiser ................................................................................................................................... 38
7.4 Clock Input and Generation ................................................................................................................ 38
7.5 Baseband and Logic ........................................................................................................................... 39
7.5.1 Memory Management Unit................................................................................................... 39
7.5.2 Burst Mode Controller .......................................................................................................... 39
7.5.3 Physical Layer Hardware Engine DSP ................................................................................ 39
7.5.4 RAM..................................................................................................................................... 39
7.5.5 ROM .................................................................................................................................... 39
7.5.6 Flash (BlueCore3-ROM Flash Only) .................................................................................... 39
7.5.7 USB ..................................................................................................................................... 39
7.5.8 Synchronous Serial Interface............................................................................................... 40
7.5.9 UART................................................................................................................................... 40
7.5.10 Audio PCM Interface............................................................................................................ 40
7.6 Microcontroller .................................................................................................................................... 40
7.6.1 Programmable I/O ............................................................................................................... 40
Contents
BC313143A-ds-001Pn
Production Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
8 CSR Bluetooth Software Stacks.................................................................................................................41
8.1 BlueCore HCI Stack............................................................................................................................ 41
8.1.1 Key Features of the HCI Stack ............................................................................................ 42
8.2 BlueCore RFCOMM Stack.................................................................................................................. 44
8.2.1 Key Features of the BlueCore3-ROM RFCOMM Stack ....................................................... 44
8.3 BlueCore Virtual Machine Stack ......................................................................................................... 45
8.4 BlueCore HID Stack............................................................................................................................ 46
8.5 BCHS Software................................................................................................................................... 47
8.6 Additional Software for Other Embedded Applications ....................................................................... 47
8.7 CSR Development Systems ............................................................................................................... 47
9 Device Terminal Descriptions.....................................................................................................................48
9.1 RF Ports.............................................................................................................................................. 48
9.2 Transmitter/Receiver Inputs and Outputs ........................................................................................... 48
9.2.1 Transmitter S-Parameters.................................................................................................... 49
9.2.2 Receiver S-Parameters ....................................................................................................... 53
9.2.3 Single Ended Impedance..................................................................................................... 55
9.3 External Reference Clock Input (XTAL_IN) ........................................................................................56
9.3.1 External Mode...................................................................................................................... 56
9.3.2 XTAL_IN Impedance in External Mode................................................................................ 56
9.3.3 Clock Timing Accuracy ........................................................................................................ 57
9.3.4 Clock Start-Up Delay ........................................................................................................... 57
9.3.5 Input Frequencies and PS Key Settings .............................................................................. 58
9.4 Crystal Oscillator (XTAL_IN, XTAL_OUT) ..........................................................................................59
9.4.1 XTAL Mode.......................................................................................................................... 59
9.4.2 Load Capacitance................................................................................................................60
9.4.3 Frequency Trim.................................................................................................................... 60
9.4.4 Transconductance Driver Model .......................................................................................... 61
9.4.5 Negative Resistance Model ................................................................................................. 61
9.4.6 Crystal PS Key Settings....................................................................................................... 61
9.4.7 Crystal Oscillator Characteristics ......................................................................................... 62
9.5 UART Interface ................................................................................................................................... 65
9.5.1 UART Bypass ...................................................................................................................... 67
9.5.2 UART Configuration while RESET is Active ........................................................................ 67
9.5.3 UART Bypass Mode ............................................................................................................ 67
9.5.4 Current Consumption in UART Bypass Mode...................................................................... 67
9.6 USB Interface ..................................................................................................................................... 68
9.6.1 USB Data Connections........................................................................................................ 68
9.6.2 USB Pull-Up Resistor .......................................................................................................... 68
9.6.3 Power Supply....................................................................................................................... 68
9.6.4 Self Powered Mode ............................................................................................................. 69
9.6.5 Bus Powered Mode ............................................................................................................. 70
9.6.6 Suspend Current.................................................................................................................. 71
9.6.7 Detach and Wake_Up Signalling ......................................................................................... 71
9.6.8 USB Driver........................................................................................................................... 71
9.6.9 USB 1.1 Compliance ........................................................................................................... 72
9.6.10 USB 2.0 Compatibility .......................................................................................................... 72
9.7 Serial Peripheral Interface .................................................................................................................. 72
9.7.1 Instruction Cycle .................................................................................................................. 72
9.7.2 Writing to BlueCore3-ROM .................................................................................................. 73
9.7.3 Reading from BlueCore3-ROM............................................................................................ 73
9.7.4 Multi Slave Operation .......................................................................................................... 73
9.7.5 PCM CODEC Interface........................................................................................................ 74
9.7.6 PCM Interface Master/Slave ................................................................................................ 75
9.7.7 Long Frame Sync ................................................................................................................ 76
9.7.8 Short Frame Sync................................................................................................................76
9.7.9 Multi Slot Operation ............................................................................................................. 77
9.7.10 GCI Interface ....................................................................................................................... 77
9.7.11 Slots and Sample Formats................................................................................................... 78
9.7.12 Additional Features.............................................................................................................. 78
9.7.13 PCM Timing Information ...................................................................................................... 79
Contents
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9.7.14 PCM Slave Timing ............................................................................................................... 81
9.7.15 PCM_CLK and PCM_SYNC Generation ............................................................................. 82
9.7.16 PCM Configuration .............................................................................................................. 83
9.8 I/O Parallel Ports................................................................................................................................. 85
9.9 I2C Interface........................................................................................................................................ 86
9.10 TCXO Enable OR Function................................................................................................................. 86
9.11 RESET and RESETB ......................................................................................................................... 87
9.11.1 Pin States on Reset .............................................................................................................88
9.11.2 Status after Reset ................................................................................................................ 88
9.12 Power Supply...................................................................................................................................... 89
9.12.1 Voltage Regulator ................................................................................................................ 89
9.12.2 Sequencing.......................................................................................................................... 89
9.12.3 Sensitivity to Disturbances................................................................................................... 89
10 Application Schematic.................................................................................................................................90
10.1 6 x 6mm VFBGA 84-Ball Package...................................................................................................... 90
11 PCB Design and Assembly Considerations..............................................................................................91
11.1 VFBGA 84-Ball Package..................................................................................................................... 91
12 Package Dimensions...................................................................................................................................92
12.1 6 x 6mm VFBGA 84-Ball Package...................................................................................................... 92
12.2 6.5 x 6.5mm VFBGA 84-Ball Package................................................................................................ 93
13 Solder Profiles..............................................................................................................................................94
13.1 Example Solder Re-flow Profile for Devices with Lead-Free Solder Balls .......................................... 94
13.2 Example Solder Re-Flow Profile for Devices with Tin / Lead Solder Balls .......................................... 95
14 Product Reliability Tests.............................................................................................................................96
15 Ordering Information...................................................................................................................................97
15.1 BlueCore3-ROM ................................................................................................................................. 97
15.2 BlueCore3-ROM Flash Software Prototyping Device ......................................................................... 97
16 Tape and Reel Information..........................................................................................................................98
16.1 Tape Orientation and Dimensions ...................................................................................................... 98
16.2 Reel Information ............................................................................................................................... 100
16.3 Dry Pack Information (6 x 6mm VFBGA 84-Ball Package Only)....................................................... 101
16.4 Baking Conditions............................................................................................................................. 102
16.5 Product Information .......................................................................................................................... 102
17 Contact Information...................................................................................................................................103
18 Document References...............................................................................................................................104
Terms and Definitions ......................................................................................................................................105
Document History.............................................................................................................................................108
Contents
BC313143A-ds-001Pn
Production Information
© Cambridge Silicon Radio Ltd. 2005
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_äìÉ`çêÉ»PJolj Product Data Sheet
List of Figures
Figure 2.1: BlueCore3-ROM 6 x 6mm Packages (BC313143AXX-IEK and BC313143AXX-IRK)........................... 9
Figure 3.1: BlueCore3-ROM Flash 6.5 x 6.5mm Packages (BC31A159A-ES-ITK)............................................... 14
Figure 6.1: BlueCore3-ROM Device Diagram for 6 x 6mm VFBGA Packages ..................................................... 36
Figure 6.2: BlueCore3-ROM Flash Device Diagram for 6.5 x 6.5mm TFBGA Packages ...................................... 37
Figure 8.1: BlueCore HCI Stack............................................................................................................................ 41
Figure 8.2: BlueCore RFCOMM Stack .................................................................................................................. 44
Figure 8.3: Virtual Machine ................................................................................................................................... 45
Figure 8.4: HID Stack............................................................................................................................................ 46
Figure 9.1: Circuit TX/RX_A and TX/RX_B ........................................................................................................... 48
Figure 9.2: Circuit RF_IN ...................................................................................................................................... 48
Figure 9.3: TX_A PL35.......................................................................................................................................... 50
Figure 9.4: TX_A PL50.......................................................................................................................................... 50
Figure 9.5: TX_A PL63.......................................................................................................................................... 51
Figure 9.6: TX_B PL35.......................................................................................................................................... 51
Figure 9.7: TX_B PL50.......................................................................................................................................... 52
Figure 9.8: TX_B PL63.......................................................................................................................................... 52
Figure 9.9: RX_A Balanced................................................................................................................................... 54
Figure 9.10: RX_B Balanced................................................................................................................................. 54
Figure 9.11: RX Un-Balanced ............................................................................................................................... 55
Figure 9.12: TCXO Clock Accuracy ...................................................................................................................... 57
Figure 9.13: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 57
Figure 9.14: Crystal Driver Circuit ......................................................................................................................... 59
Figure 9.15: Crystal Equivalent Circuit .................................................................................................................. 59
Figure 9.16: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 62
Figure 9.17: Crystal Driver Transconductance vs. Driver Level Register Setting..................................................63
Figure 9.18: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 64
Figure 9.19: Universal Asynchronous Receiver .................................................................................................... 65
Figure 9.20: Break Signal...................................................................................................................................... 66
Figure 9.21: UART Bypass Architecture ............................................................................................................... 67
Figure 9.22: USB Connections for Self Powered Mode ........................................................................................ 69
Figure 9.23: USB Connections for Bus Powered Mode ........................................................................................ 70
Figure 9.24: USB_DETACH and USB_WAKE_UP Signal .................................................................................... 71
Figure 9.25: Write Operation................................................................................................................................. 73
Figure 9.26: Read Operation................................................................................................................................. 73
Figure 9.27: BlueCore3-ROM as PCM Interface Master ....................................................................................... 75
Figure 9.28: BlueCore3-ROM as PCM Interface Slave ......................................................................................... 75
Figure 9.29: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................... 76
Figure 9.30: Short Frame Sync (Shown with 16-bit Sample) ................................................................................ 76
Figure 9.31: Multi Slot Operation with Two Slots and 8-bit Companded Samples ................................................ 77
Figure 9.32: GCI Interface..................................................................................................................................... 77
Figure 9.33: 16-Bit Slot Length and Sample Formats ........................................................................................... 78
Figure 9.34: PCM Master Timing Long Frame Sync ............................................................................................. 80
Figure 9.35: PCM Master Timing Short Frame Sync............................................................................................. 80
Figure 9.36: PCM Slave Timing Long Frame Sync ............................................................................................... 81
Figure 9.37: PCM Slave Timing Short Frame Sync............................................................................................... 82
Figure 9.38: Example EEPROM Connection ........................................................................................................ 86
Contents
BC313143A-ds-001Pn
Production Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
Figure 9.39: Example TXCO Enable OR Function................................................................................................ 86
Figure 11.1: Application Circuit for Radio Characteristics Specification for 6 x 6mm VFBGA Package ................ 90
Figure 13.1: BlueCore3-ROM VFBGA Package Dimensions ................................................................................ 92
Figure 13.2: BlueCore3-ROM Flash TFBGA Package Dimensions ...................................................................... 93
Figure 14.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 94
Figure 14.2: Typical Re-flow Solder Profile ........................................................................................................... 95
Figure 17.1: Tape and Reel Orientation ................................................................................................................ 98
Figure 17.2: Tape Dimensions .............................................................................................................................. 99
Figure 17.3: Reel Dimensions............................................................................................................................. 100
Figure 17.4: Tape and Reel Packaging............................................................................................................... 101
Figure 17.5: Product Information Labels ............................................................................................................. 102
List of Tables
Table 9.1: Transmit Impedance............................................................................................................................. 49
Table 9.2: Balanced Receiver Impedance ............................................................................................................ 53
Table 9.3: Single Ended Impedance ..................................................................................................................... 55
Table 9.4: External Clock Specifications ............................................................................................................... 56
Table 9.5: PS Key Values for CDMA/3G phone TCXO Frequencies .................................................................... 58
Table 9.6: Crystal Oscillator Specification............................................................................................................. 61
Table 9.7: Possible UART Settings ....................................................................................................................... 65
Table 9.8: Standard Baud Rates ........................................................................................................................... 66
Table 9.9: USB Interface Component Values ....................................................................................................... 70
Table 9.10: Instruction Cycle for an SPI Transaction ............................................................................................ 72
Table 9.11: PCM Master Timing............................................................................................................................ 79
Table 9.12: PCM Slave Timing.............................................................................................................................. 81
Table 9.13: PSKEY_PCM_CONFIG32 Description............................................................................................... 83
Table 9.14: PSKEY_PCM_LOW_JITTER_CONFIG Description .......................................................................... 84
Table 9.15: Pin States of BlueCore3-ROM on Reset ............................................................................................ 88
Table 17.1: Reel Dimensions .............................................................................................................................. 100
Table 17.2: Diameter Dependent Dimensions .................................................................................................... 100
Status Information
BC313143A-ds-001Pn
Production Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
Status Information
The status of this Data Sheet is Production Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of
the design. Minimum and maximum values specified are only given as guidance to the final specification limits
and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-Production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not
be considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
RoHS Compliance
BlueCore4-ROM devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the
Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Paten t s and Licenses
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by
Cambridge Silicon Radio Limited or its affiliates. Bluetooth® and the Bluetooth logos are trademarks owned by
Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have
been trademarked by their respective owners.
Windows®, Windows 98™, Windows 2000™, Windows XP™ and Windows NT™ are registered trademarks of
the Microsoft Corporation.
OMAP™ is a trademark of Texas Instruments Inc.
The publication of this information does not imply that any license is granted under any patent or other rights
owned by Cambridge Silicon Radio Limited.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
CSR’s products are not authorised for use in life-support or safety-critical applications.
Key Features
BC313143A-ds-001Pn
Production Information
© Cambridge Silicon Radio Ltd. 2005
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_äìÉ`çêÉ»PJolj Product Data Sheet
1 Key Features
Radio
! Common TX/RX terminals simplifies external
matching; eliminates external antenna switch
! BIST minimises production test time. No external
trimming is required in production
! Full RF reference designs are available
! Bluetooth v1.2 specification compliant
Transmitter
! +6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
! Class 2 and Class 3 support without the need for
an external power amplifier or TX/RX switch
! Class 1 support using external power amplifier,
with RF power controlled by an internal 8-bit DAC.
Receiver
! Integrated channel filters
! Digital demodulator for improved sensitivity and
co-channel rejection
! Real time digitised RSSI available on HCI
interface
! Fast AGC for enhanced dynamic range
Synthesiser
! Fully integrated synthesizer requires no external
VCO varactor diode, resonator or loop filter
! Compatible with crystals between 8 and 32MHz (in
multiples of 250kHz) or an external clock
! Accepts 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8
and 38.4MHz TCXO frequencies for GSM and
CDMA devices with either sinusoidal or logic level
signals
Auxiliary Features
! Crystal oscillator with built-in digital trimming
! Power management includes digital shut down
and wake up commands with an integrated low
power oscillator for ultra-low Park/Sniff/Hold mode
! ‘Clock request’ output to control an external clock
source
! Device can run in low power modes from an
external 32768Hz clock signal
! Auto Baud Rate setting for different TCXO
frequencies
! On-chip linear regulator, producing 1.8V output
from 2.2 - 4.2V input
Auxiliary Features (Continued)
! Power-on-reset cell detects low supply voltage
! Arbitrary sequencing of power supplies is
permitted
! Uncommitted 8-bit ADC and 8-bit DAC are
available to application programs
Baseband and Software
! Internal programmed 4Mbit ROM for complete
system solution
! BlueCore3-ROM Flash device for software
prototyping
! 32kbyte on-chip RAM allows full speed Bluetooth
data transfer, mixed voice and data, plus full
seven slave Piconet operation
! Dedicated logic for forward error correction,
header error control, access code correlation,
demodulation, cyclic redundancy check,
encryption bit stream generation, whitening and
transmit pulse shaping. Supports all Bluetooth 1.2
features including eSCO
! Transcoders for A-law, μ-law and linear voice from
host and A-law, μ-law and CVSD voice over air
Physical Interfaces
! Synchronous serial interface up to 4M Baud for
system debugging
! UART interface with programmable Baud rate up
to 1.5M Baud with an optional bypass mode
! Full speed USB interface supports OHCI and
UHCI host interfaces. Compliant with USB v2.0
! Synchronous bi-directional serial programmable
audio interface
! Optional I2C™ compatible interface
Bluetooth Stack Running on an
Internal Microcontroller
CSR’s Bluetooth protocol stack runs on-chip in a
variety of configurations:
! Standard HCI (UART or USB)
! Fully embedded to RFCOMM
! Customer specific builds with embedded
application code
Package Options
! 84-ball VFBGA 6 x 6 x 1.0mm 0.5mm pitch
(BlueCore3-ROM)
! 84-ball TFBGA 6.5 x 6.5 x 1.2mm 0.5mm pitch
(BlueCore3-ROM Flash for software prototyping)
6 x 6mm Package Information
BC313143A-ds-001Pn
Production Information
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This material is subject to CSR’s non-disclosure agreement
Page 9 of 108
_äìÉ`çêÉ»PJolj Product Data Sheet
2 6 x 6mm Package Information
2.1 BC313143AXX-IEK and BC313143AXX-IRK Pinout Diagram
Orientation from top of device
A
B
C
D
E
F
G
H
J
K
123
4
5
6
7
8910
A1 A2 A3
A
4
A
5
A
6
A
7
A
8A9 A10
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
D1 D2 D3 D8 D9 D10
E1 E2 E3 E8 E9 E10
F1 F2 F3 F8 F9 F10
G1 G2 G3 G8 G9 G10
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
Figure 2.1: BlueCore3-ROM 6 x 6mm Packages (BC313143AXX-IEK and BC313143AXX-IRK)
6 x 6mm Package Information
BC313143A-ds-001Pn
Production Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
2.2 Device Terminal Functions
Radio Ball Pad Type Description
RF_IN D1 Analogue Single-ended receiver input
PIO[0]/RXEN B1
Bi-directional with
programmable strength
internal pull-up/down
Control output for external TX/RX switch (if
fitted)
PIO[1]/TXEN B2
Bi-directional with
programmable strength
internal pull-up/down
Control output for external PA (if fitted)
TX_A F1 Analogue Transmitter output/switched receiver input
TX_B E1 Analogue Complement of TX_A
AUX_DAC D3 Analogue Voltage DAC output
Synthesiser and
Oscillator Ball Pad Type Description
XTAL_IN K3 Analogue For crystal or external clock input
XTAL_OUT J3 Analogue Drive for crystal
LOOP_FILTER H2 No pad Do not connect
PCM Interface Ball Pad Type Description
PCM_OUT G8
CMOS output, tri-state with
weak internal pull-down Synchronous data output
PCM_IN G9
CMOS input, with weak
internal pull-down Synchronous data input
PCM_SYNC G10
Bi-directional with weak
internal pull-down Synchronous data sync
PCM_CLK H10
Bi-directional with weak
internal pull-down Synchronous data clock
USB and UART Ball Pad Type Description
UART_TX J10
CMOS output, tri-state with
weak internal pull-up UART data output active high
UART_RX H9
CMOS input with weak
internal pull-down UART data input active high
UART_RTS H7
CMOS output, tri-state with
weak internal pull-up UART request to send active low
UART_CTS H8
CMOS input with weak
internal pull-down UART clear to send active low
USB_DP J8 Bi-directional USB data plus with selectable internal
1.5kΩ pull-up resistor
USB_DN K8 Bi-directional USB data minus
6 x 6mm Package Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
Test and Debug Ball Pad Type Description
RESET C7
CMOS input with weak
internal pull-down
Reset if high. Input debounced, so must be
high for >5ms to cause a reset
RESET_B D8
CMOS input with weak
internal pull-up
Reset if low. Input debounced, so must be
low for >5ms to cause a reset
SPI_CSB C9
CMOS input with weak
internal pull-up
Chip select for Serial Peripheral Interface,
active low
SPI_CLK C10
CMOS input with weak
internal-pull-down Serial Peripheral Interface clock
SPI_MOSI C8
CMOS input with weak
internal pull-down Serial Peripheral Interface data input
SPI_MISO B9
CMOS output, tri-state with
weak internal pull-down Serial Peripheral Interface data output
TEST_EN C6
CMOS input with strong
internal pull-down For test purposes only (leave unconnected)
FLASH_EN B8 No pad Pull high to VDD_MEM for compatibility with
flash devices
6 x 6mm Package Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
PIO Port Ball Pad Type Description
PIO[2] B3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[3] B4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[4] E8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[5] F8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[6] F10
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[7] F9
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[8] C5
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[9] C3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[10] C4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[11] E3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
AIO[0] H4 Bi-directional Programmable input/output line
AIO[1] H5 Bi-directional Programmable input/output line
AIO[2] J5 Bi-directional Programmable input/output line
6 x 6mm Package Information
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Power Supplies and
Control Ball Pad Type Description
VREG_IN K6 Regulator Input Linear regulator voltage input(1)
VREG_EN K5 CMOS input
High or not connected to enable regulator.
VSS to disable regulator(1)
VDD_USB K9 VDD Positive supply for UART/USB and AIO ports
VDD_PIO A3 VDD Positive supply for PIO and AUX DAC(2)
VDD_PADS D10 VDD Positive supply for all other digital
input/output ports(3)
VDD_PRG G3 VDD Positive supply for battery backed memory
VDD_MEM
A6,A7,
A9, H6,
J6, K7
VDD Not connected on ROM device
VDD_CORE E10 VDD Positive supply for internal digital circuitry
VDD_RADIO C1, C2 VDD Positive supply for RF circuitry
VDD_VCO H1 VDD Positive supply for VCO and synthesiser
circuitry
VDD_ANA K4 VDD/Regulator output
Positive supply for analogue circuitry and
1.8V regulated output
VSS_PADS
A1, A2,
D9, J9,
K10
VSS Ground connections for input/output
VSS_MEM
A10, B5,
B7, B10,
J7
VSS Ground connections for program memory
and AIO ports
VSS_CORE E9 VSS Ground connection for internal digital
circuitry
VSS_RADIO D2, E2,
F2 VSS Ground connections for RF circuitry
VSS_VCO G1, G2 VSS Ground connections for VCO and
synthesiser
VSS_ANA J2, J4,
K2 VSS Ground connections for analogue circuitry
VSS F3 VSS Ground connection for internal package
shield
Ball Description
Unconnected
Terminals A4, A5, A8, B6, H3, J1, K1 Leave unconnected
Notes:
(1) To enable the regulator the VREG_EN pin needs to be either pulled high or left unconnected. This
keeps compatibility with BlueCore2-ROM as the corresponding pin on BlueCore2-ROM was designated
as a not connect pin. In this situation the BlueCore3-ROM regulator is permanently on replicating the
BlueCore2-ROM that has no regulator enable pin.
(2) Positive supply for PIO[3:0] and PIO[11:8]
(3) Positive supply for SPI/PCM ports and PIO[7:4]
6.5 x 6.5mm Package Information
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_äìÉ`çêÉ»PJolj Product Data Sheet
3 6.5 x 6.5mm Package Information
3.1 BlueCore3-ROM Flash Pinout Diagram
Orientation from top of device
A
B
C
D
E
F
G
H
J
K
123
4
5
6
7
8910
A1 A2 A3
A
4
A
5
A
6
A
7
A
8A9 A10
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
D1 D2 D3 D8 D9 D10
E1 E2 E3 E8 E9 E10
F1 F2 F3 F8 F9 F10
G1 G2 G3 G8 G9 G10
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
Figure 3.1: BlueCore3-ROM Flash 6.5 x 6.5mm Packages (BC31A159A-ES-ITK)
6.5 x 6.5mm Package Information
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3.2 Device Terminal Functions
Radio Ball Pad Type Description
RF_IN D1 Analogue Single-ended receiver input
PIO[0]/RXEN B1
Bi-directional with
programmable strength
internal pull-up/down
Control output for external TX/RX switch (if
fitted)
PIO[1]/TXEN B2
Bi-directional with
programmable strength
internal pull-up/down
Control output for external PA (if fitted)
TX_A F1 Analogue Transmitter output/switched receiver input
TX_B E1 Analogue Complement of TX_A
AUX_DAC D3 Analogue Voltage DAC output
Synthesiser and
Oscillator Ball Pad Type Description
XTAL_IN K3 Analogue For crystal or external clock input
XTAL_OUT J3 Analogue Drive for crystal
LOOP_FILTER H2 No pad Do not connect
PCM Interface Ball Pad Type Description
PCM_OUT G8
CMOS output, tri-state with
weak internal pull-down Synchronous data output
PCM_IN G9
CMOS input, with weak
internal pull-down Synchronous data input
PCM_SYNC G10
Bi-directional with weak
internal pull-down Synchronous data sync
PCM_CLK H10
Bi-directional with weak
internal pull-down Synchronous data clock
USB and UART Ball Pad Type Description
UART_TX J10
CMOS output, tri-state with
weak internal pull-up UART data output active high
UART_RX H9
CMOS input with weak
internal pull-down UART data input active high
UART_RTS H7
CMOS output, tri-state with
weak internal pull-up UART request to send active low
UART_CTS H8
CMOS input with weak
internal pull-down UART clear to send active low
USB_DP J8 Bi-directional USB data plus with selectable internal
1.5kΩ pull-up resistor
USB_DN K8 Bi-directional USB data minus
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Test and Debug Ball Pad Type Description
RESET C7
CMOS input with weak
internal pull-down
Reset if high. Input debounced, so must be
high for >5ms to cause a reset
RESET_B D8
CMOS input with weak
internal pull-up
Reset if low. Input debounced, so must be
low for >5ms to cause a reset
SPI_CSB C9
CMOS input with weak
internal pull-up
Chip select for Serial Peripheral Interface,
active low
SPI_CLK C10
CMOS input with weak
internal-pull-down Serial Peripheral Interface clock
SPI_MOSI C8
CMOS input with weak
internal pull-down Serial Peripheral Interface data input
SPI_MISO B9
CMOS output, tri-state with
weak internal pull-down Serial Peripheral Interface data output
TEST_EN C6
CMOS input with strong
internal pull-down For test purposes only (leave unconnected)
FLASH_EN B8 No pad Pull high to VDD_MEM for compatibility with
flash devices
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PIO Port Ball Pad Type Description
PIO[2] B3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[3] B4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[4] E8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[5] F8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[6] F10
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[7] F9
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[8] C5
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[9] C3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[10] C4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[11] E3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
AIO[0] H4 Bi-directional Programmable input/output line
AIO[1] H5 Bi-directional Programmable input/output line
AIO[2] J5 Bi-directional Programmable input/output line
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Power Supplies and
Control Ball Pad Type Description
VREG_IN K6 Regulator Input Linear regulator voltage input
VREG_EN K5 CMOS input
This pin must be pulled high externally to
enable the device(1)
VDD_USB K9 VDD Positive supply for UART/USB and AIO ports
VDD_PIO A3 VDD Positive supply for PIO and AUX DAC(2)
VDD_PADS D10 VDD Positive supply for all other digital
input/output ports(3)
VDD_PRG G3 VDD Positive supply for battery backed memory
VDD_MEM
A6,A7,
A9, H6,
J6, K7
VDD Not connected on ROM device
VDD_CORE E10 VDD Positive supply for internal digital circuitry
VDD_RADIO C1, C2 VDD Positive supply for RF circuitry
VDD_VCO H1 VDD Positive supply for VCO and synthesiser
circuitry
VDD_ANA K4 VDD/Regulator output
Positive supply for analogue circuitry and
1.8V regulated output
VSS_PADS
A1, A2,
D9, J9,
K10
VSS Ground connections for input/output
VSS_MEM
A10, B5,
B7, B10,
J7
VSS Ground connections for program memory
and AIO ports
VSS_CORE E9 VSS Ground connection for internal digital
circuitry
VSS_RADIO D2, E2,
F2 VSS Ground connections for RF circuitry
VSS_VCO G1, G2 VSS Ground connections for VCO and
synthesiser
VSS_ANA J2, J4,
K2 VSS Ground connections for analogue circuitry
VSS F3 VSS Ground connection for internal package
shield
Ball Description
Unconnected
Terminals A4, A5, A8, B6, H3, J1, K1 Leave unconnected
Notes:
(1) If BlueCore3-ROM Flash is being used as a development part to replicate BlueCore3-ROM functionality
then VREG_EN must be pulled high externally to replicate the ROM devices functionality. If VREG_EN
is not being used then connect pin VREG_EN to VREG_IN.
(2) Positive supply for PIO[3:0] and PIO[11:8]
(3) Positive supply for SPI/PCM ports and PIO[7:4]
Electrical Characteristics
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4 Electrical Characteristics
Absolute Maximum Ratings
Rating Minimum Maximum
Storage Temperature -40°C 150°C
Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,
VDD_CORE, VDD_MEM, VDD_PRG -0.40V 2.20V
Supply Voltage: VDD_PADS, VDD_PIO, VDD_USB -0.40V 3.70V
Supply Voltage: VREG_IN -0.40V 5.60V
Other Terminal Voltages VSS-0.4V VDD+0.4V
Recommended Operating Conditions
Operating Condition Minimum Maximum
Operating Temperature Range -40°C 105°C
Guaranteed RF performance range -40°C 105°C
Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,
VDD_CORE, VDD_MEM, VDD_PRG 1.70V 1.90V
Supply Voltage: VDD_PADS, VDD_PIO, VDD_USB 1.70V 3.60V
Supply Voltage: VREG_IN 2.20V 4.20V(1)
Note:
(1) The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is
not guaranteed above 4.20V.
Electrical Characteristics
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Input/Output Terminal Charac teris tic s
Linear Regulator Minimum Typical Maximum Unit
Normal Operation
Output Voltage (Iload = 70mA / Vreg_IN = 3.0V) 1.70 1.78 1.85 V
Temperature Coefficient -250 - 250 ppm/C
Output Noise(1)(2) - - 1 mV rms
Load Regulation (Iload < 100 mA) - - 50 mV/A
Settling Time(1)(3) - - 50
μs
Maximum Output Current 70 - - mA
Minimum Load Current 5 - - μA
Input Voltage - - 4.2(6) V
Dropout Voltage (Iload = 70 mA) - - 350 mV
Quiescent Current (excluding Ioad, Iload < 1mA) 25 35 50 μA
Low Power Mode(4)
Quiescent Current (excluding Ioad, Iload < 100μA) 4 7 10
μA
Disabled Mode(5)
Quiescent Current 1.5 2.5 3.5 μA
Notes:
(1) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors
(2) Frequency range 100Hz to 100kHz
(3) 1mA to 70mA pulsed load
(4) Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode
(5) Regulator is disabled when VREG_EN is pulled low. It is also disabled when VREG_IN is either open
circuit or driven to the same voltage as VDD_ANA.
(6) Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to
damage the rest of BlueCore3, but output regulation and other specifications are no longer guaranteed
at input voltages in excess of 4.2V.
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Digital Terminals Minimum Typical Maximum Unit
Input Voltage Levels
-0.4 - 0.8 V
VIL input logic level low (VDD=3.0V)
(VDD=1.8V) -0.4 - 0.4 V
VIH input logic level high 0.7VDD - VDD+0.4 V
Output Voltage Levels
VOL output logic level low, (lO = 4.0mA),
VDD=3.0V - - 0.2 V
VOL output logic level low, (lO = 4.0mA),
VDD=1.8V - - 0.4 V
VOH output logic level high, (lO = -4.0mA),
VDD=3.0V VDD-0.2 - - V
VOH output logic level high, (lO = -4.0mA),
VDD=1.8V VDD-0.4 - - V
Input and Tri-State Current with:
Strong pull-up -100 -20 -10 μA
Strong pull-down 10 20 100 μA
Weak pull-up -5 -1 -0.5 μA
Weak pull-down 0.5 1 5 μA
I/O pad leakage current -1 0 1 μA
CI Input Capacitance 1.0 - 5.0 pF
USB Terminals Minimum Typical Maximum Unit
Input threshold
VIL input logic level low - - 0.3VDD_USB V
VIH input logic level high 0.57VDD_USB - - V
Input leakage current
VSS_USB< VIN< VDD_USB(1) -1 - 1
μA
CI Input capacitance 2.5 - 10.0 pF
Output Voltage levels
To correctly terminated USB Cable
VOL output logic level low 0.0 - 0.2 V
VOH output logic level high 2.8 - VDD_USB V
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Auxiliary ADC Minimum Typical Maximum Unit
Resolution - - 8 Bits
Input voltage range
(LSB size = VDD_ANA/255) 0 - VDD_ANA V
Accuracy INL -1 - 1 LSB
(Guaranteed monotonic) DNL 0 - 1 LSB
Offset -1 - 1 LSB
Gain Error -0.8 - 0.8 %
Input Bandwidth - 100 - kHz
Conversion time - 2.5 - μs
Sample rate(2) - - 700 Samples/s
Input/Output Terminal Characteristics (Continued)
Auxiliary DAC Minimum Typical Maximum Unit
Resolution - - 8 Bits
Average output step size(2) 12.5 14.2 16.5 mV
Output Voltage Monotonic(2)
Voltage range (IO=0mA) VSS_PIO - VDD_PIO V
Current range -10.0 - +0.1 mA
Minimum output voltage (IO=100μA) 0.0 - 0.2 V
Maximum output voltage (IO=10mA) VDD_PIO-0.3 - VDD_PIO V
High Impedance leakage current -1 - 1 μA
Offset -120 - 120 mV
Integral non-linearity(3) -1.5 - 1.5 LSB
Starting time (50pF load) - - 10 μs
Settling time (50pF load) - - 5 μs
Crystal Oscillator Minimum Typical Maximum Unit
Crystal frequency (4) 8.0 - 32.0 MHz
Digital trim range (5) 5.0 6.2 8.0 pF
Trim step size (5) - 0.1 - pF
Transconductance 2.0 - - mS
Negative resistance(6) 870 1500 2400
Ω
External Clock
Input frequency(7) 8.0 - 40.0 MHz
Clock input level(8) 0.4 - VDD_ANA V pk-pk
Allowable jitter - - 15 ps rms
XTAL_IN input impedance - ≥10 - kΩ
XTAL_IN input capacitance - ≤4 - pF
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Power-on reset Minimum Typical Maximum Unit
VDD_CORE falling threshold 1.40 1.50 1.60 V
VDD_CORE rising threshold 1.50 1.60 1.70 V
Hysteresis 0.05 0.10 0.15 V
Notes:
VDD_CORE, VDD_RADIO, VDD_VCO, VDD_ANA, VDD_BAL and VDD_MEM are at 1.8V unless shown
otherwise
VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise
The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative
(1) Internal USB pull-up disabled
(2) Access of ADC is through VM function and therefore sample rate given is achieved as part of this
function
(3) Specified for an output voltage between 0.2V and VDD_PIO -0.2V
(4) Integer multiple of 250kHz
(5) The difference between the internal capacitance at minimum and maximum settings of the internal
digital trim
(6) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF
(7) Clock input can be any frequency between 8 and 40MHz in steps of 250kHz + CDMA/3G TCXO
frequencies of 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz
(8) Clock input can either be sinusoidal or square wave if the peaks of the signal are below VSS_ANA or
above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN
Radio Characteristics
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5 Radio Characteristics
Important Notes
BlueCore3-ROM meets the Bluetooth specification v1.2 when used in a suitable application circuit between
-40°C and +105°C.
Tx output is guaranteed to be unconditionally stable over the guaranteed temperature range.
The radio characteristics for BlueCore3-ROM Flash are not stated as this device is for software prototyping
only.
5.1 Temperature +20°C
5.1.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = +20°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1)(2) - 6.0 - -6 to +4(3) dBm
Variation in RF power over temperature range with
compensation enabled (±)(4) - 0.5 - - dB
Variation in RF power over temperature range with
compensation disabled (±)(4) - 3 - - dB
RF power control range - 35 - ≥16 dB
RF power range control resolution(5) - 0.5 - - dB
20dB bandwidth for modulated carrier - 790 - ≤1000 kHz
Adjacent channel transmit power F=F0 ± 2MHz(6)(7) - -35 - ≤-20 dBm
Adjacent channel transmit power F=F0 ± 3MHz(6)(7) - -45 - ≤-40 dBm
Adjacent channel transmit power F=F0 > ±3MHz(6)(7) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 135 - 115 kHz
Δf2avg / Δf1avg - 0.9 - ≥0.80 -
Initial carrier frequency tolerance - 10 - ±75 kHz
Drift Rate - 8 - ≤20 kHz/50μs
Drift (single slot packet) - 7 - ≤25 kHz
Drift (five slot packet) - 8 - ≤40 kHz
2nd Harmonic Content - -55 - ≤30 dBm
3rd Harmonic Content - -60 - ≤30 dBm
Notes:
(1) BlueCore3-ROM firmware maintains the transmit power within the Bluetooth specification v1.2 limits
(2) Measurement made using a PSKEY_LC_MAX_TX_POWER setting corresponds to a
PSKEY_LC_POWER_TABLE power table entry of 63
(3) Class 2 RF transmit power range, Bluetooth specification v1.2
(4) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control
(5) Resolution guaranteed over the range -5dB to -25dB relative to maximum power for Tx Level >20.
(6) Measured at F0 = 2441MHz
Radio Characteristics
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(7) Up to three exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore3-ROM is guaranteed
to meet the ACP performance as specified by the Bluetooth specification v1.2.
Radio Characteristics VDD = 1.8V Temperature = +20°C (Continued)
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.869 – 0.894(1) - -134 - GSM 850
0.869 – 0.894(2) - -133 - CDMA 850
0.925 – 0.960(1) - -136 - GSM 900
1.570 – 1.580(3) - -140 - GPS
1.805 – 1.880(1) - -141 - GSM 1800 / DCS 1800
1.930 – 1.990(4) - -135 - PCS 1900
1.930 – 1.990(1) - -135 - GSM 1900
1.930 – 1.990(1) - -134 - CDMA 1900
2.110 – 2.170(2) - -131 - W-CDMA 2000
Emitted power in
cellular bands
measured at chip
terminals
Output power
≤4dBm
2.110 – 2.170(5) - -135 - W-CDMA 2000
dBm
Notes:
(1) Integrated in 200kHz bandwidth.
(2) Integrated in 1.2MHz bandwidth.
(3) Integrated in 1MHz bandwidth.
(4) Integrated in 30kHz bandwidth.
(5) Integrated in 5MHz bandwidth.
Radio Characteristics
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5.1.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = +20°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -84 -
2.441 - -85 -
Sensitivity at 0.1% BER for all
packet types
2.480 - -83 -
≤-70 dBm
Maximum received signal at 0.1% BER - 3 - ≥-20 dBm
Frequency
(MHz) Min Typ Max Bluetooth
Specification Unit
30 – 2000 - TBA - -10
2000 – 2399 - TBA - -27
2498 – 3000 - TBA - -27
Continuous power required to
block Bluetooth reception (for
sensitivity of -67dBm with 0.1%
BER) measured at chip
terminals 3000 –12750 - TBA - -10
dBm
C/I co-channel - 6 - ≤11 dB
Adjacent channel selectivity C/I F = F0 + 1MHz(1)(2) - -4 - ≤0 dB
Adjacent channel selectivity C/I F = F0 - 1MHz(1)(2) - -4 - ≤0 dB
Adjacent channel selectivity C/I F = F0 + 2MHz(1)(2) - -38 - ≤-30 dB
Adjacent channel selectivity C/I F = F0 - 2MHz(1)(2) - -23 - ≤-20 dB
Adjacent channel selectivity C/I F ≥ F0 + 3MHz(1)(2) - -45 - ≤-40 dB
Adjacent channel selectivity C/I F ≤ F0 - 5MHz(1)(2) - -45 - ≤-40 dB
Adjacent channel selectivity C/I F = FImage(1)(2) - -22 - ≤-9 dB
Maximum level of intermodulation interferers(3) - -30 - ≥−39 dBm
Spurious output level(4) - -140 - - dBm/Hz
Notes:
(1) Up to five exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore3-ROM is guaranteed
to meet the C/I performance as specified by the Bluetooth specification v1.2.
(2) Measured at F0 = 2405MHz, 2441MHz, 2477MHz
(3) Measured at f1-f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test
RCV/CA/05/c. i.e. wanted signal at -64dBm
(4) Integrated in 100kHz bandwidth. Actual figure is typically below -140dBm/Hz except for peaks at
multiples of receive frequency/3.
Radio Characteristics
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Radio Characteristics VDD = 1.8V Temperature = +20°C (Continued)
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.824 – 0.849(1) - +4 - GSM 850
0.824 – 0.849 - +5 - CDMA
0.880 – 0.915 - +8 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power
in cellular bands
required to block
Bluetooth reception
(for sensitivity of
-67dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
0.824 – 0.849(1) - +3 - GSM 850
0.824 – 0.849 - +3 - CDMA
0.880 – 0.915 - +8 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power
in cellular bands
required to block
Bluetooth reception
(for sensitivity of
-72dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
Note:
(1) | 3fBlocking – fBluetooth | > 10MHz
Radio Characteristics
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5.2 Temperature -40°C
5.2.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = -40°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1) - 8 - -6 to +4(2) dBm
RF power control range - 35 - ≥16 dB
RF power range control resolution - 0.5 - - dB
20dB bandwidth for modulated carrier - 790 - ≤1000 kHz
Adjacent channel transmit power F = F0 ± 2MHz(4)(5) - -35 - ≤-20 dBm
Adjacent channel transmit power F = F0 ± 3MHz(4)(5) - -45 - ≤-40 dBm
Adjacent channel transmit power F=F0 > ±3MHz(4)(5) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 138 - 115 kHz
Δf2avg / Δf1avg - 0.9 - ≥0.80 -
Initial carrier frequency tolerance - 10 - ±75 kHz
Drift Rate - 8 - ≤20 kHz/50μs
Drift (single slot packet) - 8 - ≤25 kHz
Drift (five slot packet) - 9 - ≤40 kHz
Notes:
(1) BlueCore3-ROM firmware maintains the transmit power to be within the Bluetooth specification v1.2
limits
(2) Class 2 RF transmit power range, Bluetooth specification v1.2
(3) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control
(4) Measured at F0 = 2441MHz
(5) Up to three exceptions are allowed in v1.2 of the Bluetooth specification
5.2.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = -40°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -87 -
2.441 - -88 -
Sensitivity at 0.1% BER for all packet
types
2.480 - -84 -
≤-70 dBm
Maximum received signal at 0.1% BER - 1 - ≥-20 dBm
Radio Characteristics
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5.3 Temperature -30°C
5.3.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = -30°C
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.869 – 0.894(1) - -134 - GSM 850
0.869 – 0.894(2) - -133 - CDMA 850
0.925 – 0.960(1) - -137 - GSM 900
1.570 – 1.580(3) - -140 - GPS
1.805 – 1.880(1) - -139 - GSM 1800 / DCS 1800
1.930 – 1.990(4) - -135 - PCS 1900
1.930 – 1.990(1) - -135 - GSM 1900
1.930 – 1.990(1) - -136 - CDMA 1900
2.110 – 2.170(2) - -131 - W-CDMA 2000
Emitted power in
cellular bands
measured at chip
terminals
Output power
≤4dBm
2.110 – 2.170(5) - -135 - W-CDMA 2000
dBm
Notes:
(1) Integrated in 200kHz bandwidth.
(2) Integrated in 1.2MHz bandwidth.
(3) Integrated in 1MHz bandwidth.
(4) Integrated in 30kHz bandwidth.
(5) Integrated in 5MHz bandwidth.
5.3.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = -30°C
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.824 – 0.849(1) - +3 - GSM 850
0.824 – 0.849 - +5 - CDMA
0.880 – 0.915 - +8 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power
in cellular bands
required to block
Bluetooth reception
(for sensitivity of
-67dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
0.824 – 0.849(1) - +1 - GSM 850
0.824 – 0.849 - +3 - CDMA
0.880 – 0.915 - +7 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power
in cellular bands
required to block
Bluetooth reception
(for sensitivity of
-72dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
Note:
(1) | 3fBlocking – fBluetooth | > 10MHz
Radio Characteristics
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5.4 Temperature -25°C
5.4.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = -25°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1) - 7 - -6 to +4(2) dBm
RF power control range - 35 - ≥16 dB
RF power range control resolution - 0.5 - - dB
20dB bandwidth for modulated carrier - 790 - ≤1000 kHz
Adjacent channel transmit power F=F0 ±2MHz(4)(5) - -35 - ≤-20 dBm
Adjacent channel transmit power F=F0 ±3MHz(4)(5) - -45 - ≤-40 dBm
Adjacent channel transmit power F=F0 > ±3MHz(4)(5) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 138 - 115 kHz
Δf2avg / Δf1avg - 0.9 - ≥0.80 -
Initial carrier frequency tolerance - 10 - ±75 kHz
Drift Rate - 8 - ≤20 kHz/50μs
Drift (single slot packet) - 8 - ≤25 kHz
Drift (five slot packet) - 9 - ≤40 kHz
Notes:
(1) BlueCore3-ROM firmware maintains the transmit power to be within the Bluetooth specification v1.2
limits
(2) Class 2 RF transmit power range, Bluetooth specification v1.2
(3) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control
(4) Measured at F0 = 2441MHz
(5) Up to three exceptions are allowed in v1.2 of the Bluetooth specification
5.4.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = -25°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -86 -
2.441 - -87 -
Sensitivity at 0.1% BER for all packet
types
2.480 - -84 -
≤-70 dBm
Maximum received signal at 0.1% BER - 1 - ≥-20 dBm
Radio Characteristics
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5.5 Temperature +85°C
5.5.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = +85°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1) - 3 - -6 to +4(2) dBm
RF power control range - 35 - ≥16 dB
RF power range control resolution - 0.5 - - dB
20dB bandwidth for modulated carrier - 790 - ≤1000 kHz
Adjacent channel transmit power F=F0 ±2MHz(4)(5) - -40 - ≤-20 dBm
Adjacent channel transmit power F=F0 ±3MHz(4)(5) - -50 - ≤-40 dBm
Adjacent channel transmit power F=F0 > ±3MHz(4)(5) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 134 - 115 kHz
Δf2avg / Δf1avg - 0.9 - ≥0.80 -
Initial carrier frequency tolerance - 10 - ±75 kHz
Drift Rate - 8 - ≤20 kHz/50μs
Drift (single slot packet) - 9 - ≤25 kHz
Drift (five slot packet) - 10 - ≤40 kHz
Notes:
(1) BlueCore3-ROM firmware maintains the transmit power to be within the Bluetooth specification v1.2
limits
(2) Class 2 RF transmit power range, Bluetooth specification v1.2
(3) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control
(4) Measured at F0 = 2441MHz
(5) Up to three exceptions are allowed in v1.2 of the Bluetooth specification
Radio Characteristics
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Radio Characteristics VDD = 1.8V Temperature = +85°C (Continued)
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.869 – 0.894(1) - -134 - GSM 850
0.869 – 0.894(2) - -133 - CDMA 850
0.925 – 0.960(1) - -136 - GSM 900
1.570 – 1.580(3) - -140 - GPS
1.805 – 1.880(1) - -142 - GSM 1800 / DCS 1800
1.930 – 1.990(4) - -135 - PCS 1900
1.930 – 1.990(1) - -135 - GSM 1900
1.930 – 1.990(1) - -135 - CDMA 1900
2.110 – 2.170(2) - -131 - W-CDMA 2000
Emitted power in
cellular bands
measured at chip
terminals
Output power
≤4dBm
2.110 – 2.170(5) - -135 - W-CDMA 2000
dBm
Notes:
(1) Integrated in 200kHz bandwidth.
(2) Integrated in 1.2MHz bandwidth.
(3) Integrated in 1MHz bandwidth.
(4) Integrated in 30kHz bandwidth.
(5) Integrated in 5MHz bandwidth.
Radio Characteristics
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5.5.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = +85°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -82 -
2.441 - -83 -
Sensitivity at 0.1% BER for all packet
types
2.480 - -81 -
≤-70 dBm
Maximum received signal at 0.1% BER - 5 - ≥-20 dBm
Radio Characteristics VDD = 1.8V Temperature = +85°C
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.824 – 0.849(1) - +5 - GSM 850
0.824 – 0.849 - +6 - CDMA
0.880 – 0.915 - +8 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power in
cellular bands
required to block
Bluetooth reception
(for sensitivity of
-67dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
0.824 – 0.849(1) - >+6 - GSM 850
0.824 – 0.849 - +4 - CDMA
0.880 – 0.915 - +6 - GSM 900
1.710 – 1.785 - >+5 - GSM 1800 / DCS 1800
1.850 – 1.910 - >+3 - GSM 1900 / PCS 1900
1.850 – 1.910 - >+3 - CDMA 1900
Continuous power in
cellular bands
required to block
Bluetooth reception
(for sensitivity of
-72dBm with 0.1%
BER) measured at
chip terminals
1.920 – 1.980 - >+4 - W-CDMA 2000
dBm
Note:
(1) | 3fBlocking – fBluetooth | > 10MHz
Radio Characteristics
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5.6 Temperature +105°C
5.6.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = +105°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1) - 1.5 - -6 to +4(2) dBm
RF power control range - 35 - ≥16 dB
RF power range control resolution - 0.5 - - dB
20dB bandwidth for modulated carrier - 810 - ≤1000 kHz
Adjacent channel transmit power F=F0 ±2MHz(4)(5) - -45 - ≤-20 dBm
Adjacent channel transmit power F=F0 ±3MHz(4)(5) - -50 - ≤-40 dBm
Adjacent channel transmit power F=F0 > ±3MHz(4)(5) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 130 - 115 kHz
Δf2avg / Δf1avg - 0.9 - ≥0.80 -
Initial carrier frequency tolerance - 10 - ±75 kHz
Drift Rate - 9 - ≤20 kHz/50μs
Drift (single slot packet) - 12 - ≤25 kHz
Drift (five slot packet) - 14 - ≤40 kHz
Notes:
(1) BlueCore3-ROM firmware maintains the transmit power to be within the Bluetooth specification v1.2
limits
(2) Class 2 RF transmit power range, Bluetooth specification v1.2
(3) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control
(4) Measured at F0 = 2441MHz
(5) Up to three exceptions are allowed in v1.2 of the Bluetooth specification
5.6.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = +105°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -81 -78
2.441 - -81 -78
Sensitivity at 0.1% BER for all packet
types
2.480 - -80 -77
≤-70 dBm
Maximum received signal at 0.1% BER - 5 - ≥-20 dBm
Radio Characteristics
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5.7 Power Consumption
Operation Mode Connection
Type UART Rate
(kbps) Average Peak Unit
Page scan - 115.2 0.36 38.30 mA
Inquiry & page scan - 115.2 0.66 38.67 mA
ACL data transfer No traffic Master 115.2 6.36 14.43 mA
ACL data transfer With file transfer Master 115.2 11.66 36.84 mA
ACL data transfer No traffic Slave 115.2 13.68 19.23 mA
ACL data transfer With file transfer Slave 115.2 16.99 35.70 mA
ACL data transfer 40ms sniff Master 34.4 1.50 22.05 mA
ACL data transfer 1.28s sniff Master 34.4 0.19 20.59 mA
SCO connection HV1 Master 34.4 33.80 35.70 mA
SCO connection HV3 Master 34.4 17.17 25.29 mA
SCO connection HV3 30ms sniff Master 34.4 16.81 25.31 mA
ACL data transfer 40ms sniff Slave 34.4 1.45 17.79 mA
ACL data transfer 1.28s sniff Slave 34.4 0.24 28.00 mA
SCO connection HV1 Slave 34.4 33.82 35.73 mA
SCO connection HV3 Slave 34.4 20.79 29.00 mA
SCO connection HV3 30ms sniff Slave 34.4 16.73 26.06 mA
Parked 1.28s beacon Slave 34.4 0.18 26.26 mA
Standby Host connection - 34.4 0.03 4.62 mA
Reset (RESETB low) - - 42 TBA µA
Note:
Firmware used: 17.11.
Device Diagrams
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6 Device Diagrams
6.1 BlueCore3-ROM
Clock
Generation
Baseband and Logic
RAM
Memory
Mapped
Control
Status
Physical
Layer
Hardware
Engine
Burst
Mode
Controller
Microcontroller
RISC
Microcontroller
Interrupt
Controller
Event
Timer
DAC
IQ MOD
ROM
Memory
Management
Unit
TX_A PA
AUX_DAC
PIO[1]/TXEN
AUX
DAC
RF_IN
PIO[0]/RXEN
RF Transmitter
XTAL_OUT
XTAL_IN
Fref
-45 +45
RF Synthesiser
RF
Synthesiser
/N/N+1
Loop
Filter
Tune
VREG_IN
VDD_ANA
VREG
In Out
VDD_CORE
VSS_CORE
TEST_EN
VDD_PADS
RESET
RESETB
VDD_PIO
VDD_USB
PIO[2]
AIO[0]
AIO[1]
AIO[2]
VSS_ANA
VSS_VCO
VSS_RADIO
VSS
VSS_MEM
VDD_MEM
IQ DEMOD
ADC
Demodulator
RF Receiver
RSSI
LNA
USB USB_DP
USB_DN
Synchronous
Serial
Interface
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
UART_TX
UART_RX
UART_RTS
UART_CTS
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
UART
Audio PCM
Interface
Programmable I/O
AIO
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
PIO[11]
VDD_PRG
LOOP_FILTER(1)
VDD_VCO
TX_B
VDD_RADIO
VREG_EN
En
VSS_PADS
FLASH_EN
Note:
(1) Not connected internally
Figure 6.1: BlueCore3-ROM Device Diagram for 6 x 6mm VFBGA Packages
Device Diagrams
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6.2 BlueCore3-ROM Flash
Clock
Generation
Baseband and Logic
RAM
Memory
Mapped
Control
Status
Physical
Layer
Hardware
Engine
Burst
Mode
Controller
Microcontroller
RISC
Microcontroller
Interrupt
Controller
Event
Timer
DAC
IQ MOD
Flash
Memory
Management
Unit
TX_A PA
AUX_DAC
PIO[1]/TXEN
AUX
DAC
RF_IN
PIO[0]/RXEN
RF Transmitter
XTAL_OUT
XTAL_IN
Fref
-45 +45
RF Synthesiser
RF
Synthesiser
/N/N+1
Loop
Filter
Tune
VREG_IN
VDD_ANA
VREG
In Out
VDD_CORE
VSS_CORE
TEST_EN
VDD_PADS
RESET
RESETB
VDD_PIO
VDD_USB
PIO[2]
AIO[0]
AIO[1]
AIO[2]
VSS_ANA
VSS_VCO
VSS_RADIO
VSS
VSS_MEM
VDD_MEM
IQ DEMOD
ADC
Demodulator
RF Receiver
RSSI
LNA
USB USB_DP
USB_DN
Synchronous
Serial
Interface
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
UART_TX
UART_RX
UART_RTS
UART_CTS
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
UART
Audio PCM
Interface
Programmable I/O
AIO
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
PIO[11]
VDD_PRG
LOOP_FILTER(1)
VDD_VCO
TX_B
VDD_RADIO
VREG_EN(1)
VSS_PADS
FLASH_EN(1)
Note:
(1) Not connected internally
EN
Figure 6.2: BlueCore3-ROM Flash Device Diagram for 6.5 x 6.5mm TFBGA Packages
Description of Functional Blocks
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7 Description of Functional Blocks
7.1 RF Receiver
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input
allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband
Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a
digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent
performance in the presence of noise allows BlueCore3-ROM to exceed the Bluetooth requirements for
co-channel and adjacent channel rejection.
7.1.1 Low Noise Amplifier
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for
Class 1 Bluetooth operation and differential mode is used for Class 2 operation.
7.1.2 Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC
samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is
changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.
7.2 RF Transmitter
7.2.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot which
results in a controlled modulation index. A digital baseband transmit filter provides the required spectral shaping.
7.2.2 Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore3-ROM to be used
in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control allows a simple
implementation for Class 1 with an external RF PA.
7.2.3 Auxiliary DAC
An 8-bit voltage Auxiliary DAC is provided for power control of an external PA for Class 1 operation.
7.3 RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled
Oscillator (VCO) screening can, varactor tuning diodes or LC resonators. The synthesiser is guaranteed to lock in
sufficient time across the guaranteed temperature range to meet the Bluetooth specification V1.2.
7.4 Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All
internal reference clocks are generated using a phase locked loop, which is locked to the external reference
frequency.
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7.5 Baseband and Logic
7.5.1 Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data
which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient
use of the available Random Access Memory (RAM) and is performed by hardware MMU to minimise the
overheads on the processor during data/voice transfers.
7.5.2 Burst Mode Controller
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information
previously loaded into memory-mapped registers by the software and payload data/voice taken from the
appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped
registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention
required by the processor during transmission and reception.
7.5.3 Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:
! Forward error correction
! Header error control
! Cyclic redundancy check
! Encryption
! Data whitening
! Access code correlation
! Audio transcoding
The following voice data translations and operations are performed by firmware:
! A-law/μ-law/linear voice data (from host)
! A-law/μ-law/Continuously Variable Slope Delta (CVSD) (over the air)
! Voice interpolation for lost packets
! Rate mismatches
The hardware supports all optional and mandatory features of Bluetooth v1.2 including AFH and eSCO.
7.5.4 RAM
32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to hold voice/data for each
active connection and the general purpose memory required by the Bluetooth stack.
7.5.5 ROM
4Mbits of metal programmable ROM is provided for system firmware implementation.
7.5.6 Flash (BlueCore3-ROM Flash Only)
4Mbits of internal Flash is available on the BlueCore3-ROM Flash, this is used for software prototyping before
committing code to ROM.
7.5.7 USB
This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices.
BlueCore3-ROM acts as a USB peripheral, responding to requests from a master host controller such as a PC.
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7.5.8 Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be
used for system debugging.
7.5.9 UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other
serial devices.
7.5.10 Audio PCM Interface
The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM
encoded audio data over Bluetooth.
7.6 Microcontroller
The microcontroller, interrupt controller and event timer run the Bluetooth software stack and control the radio
and host interfaces. A 16-bit Reduced Instruction Set Computer (RISC) microcontroller is used for low power
consumption and efficient use of memory.
7.6.1 Programmable I/O
BlueCore3-ROM has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are controlled
by firmware running on the device.
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8 CSR Bluetooth Software Stacks
BlueCore3-ROM is supplied with Bluetooth v1.2 compliant stack firmware which runs on the internal RISC
microcontroller.
The BlueCore3-ROM software architecture allows Bluetooth processing and the application program to be shared
in different ways between the internal RISC microcontroller and an external host processor (if any). The upper
layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
8.1 BlueCore HCI Stack
HCI
LM
LC
Internal ROM
32KB RAM Baseband
MCU
Host I/O
Radio
PCM I/O
USB
UART
Host
Figure 8.1: BlueCore HCI Stack
In this implementation the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI).
The Host processor must provide all upper layers including the applications.
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8.1.1 Key Features of the HCI Stack
New Bluetooth V1.2 Mandatory Functionality
! Adaptive Frequency Hopping (AFH)
! Faster Connections
! Flow and Flush Timeout
! LMP Improvements
! Parameter Ranges
Optional V1.2 functionality supported
! Extended SCO (eSCO), eV3 +CRC, eV4, eV5
! Scatter mode
! LMP Absence Masks ,Quality of service and SCO handle
! L2CAP flow and error control
! Synchronisation
Standard Bluetooth Functionality
The firmware has been written against the Bluetooth Core Specification v1.2.
! Bluetooth components: Baseband (including LC), LM and HCI
! Standard USB v2.0 and UART (H5) HCI Transport Layers
! All standard radio packet types
! Full Bluetooth data rate, up to 723.2kbps asymmetric(1)
! Operation with up to seven active slaves (1)
! Maximum number of simultaneous active ACL connections: 7(2)
! Maximum number of simultaneous active SCO connections: 3(2)
! Operation with up to three SCO links, routed to one or more slaves
! Scatternet 2.5 operation
! All standard SCO voice coding, plus “transparent SCO”
! Standard operating modes: page, inquiry, page-scan and inquiry-scan
! All standard pairing, authentication, link key and encryption operations
! Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including “Forced Hold”
! Dynamic control of peers’ transmit power via LMP
! Master/slave switch
! Broadcast
! Channel quality driven data rate
! All standard Bluetooth Test Modes
The firmware’s supported Bluetooth features are detailed in the standard Protocol Implementation Conformance
Statement (PICS) documents, available from www.csr.com.
Notes:
(1) Maximum allowed by Bluetooth specification v1.2
(2) Supports all combinations of active ACL and SCO channels, per Bluetooth specification v1.2
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Extra Functionality
! The firmware extends the standard Bluetooth functionality with the following features:
! Supports BlueCore Serial Protocol (BCSP) – a proprietary, reliable alternative to the standard Bluetooth
UART Host Transport.
! Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BCCMD (BlueCore Command), provides:
! Access to the chip’s general-purpose PIO port
! The negotiated effective encryption key length on established Bluetooth links
! Access to the firmware’s random number generator
! Controls to set the default and maximum transmit powers. These can help minimise interference
between overlapping, fixed-location piconet
! Dynamic UART configuration
! Radio transmitter enable/disable (a simple command connects to a dedicated hardware switch that
determines whether the radio can transmit)
! The firmware can read the voltage on a pair of the chip’s external pins. This is normally used to build a
battery monitor, using either VM or host code.
! A block of BCCMD commands provides access to the chip’s “persistent store” configuration database
(PS). The database sets the device’s Bluetooth address, Class of Device, radio (transmit class)
configuration, SCO routing, LM, USB and DFU constants, etc.
! A UART “break” condition can be used in three ways:
1. Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
2. Presenting a break condition at boot time can hold the chip in a low power state, preventing
normal initialisation while the condition exists
3. With H5, the firmware can be configured to send a break to the host before sending data
(normally used to wake the host from a Deep Sleep state)
! A block of “radio test” or BIST commands allows direct control of the chip’s radio. This aids the
development of modules’ radio designs, and can be used to support Bluetooth qualification.
! Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific
code. Although the VM is mainly used with BlueLab and “RFCOMM builds” (alternative firmware builds
providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such
as flashing LEDs via the chip’s PIO port.
! Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
! SCO channels are normally routed over HCI over BCSP, H5 or USB. However, up to three SCO
channels can be routed over the chip’s single PCM port at the same time as routing any other SCO
channels over HCI.
! Co-operative existence with 802.11b chipsets
Always refer to the Firmware Release Note for the specific functionality of a particular build
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8.2 BlueCore RFCOMM Stack
LC
Internal ROM
32KB RAM Baseband
MCU
Host I/O
Radio
PCM I/O
USB
UART
Host
RFCOMM SDP
LM
L2CAP
HCI
Figure 8.2: BlueCore RFCOMM Stack
In this version of the firmware the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This
reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the
HCI only stack.
8.2.1 Key Features of the BlueCore3-ROM RFCOMM Stack
Interfaces to Host
! RFCOMM, an RS-232 serial cable emulation protocol
! SDP, a service database look-up protocol
Connectivity
! Maximum number of active slaves: 3
! Maximum number of simultaneous active ACL connections: 3
! Maximum number of simultaneous active SCO connections: 3
! Data Rate: up to 350Kb/s
Security
! Full support for all Bluetooth security features up to and including strong (128-bit) encryption.
Power Saving
! Full support for all Bluetooth power saving modes (Park, Sniff and Hold).
Data Integrity
! CQDDR increases the effective data rate in noisy environments.
! RSSI used to minimise interference to other radio devices using the ISM band.
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8.3 BlueCore Virtual Machine Stack
LC
Internal ROM
32KB RAM Baseband
MCU
Host I/O
Radio
PCM I/O
USB
UART
Host (Optional )
RFCOMM SDP
VM Application Software
LM
L2CAP
HCI
Figure 8.3: Virtual Machine
This version of the stack firmware requires no host processor although the serial communication ports can still be
used under the control of the VM application. All software layers, including application software, run on the
internal RISC microcontroller in a protected user software execution environment known as a virtual machine
(VM).
The user may write custom application code to run on the BlueCore VM using BlueLab™ software development
kit (SDK) supplied with the BlueLab and Casira development kits, available separately from CSR. This code will
then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for
various operations.
The execution environment is structured so the user application does not adversely affect the main software
routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the
application is changed.
Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other
profiles without the requirement of a host controller. BlueLab is supplied with example code including a full
implementation of the headset profile.
On successful completion of firmware development and testing using BlueCore3-ROM Flash, CSR can commit
the code to a mask set for mass production of the device. A Non Recurring Engineering (NRE) charge will be
required.
Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.
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8.4 BlueCore HID Stack
LC
Internal ROM
32KB RAM Baseband
MCU
HID I/O RadioPIO/UART
Sensing
Hardware
(Optical Sensor
etc.)
HID SDP
VM Application Software
LM
L2CAP
HCI
Figure 8.4: HID Stack
This version of the stack firmware requires no host processor. All software layers, including application software,
run on the internal RISC microcontroller in a protected user software execution environment known as a virtual
machine (VM).
The user may write custom application code to run on the BlueCore VM using BlueLab Professional software
development kit (SDK) supplied with the BlueLab Professional and Casira development kits, available separately
from CSR. This code will then execute alongside the main BlueCore firmware. The user is able to make calls to
the BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software
routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the
application is changed.
Using the VM and the BlueLab Professional SDK the user is able to develop Bluetooth HID devices such as an
optical mouse or keyboard. The user is able to customise features such as power management and
connect/reconnect behaviour.
The HID I/O component in the HID stack controls low latency data acquisition from external sensor hardware.
With this component running in native code, it does not incur the overhead of the VM code interpreter. Supported
external sensors include 5 mouse buttons, the Agilent ADNS-2030 optical sensor, quadrature scroll wheel, direct
coupling to a keyboard matrix and a UART interface to custom hardware.
On successful completion of firmware development and testing using BlueCore3-ROM Flash, CSR can commit
the code to a mask set for mass production of the device. A non recurring engineering (NRE) charge will be
required.
A reference schematic for implementing a three button, optical mouse with scroll wheel is available from CSR.
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8.5 BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality
into embedded products quickly, cheaply and with low risk.
BCHS is developed to work with CSR's family of BlueCore IC's. BCHS is intended for embedded products that
have a host processor for running BCHS and the Bluetooth application e.g. a mobile phone or a PDA. BCHS
together with the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete
Bluetooth system solution from RF to profiles.
BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to
develop a Bluetooth product without in-depth Bluetooth knowledge.
The BlueCore Embedded Host Software contains 3 elements:
! Example Drivers (BCSP and proxies)
! Bluetooth Profile Managers
! Example Applications
The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with
source code (ANSI C). With BCHS also come example applications in ANSI C, which makes the process of
writing the application easier.
8.6 Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore3-ROM, a UART software
driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher Bluetooth
stack layers running on the host. The code is provided as ‘C’ source or object code.
8.7 CSR Development Systems
CSR’s BlueLab and Casira development kits are available to allow the evaluation of the BlueCore3 hardware and
software, and as toolkits for developing on-chip and host software.
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9 Device Terminal Descriptions
9.1 RF Ports
The BlueCore3-ROM RF_IN terminal can be configured as either a single ended or differential input. The
operational mode is determined by the setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x20).
9.2 Transmitter/Receiver Inputs and Outputs
Terminals TX_A and TX_B form a balanced current output. They require a DC path to VDD and should be
connected through a balun to the antenna. The output impedance is capacitive and remains constant, regardless
of whether the transmitter is enabled or disabled. For Class 2 operation these terminals also act as differential
receive input terminals with an internal TX/RX switch.
Figure 9.1: Circuit TX/RX_A and TX/RX_B
For the 6 x 6 package, an off-chip balun and filter are required. These may comprise separate discrete
components, see Figure 10.1, differential filter only, or as printed structures.
For Class 1 operation the RF_IN ball is provided which is single-ended. A swing of up to 0.5V root mean squared
(rms) can be tolerated at this terminal. An external antenna switch can be connected to RF_IN.
Figure 9.2: Circuit RF_IN
R2
10Ω
0.9pF
TX_A
TX_B
PA
+
-
LNA
-
+
R3
10Ω
0.9pF
RF
Switch
RF
Switch
L2
1.5nH
L3
1.5nH
BlueCore3-ROM
RF_IN
R1
6.8Ω
C1
0.68pF
L1
1.5nH
BlueCore3-ROM
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9.2.1 Transmitter S-Parameters
S11 S21 S12 S22
Freq
(MHz) Real Imaginary Real Imaginary Real Imaginary Real Imaginary
2402 -8.18E-03 -6.79E-01 2.47E-03 6.48E-02 -9.96E-04 7.01E-02 -3.74E-02 -6.65E-01
2408 -8.18E-03 -6.79E-01 2.47E-03 6.90E-02 -9.96E-04 6.20E-02 -3.74E-02 -6.65E-01
2414 -9.98E-03 -6.79E-01 2.11E-03 6.93E-02 -1.77E-03 6.33E-02 -3.89E-02 -6.65E-01
2420 -1.45E-02 -6.78E-01 2.89E-03 6.89E-02 -1.22E-03 6.29E-02 -4.33E-02 -6.64E-01
2426 -1.79E-02 -6.76E-01 3.16E-03 6.86E-02 -1.21E-03 6.28E-02 -4.62E-02 -6.62E-01
2432 -2.19E-02 -6.75E-01 3.59E-03 6.86E-02 -1.08E-03 6.30E-02 -4.91E-02 -6.61E-01
2438 -2.56E-02 -6.74E-01 3.89E-03 6.83E-02 -9.35E-04 6.32E-02 -5.28E-02 -6.60E-01
2444 -2.87E-02 -6.73E-01 4.07E-03 6.81E-02 -8.20E-04 6.33E-02 -5.67E-02 -6.60E-01
2450 -3.27E-02 -6.72E-01 4.25E-03 6.79E-02 -6.83E-04 6.35E-02 -6.08E-02 -6.59E-01
2456 -3.55E-02 -6.72E-01 4.46E-03 6.77E-02 -3.59E-04 6.36E-02 -6.45E-02 -6.58E-01
2462 -3.94E-02 -6.71E-01 4.73E-03 6.75E-02 -1.26E-04 6.38E-02 -6.71E-02 -6.59E-01
2468 -4.33E-02 -6.70E-01 4.80E-03 6.72E-02 1.68E-04 6.38E-02 -7.14E-02 -6.57E-01
2474 -4.70E-02 -6.70E-01 4.80E-03 6.70E-02 3.78E-04 6.38E-02 -7.45E-02 -6.57E-01
2480 -5.03E-02 -6.70E-01 4.85E-03 6.68E-02 5.26E-04 6.38E-02 -7.71E-02 -6.56E-01
Table 9.1: Transmit Impedance
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Figure 9.3: TX_A PL35
Figure 9.4: TX_A PL50
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Figure 9.5: TX_A PL63
Figure 9.6: TX_B PL35
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Figure 9.7: TX_B PL50
Figure 9.8: TX_B PL63
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9.2.2 Receiver S-Parameters
S11 S21 S12 S22
Freq
(MHz) Real Imaginary Real Imaginary Real Imaginary Real Imaginary
2402 8.99E-02 -7.74E-01 1.29E-02 2.86E-02 1.29E-02 2.84E-02 3.49E-02 -7.58E-01
2408 8.62E-02 -7.74E-01 1.27E-02 2.87E-02 1.25E-02 2.84E-02 3.14E-02 -7.58E-01
2414 8.40E-02 -7.74E-01 1.24E-02 2.88E-02 1.23E-02 2.84E-02 2.73E-02 -7.57E-01
2420 8.08E-02 -7.74E-01 1.22E-02 2.88E-02 1.20E-02 2.86E-02 2.32E-02 -7.58E-01
2426 7.79E-02 -7.74E-01 1.19E-02 2.89E-02 1.18E-02 2.87E-02 1.91E-02 -7.57E-01
2432 7.40E-02 -7.74E-01 1.18E-02 2.91E-02 1.15E-02 2.88E-02 1.48E-02 -7.57E-01
2438 7.06E-02 -7.75E-01 1.15E-02 2.92E-02 1.13E-02 2.90E-02 1.07E-02 -7.56E-01
2444 6.74E-02 -7.74E-01 1.13E-02 2.93E-02 1.11E-02 2.91E-02 6.50E-03 -7.55E-01
2450 6.33E-02 -7.74E-01 1.10E-02 2.93E-02 1.08E-02 2.91E-02 1.53E-03 -7.56E-01
2456 6.06E-02 -7.74E-01 1.07E-02 2.94E-02 1.05E-02 2.92E-02 -3.51E-03 -7.55E-01
2462 5.66E-02 -7.74E-01 1.05E-02 2.94E-02 1.03E-02 2.93E-02 -6.32E-03 -7.56E-01
2468 5.33E-02 -7.74E-01 1.01E-02 2.95E-02 9.94E-03 2.95E-02 -1.24E-02 -7.54E-01
2474 5.00E-02 -7.75E-01 9.75E-03 2.96E-02 9.65E-03 2.97E-02 -1.71E-02 -7.54E-01
2480 4.73E-02 -7.75E-01 9.46E-03 2.98E-02 9.35E-03 2.98E-02 -2.15E-02 -7.52E-01
Table 9.2: Balanced Receiver Impedance
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Figure 9.9: RX_A Balanced
Figure 9.10: RX_B Balanced
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9.2.3 Single Ended Impedance
S11
Frequency
(MHz) Real Imaginary
2402 4.70E-01 -7.23E-01
2408 4.65E-01 -7.24E-01
2414 4.63E-01 -7.27E-01
2420 4.57E-01 -7.29E-01
2426 4.54E-01 -7.29E-01
2432 4.53E-01 -7.29E-01
2438 4.51E-01 -7.31E-01
2444 4.47E-01 -7.32E-01
2450 4.46E-01 -7.33E-01
2456 4.44E-01 -7.34E-01
2462 4.44E-01 -7.34E-01
2468 4.39E-01 -7.37E-01
2474 4.35E-01 -7.39E-01
2480 4.30E-01 -7.39E-01
Table 9.3: Single Ended Impedance
Figure 9.11: RX Un-Balanced
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9.3 External Reference Clock Input (XTAL_IN)
The BlueCore3-ROM RF local oscillator and internal digital clocks are derived from the reference clock at the
BlueCore3-ROM XTAL_IN input. This reference may be either an external clock or from a crystal connected
between XTAL_IN and XTAL_OUT. The crystal mode is described in Section 9.4.
9.3.1 External Mode
BlueCore3-ROM can be configured to accept an external reference clock (from another device, such as TCXO)
at XTAL_IN by connecting XTAL_OUT to ground. The external clock can either be a digital level square wave or
sinusoidal and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks
of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking
capacitor (~33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity as the
high slew rate clock edges have lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 9.5:
Min Typ Max
Frequency(1) 7.5MHz 16MHz 40MHz
Duty cycle 20:80 50:50 80:20
Edge Jitter (At Zero Crossing) - - 15ps rms
Signal Level 400mV pk-pk - VDD_ANA(2)(3)
Table 9.4: External Clock Specifications
Notes:
(1) The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
(2) VDD_ANA is 1.8V nominal
(3) If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is
reduced from VDD_ANA to 800mV pk-pk
9.3.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
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9.3.3 Clock Timing Accuracy
As Figure 9.12 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of
the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance
with the Bluetooth v1.2 specification. Radio activity may occur after 11ms, therefore at this point, the timing
accuracy of the external clock source must be within 20ppm.
Figure 9.12: TCXO Clock Accuracy
9.3.4 Clock Start-Up Delay
BlueCore3-ROM hardware incorporates an automatic 5ms delay after the assertion of the system clock request
signal before running firmware. This is suitable for most applications using an external clock source. However,
there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under
these conditions, BlueCore3-ROM firmware provides a software function which will extend the system clock
request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from
5-31ms.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueCore3-ROM as low as possible. BlueCore3-ROM will consume about
2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
Actu al Allowable Clock Presence Delay on XTA L_ IN vs. PSKey Setting
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0 5.0 10.0 15.0 20.0 25.0 30.0
PSKEY_CLOCK_STARTUP_DELAY
Delay (m s)
Figure 9.13: Actual Allowable Clock Presen ce Delay on XTAL_IN vs. PS Key Setting
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9.3.5 Input Frequencies and PS Key Settings
BlueCore3-ROM should be configured to operate with the chosen reference frequency. This is accomplished by
setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of 250KHz. The input
frequency default setting in BlueCore3-ROM is 26MHz.
The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68,
19.8 and 38.4MHz. This is accomplished by also changing PSKEY PLLX_FREQ_REF (0xabc).
Reference Crystal Frequency (MHz) PSKEY_ANA_FREQ (0x1fe) (Units of 1kHz)
7.68 7680
14.40 14400
15.36 15360
16.20 16200
16.80 16800
19.20 19200
19.44 19440
19.68 19680
19.80 19800
38.40 38400
n x 250kHz -
+26.00 Default 26000
Table 9.5: PS Key Values for CDMA/3G phone TCXO Frequencies
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9.4 Crystal Oscillator (XTAL_IN, XTAL_OUT)
The BlueCore3-ROM RF local oscillator and internal digital clocks are derived from the reference clock at the
BlueCore3-ROM XTAL_IN input. This reference may be either an external clock or from a crystal connected
between XTAL_IN and XTAL_OUT. The external reference clock mode is described in Section 9.3.
9.4.1 XTAL Mode
BlueCore3-ROM contains a crystal driver circuit. This operates with an external crystal and capacitors to form a
Pierce oscillator.
Figure 9.14: Crystal Driver Circuit
Figure 9.15 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
Figure 9.15: Crystal Equi valent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore3-ROM contains variable
internal capacitors to provide a fine trim.
The BlueCore3-ROM driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at
XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.
-
gm
BlueCore3-ROM
Ctrim Cint Ctrim
Ct2 Ct1
XTAL_IN
XTAL_OUT
LmRm
Cm
Co
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9.4.2 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore3-ROM
provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external
capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This
maximises the signal swing, hence slew rate at XTAL_IN, to which all on chip clocks are referred. Crystal load
capacitance, Cl is calculated with the following equation:
Equation 9.1: Load Capacitance
Where:
Ctrim = 3.4pF nominal (Mid range setting)
Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance, it is the driver self capacitance
9.4.3 Frequency Trim
BlueCore3-ROM enables frequency adjustments to be made. This feature is typically used to remove initial
tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load
capacitance with on chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the Persistent Store Key
PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus:
Equation 9.2: Trim Capacitance
There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they
appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal
of 55fF.
The frequency trim is described by Equation 9.3:
Equation 9.3: Frequency Trim
Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63
times the value above.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 9.4:
Equation 9.4: Pullability
Where:
C0 = Crystal self capacitance (shunt capacitance)
Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 9.15.
Note:
It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient
to pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift
with ageing and temperature. A crystal with an ageing and temperature drift specification of better than
±15ppm is required.
2t1t
2t1ttrim
intl CC
CC
2
C
CC +
⋅
++=
FTRIMPSKEY_ANA_ fF 110 Ctrim ×=
()
)LSB/ppm(1055ypullabilit
F
F3
x
x−
××=
Δ
(
)
() ()
2
0l
m
x
x
CC4
C
F
C
F
+
⋅=
∂
∂
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9.4.4 Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to
one terminal generates a voltage at the other. The transconductance amplifier in BlueCore3-ROM uses the
voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if
the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the
product should be greater than 3. The transconductance required for oscillation is defined by the following
relationship:
Equation 9.5: Transconductance Required for Oscillation
BlueCore3-ROM guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher
capacitance loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk−pk. The drive level is
determined by the crystal driver transconductance, by setting the Persistent Store KEY_XTAL_LVL (0x241).
9.4.5 Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element.
The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of
the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the
BlueCore3-ROM crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance
may be calculated for it with the following formula in Equation 9.6:
Equation 9.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore3-ROM driver as a function of its drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series
with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of
the oscillator.
Min Typ Max
Frequency 8MHz 16MHz 32MHz
Initial Tolerance - ±25ppm -
Pullability - ±20ppm/pF -
Table 9.6: Crystal Oscillator Specification
9.4.6 Crystal PS Key Settings
See tables in Section 9.3.5.
(
)
(
)
()( )( )( )( )()
2
trim2ttrim1ttrim2t1tint0m
2
x
trim2ttrim1t
mCCCCC2CCCCRF2
CCCC3
g
++++++π
++
>
(
)
(
)
()( )( )( )( )()
2
trim2ttrim1ttrim2t1tint0
2
xm
trim2ttrim1t
neg CCCCC2CCCCF2g
CCCC3
R
++++++π
++
>
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9.4.7 Crystal Oscillator Characteristics
Figure 9.16: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequ en cy
Note:
Graph shows results for BlueCore3-ROM crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value
Crystal Co = 2pF
Transconductance setting = 2mA/V
Loop gain = 3
Ct1/Ct2 = 3
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
10.0
100.0
1000.0
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5
Load Capacitance (pF)
Max X tal Rm Value (ESR), (Ohm)
8 MHz 12 MHz 16 MHz
20 MHz 24 MHz 28 MHz
32 MHz
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Figure 9.17: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by Persistent Store Key PSKEY_XTAL_LVL (0x241).
BlueCore3-ROM XTAL Driver Characteristics
0.000
0.001
0.002
0.003
0.004
0.005
0.006
0.007
012345678910111213141516
PSKEY_XTAL_LVL
Transconductance (S)
Gm Typical
Gm Minimum
Gm Maximum
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Figure 9.18: Crystal Dri ver Negative Resistance as a Function of Drive Level Setting
Crystal parameters:
Crystal frequency 16MHz (Please refer to your software build release note for frequencies supported);
Crystal C0 = 0.75pF
Circuit parameters:
Ctrim = 8pF, maximum value
Ct1,Ct2 = 5pF (3.9pF plus 1.1pF stray)
(Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
Negative Resistance for 16 MHz Xtal
10
100
1000
10000
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0
Drive Level Setting
Max -ve Resistance (Ω)
Typical
Minimum
Maximum
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9.5 UART Interface
BlueCore3-ROM Universal Asynchronous Receiver Transmitter (UART) interface provides a simple mechanism
for communicating with other serial devices using the RS232 standard (1).
Figure 9.19: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 9.19. When BlueCore3-ROM is
connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The
remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control
where both are active low indicators. All UART connections are implemented using CMOS technology and have
signalling levels of 0V and VDD_PADS.
UART configuration parameters, such as Baud rate and packet format, are set using BlueCore3-ROM software.
Notes:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial
port adapter card is required for the PC.
(1) Uses RS232 protocol but voltage levels are 0V to VDD_USB, (requires external RS232 transceiver chip)
Parameter Possible Values
1200 Baud (≤2%Error)
Minimum 9600 Baud (≤1%Error)
Baud Rate
Maximum 1.5MBaud (≤1%Error)
Flow Control RTS/CTS or None
Parity None, Odd or Even
Number of Stop Bits 1 or 2
Bits per channel 8
Table 9.7: Possible U ART Settings
UART_TX
UART_RX
UART_RTS
UART_CTS
BlueCore3-ROM
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The UART interface is capable of resetting BlueCore3-ROM upon reception of a break signal. A Break is
identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 9.20. If tBRK is longer than
the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This
feature allows a host to initialise the system to a known state. Also, BlueCore3-ROM can emit a Break character
that may be used to wake the Host.
Figure 9.20: Break Signal
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used.
This initial flash programming can be done via the SPI.
Table 9.8 shows a list of commonly used Baud rates and their associated values for the Persistent Store Key
PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any Baud rate
within the supported range can be set in the Persistent Store Key according to the formula in Equation 9.7.
Equation 9.7: Baud Rate
Persistent Store Value
Baud Rate Hex Dec
Error
1200 0x0005 5 1.73%
2400 0x000a 10 1.73%
4800 0x0014 20 1.73%
9600 0x0027 39 -0.82%
19200 0x004f 79 0.45%
38400 0x009d 157 -0.18%
57600 0x00ec 236 0.03%
76800 0x013b 315 0.14%
115200 0x01d8 472 0.03%
230400 0x03b0 944 0.03%
460800 0x075f 1887 -0.02%
921600 0x0ebf 3775 0.00%
1382400 0x161e 5662 -0.01%
Table 9.8: Standard Baud Rates
004096.0
_BAUD_RATEPSKEY_UART
Rate Baud =
UART RX
tBRK
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9.5.1 UART Bypass
Figure 9.21: UART Bypass Architecture
9.5.2 UART Configuration while RESET is Active
The UART interface for BlueCore3-ROM while the chip is being held in reset is tri-state. This will allow the user to
daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tri-state when BlueCore3-ROM reset is de-asserted and the firmware begins to run.
9.5.3 UART B ypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore3-ROM can be
used. The default state of BlueCore3-ROM after reset is de-asserted is for the host UART bus to be connected to
the BlueCore3-ROM UART, thereby allowing communication to BlueCore3-ROM via the UART.
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore3-ROM upon this, it will
switch the bypass to PIO[7:4] as shown in Figure 9.21. Once the bypass mode has been invoked,
BlueCore3-ROM will enter the deep sleep state indefinitely.
In order to re-establish communication with BlueCore3-ROM, the chip must be reset so that the default
configuration takes affect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode
is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode.
9.5.4 Current Consumption in UART Bypass Mode
The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in
standby mode.
BlueCore3-ROM
Another Device
RESET
UART
Host Processor
RXD
CTS
Test Interface
RTS
UART_RX
UART_CTS
UART_RTS
UART_TX PIO4
PIO5
PIO6
PIO7
TXD
TX
RTS
CTS
RX
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9.6 USB Interface
BlueCore3-ROM devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable
directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to
requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported. The
set of USB endpoints implemented can behave as specified in the USB section of the Bluetooth specification v1.2
or alternatively can appear as a set of endpoints appropriate to USB audio devices such as speakers.
As USB is a Master/Slave oriented system (in common with other USB peripherals), BlueCore3-ROM only
supports USB Slave operation.
9.6.1 USB Data Connections
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB
I/O buffers of the BlueCore3-ROM and therefore have a low output impedance. To match the connection to the
characteristic impedance of the USB cable, resistors must be placed in series with USB_DP / USB_DN and the
cable.
9.6.2 USB Pull-Up Resistor
BlueCore3-ROM features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when
BlueCore3-ROM is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s) USB device.
The USB internal pull-up is implemented as a current source, and is compliant with Section 7.1.5 of the USB
specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15kΩ ±5%
pull-down resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at
least 900Ω. Alternatively, an external 1.5kΩ pull-up resistor can be placed between a PIO line and D+ on the
USB cable. The firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP
appropriately. The default setting uses the internal pull-up resistor.
9.6.3 Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet
the USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V.
CSR recommends 3.3V for optimal USB signal quality.
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9.6.4 Self Powered Mode
In self powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the
USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier
mode for which to design for, as the design is not limited by the power that can be drawn from the USB hub or
root port. However, it requires that VBUS be connected to BlueCore3-ROM via a resistor network (Rvb1 and Rvb2),
so BlueCore3-ROM can detect when VBUS is powered up. BlueCore3-ROM will not pull USB_DP high when
VBUS is off.
Self powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB
pull-up purposes. A 1.5K 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the
design. Failure to fit this resistor may result in the design failing to be USB compliant in self powered mode. The
internal pull-up in BlueCore is only suitable for bus powered USB devices i.e. dongles.
Figure 9.22: USB Connections for Self Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting
PSKEY_USB_PIO_VBUS to the corresponding pin number.
USB_DP
USB_DN
USB_ON
D-
VBUS
D+
GND
Rs
Rs
Rvb1
Rvb2
BlueCore3-ROM
PIO 1.5KΩ 5%
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9.6.5 Bus Powered Mode
In bus powered mode the application circuit draws its current from the 5V VBUS supply on the USB cable.
BlueCore3-ROM negotiates with the PC during the USB enumeration stage about how much current it is allowed
to consume.
For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated
at 100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In bus
powered mode, BlueCore3-ROM requests 100mA during enumeration.
For Class 1 Bluetooth applications, the USB power descriptor should be altered to reflect the amount of power
required. This is accomplished by setting the PS Key PSKEY_USB_MAX_POWER (0x2c6). This is higher than
for a Class 2 application due to the extra current drawn by the Transmit RF PA.
When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging
reservoir and supply decoupling capacitors) is limited by the USB specification (see USB specification v1.1,
Section 7.2.4.1). Some applications may require soft start circuitry to limit inrush current if more than 10μF is
present between VBUS and GND.
The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V,
applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator
bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore3-ROM will result in
reduced receive sensitivity and a distorted RF transmit signal.
Figure 9.23: USB Connections for Bus Powered Mode
Note:
USB_ON is shared with BlueCore3-ROM PIO terminals
Identifier Value Function
Rs 27Ω nominal Impedance matching to USB cable
Rvb1 22kΩ 5% VBUS ON sense divider
Rvb2 47kΩ 5% VBUS ON sense divider
Table 9.9: USB Interface Component Values
USB_DP
USB_DN
USB_ON
D-
VBUS
D+
GND
Rs
Rs
Rvb1
BlueCore3-ROM
Voltage
Regulator
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9.6.6 Suspend Current
All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend,
bus powered devices must not draw more than 0.5mA from USB VBUS (self powered devices may draw more
than 0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus
powered devices during USB Suspend.
The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100μA) to
ensure adherence to the suspend current requirement of the USB specification. This is not normally a problem
with modern regulators. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore3-ROM. The
entire circuit must be able to enter the suspend mode. (For more details on USB Suspend, see separate CSR
documentation).
9.6.7 Detach and Wake_Up Signalling
BlueCore3-ROM can provide out-of-band signalling to a host controller by using the control lines called
‘USB_DETACH’ and ‘USB_WAKE_UP’. These are outside the USB specification (no wires exist for them inside
the USB cable), but can be useful when embedding BlueCore3-ROM into a circuit where no external USB is
visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the
PS Keys PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number.
USB_DETACH is an input which, when asserted high, causes BlueCore3-ROM to put USB_DN and USB_DP in
a high impedance state and turned off the pull-up resistor on DP. This detaches the device from the bus and is
logically equivalent to unplugging the device. When USB_DETACH is taken low, BlueCore3-ROM will connect
back to USB and await enumeration by the USB host.
USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and
allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message
(which runs over the USB cable), and cannot be sent while BlueCore3-ROM is effectively disconnected from the
bus.
Figure 9.24: USB_DETACH and USB_WAKE_UP Signal
9.6.8 USB Driver
A USB Bluetooth device driver is required to provide a software interface between BlueCore3-ROM and
Bluetooth software running on the host computer. Suitable drivers are available from www.csrsupport.com.
USB_DETACH
USB_WAKE_UP
Port_Impedance
USB_DP
USB_DN
USB_PULL_UP
10ms max
10ms max
Disconnected
No max
10ms max
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9.6.9 USB 1.1 Compliance
BlueCore3-ROM is qualified to the USB specification v1.1, details of which are available from http://www.usb.org.
The specification contains valuable information on aspects such as PCB track impedance, supply inrush current
and product labelling.
Although BlueCore3-ROM meets the USB specification, CSR cannot guarantee that an application circuit
designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout
all affect USB signal quality and electrical characteristics. The information in this document is intended as a guide
and should be read in association with the USB specification, with particular attention being given to Chapter 7.
Independent USB qualification must be sought before an application is deemed USB compliant and can bear the
USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
Terminals USB_DP and USB_DN adhere to the USB specification 2.0 (Chapter 7) electrical requirements.
9.6.10 USB 2.0 Compatibility
BlueCore3-ROM is compatible with USB v2.0 host controllers; under these circumstances the two ends agree the
mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
9.7 Serial Peripheral Interface
BlueCore3-ROM uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur
when the internal processor is running or is stopped. This section details the considerations required when
interfacing to BlueCore3-ROM via the four dedicated serial peripheral interface terminals. Data may be written or
read one word at a time or the auto increment feature may be used to access blocks.
9.7.1 Instruction Cycle
The BlueCore3-ROM is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. The
instruction cycle for a SPI transaction is shown in Table 9.10.
1 Reset the SPI interface Hold SPI_CSB high for two SPI_CLK cycles
2 Write the command word Take SPI_CSB low and clock in the 8 bit command
3 Write the address Clock in the 16-bit address word
4 Write or read data words Clock in or out 16-bit data word(s)
5 Termination Take SPI_CSB high
Table 9.10: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueCore3-ROM on the rising edge of the clock line SPI_CLK. When reading, BlueCore3-ROM will reply to
the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the
clock on SPI_CLK. The transaction is teminated by taking SPI_CSB high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore3-ROM offers
increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept
low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written
or read.
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9.7.2 Writing to BlueCore3-ROM
To write to BlueCore3-ROM, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit
address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the
address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data
written to consecutive locations until the transaction terminates when SPI_CSB is taken high.
Figure 9.25: Write Operation
9.7.3 Reading from BlueCore3-ROM
Reading from BlueCore3-ROM is similar to writing to it. An 8-bit read command (00000011) is sent first (C[7:0]),
followed by the address of the location to be read (A[15:0]). BlueCore3-ROM then outputs on SPI_MISO a check
word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read
operation to a memory location. This overcomes the problems encountered with typical serial peripheral interface
slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the
result of the slave device not responding.
If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks,
until the transaction terminates when SPI_CSB is taken high.
Figure 9.26: Read Operation
9.7.4 Multi Slave Operation
BlueCore3-ROM should not be connected in a multi slave arrangement by simple parallel connection of slave
MISO lines. When BlueCore3-ROM is deselected (SPI_CSB = 1), the SPI_MISO line does not float, instead,
BlueCore3-ROM outputs 0 if the processor is running or 1 if it is stopped.
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
C7 C6 C1 C0 A15 A14 A1 A0 Don't Care
T15 T14 T1 T0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0
Address(A) Check_Word Data(A) Data(A+1) etc
Reset
Read_Command
End of Cycle
Processor
State
Processor
State
MISO Not Defined During Address
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
C7 C6 C1 C0 A15 A14 A1 A0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0 Don't Care
Processor
State
Address(A) Data(A) Data(A+1) etcWrite_Command
Reset
Processor
State MISO Not Defined During Write
End of Cycle
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9.7.5 PCM CODEC Interface
Pulse Code Modulation (PCM) is a standard method used to digitise human voice patterns for transmission over
digital communication channels. Through its PCM interface, BlueCore3-ROM has hardware support for continual
transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications.
BlueCore3-ROM offers a bi directional digital audio interface that routes directly into the baseband layer of the on
chip firmware. It does not pass through the HCI protocol layer.
Hardware on BlueCore3-ROM allows the data to be sent to and received from a SCO connection.
Up to three SCO connections can be supported by the PCM interface at any one time(1).
BlueCore3-ROM can operate as the PCM interface Master generating an output clock of 128, 256 or 512kHz.
When configured as PCM interface slave it can operate with an input clock up to 2048kHz. BlueCore3-ROM is
compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing
environments.
It supports 13 or 16-bit linear, 8-bit μ-law or A-law companded sample formats at 8ksamples/s and can receive
and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options
are enabled by setting the PS Key PS KEY_PCM_CONFIG (0x1b3).
BlueCore3-ROM interfaces directly to PCM audio devices including the following:
! Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices
! OKI MSM7705 four channel A-law and μ-law CODEC
! Motorola MC145481 8-bit A-law and μ-law CODEC
! Motorola MC145483 13-bit linear CODEC
! STW 5093 and 5094 14-bit linear CODECs
! BlueCore3-ROM is also compatible with the Motorola SSI™ interface
Note:
(1) Subject to firmware support, contact CSR for current status.
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9.7.6 PCM Interface Master/Slave
When configured as the Master of the PCM interface, BlueCore3-ROM generates PCM_CLK and PCM_SYNC.
Figure 9.27: BlueCore3-ROM as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore3-ROM accepts PCM_CLK rates up to 2048kHz.
Figure 9.28: BlueCore3-ROM as PCM Interface Slave
BlueCore3-ROM
PCM_SYNC
PCM_OUT
PCM_IN
PCM_CLK 128/256/512kHz
8kHz
BlueCore3-ROM
PCM_SYNC
PCM_OUT
PCM_IN
PCM_CLK Upto 2048kHz
8kHz
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9.7.7 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or
samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
BlueCore3-ROM is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-
bits long. When BlueCore3-ROM is configured as PCM Slave, PCM_SYNC may be from two consecutive falling
edges of PCM_CLK to half the PCM_SYNC rate, i.e. 62.5μs long.
Figure 9.29: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore3-ROM samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.
PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on
the rising edge.
9.7.8 Short Frame Sync
In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always
one clock cycle long.
Figure 9.30: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore3-ROM samples PCM_IN on the falling edge of PCM_CLK and transmits
PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of
PCM_CLK in the LSB position or on the rising edge.
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Undefined Undefined
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
12345678910 11 12 13 14 15 16
12345678910 11 12 13 14 15 16 UndefinedUndefined
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9.7.9 Multi Slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO
connections can be carried over any of the first four slots.
Figure 9.31: Multi Slot Operation with Two Slots and 8-bit Companded Samples
9.7.10 GCI Interface
BlueCore3-ROM is compatible with the General Circuit Interface, a standard synchronous 2B+D ISDN timing
interface. The two 64Kbps B channels can be accessed when this mode is configured.
Figure 9.32: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore3-ROM in
Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
LONG_PCM_SYNC
Or
SHORT_PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not CareDo Not Care
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not
Care
Do Not
Care
B1 Channel B2 Channel
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9.7.11 Slots and Sample Formats
BlueCore3-ROM can receive and transmit on any selection of the first four slots following each sync pulse. Slot
durations can be either 8 or 16 clock cycles. Duration’s of 8 clock cycles may only be used with 8-bit sample
formats. Durations of 16 clocks may be used with 8, 13 or 16-bit sample formats.
BlueCore3-ROM supports 13-bit linear, 16-bit linear and 8-bit μ-law or A-law sample formats. The sample rate is
8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each
slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible
with some Motorola CODECs.
Figure 9.33: 16-Bit Slot Length and Sample Formats
9.7.12 Additional Features
BlueCore3-ROM has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be
forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
PCM_OUT
PCM_OUT
PCM_OUT
PCM_OUT
12345678910 11 12 13 14 15 16
12345678910 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12345678910 11 12 13 14 15 16
Sign
Extension
8-Bit
Sample
8-Bit
Sample
Zeros
Padding
Sign
Extension
13-Bit
Sample
13-Bit
Sample
Audio
Gain
A 16-bit slot with 8-bit companded sample and sign extension selected.
A 16-bit slot with 8-bit companded sample and zeros padding selected.
A 16-bit slot with 13-bit linear sample and sign extension selected.
A 16-bit slot with 13-bit linear sample and audio gain selected.
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9.7.13 PCM Timing Information
Symbol Parameter Min Typ Max Unit
128
256
4MHz DDS generation.
Selection of frequency is
programmable, see
Table 9.13
-
512
- kHz
fmclk PCM_CLK frequency 48MHz DDS generation.
Selection of frequency is
programmable, see
Table 9.14 and
Section 9.7.15
2.9 - kHz
- PCM_SYNC frequency - 8
kHz
tmclkh(1) PCM_CLK high 4MHz DDS generation 980 - - ns
tmclkl(1) PCM_CLK low 4MHz DDS generation 730 - ns
- PCM_CLK jitter 48MHz DDS generation
21 ns pk-pk
tdmclksynch Delay time from PCM_CLK high to PCM_SYNC
high - - 20 ns
tdmclkpout Delay time from PCM_CLK high to valid PCM_OUT - - 20 ns
tdmclklsyncl Delay time from PCM_CLK low to PCM_SYNC low
(Long Frame Sync only) - - 20 ns
tdmclkhsyncl Delay time from PCM_CLK high to PCM_SYNC low - - 20 ns
tdmclklpoutz Delay time from PCM_CLK low to PCM_OUT high
impedance - - 20 ns
tdmclkhpoutz Delay time from PCM_CLK high to PCM_OUT high
impedance - - 20 ns
tsupinclkl Set-up time for PCM_IN valid to PCM_CLK low 30 - - ns
thpinclkl Hold time for PCM_CLK low to PCM_IN invalid 10 - - ns
Table 9.11: PCM Master Timing
Note:
(1) Assumes normal system clock operation. Figures will vary during low power modes, when system clock
speeds are reduced.
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Figure 9.34: PCM Master Timing Long Frame Sync
Figure 9.35: PCM Master Timing Short Frame Sync
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
MSB (LSB) LSB (MSB)
MSB (LSB) LSB (MSB)
fmlk
tmclkh tmclkl
tsupinclkl
tdmcl ksyn ch
tdmclkpout
thpinclkl
tdmcl kl syn cl
tdm cl khsyn cl
tdmclklpoutz
tdmclkhpoutz
tr,t f
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
MSB (LSB) LSB (MSB)
MSB (LSB) LSB (MSB)
fmlk
tmclkh tmclkl
tsup i ncl kl
t
tdm cl kpout
thp i ncl kl
dm cl khsyncl
tdm cl klp ou tz
tdmclkhpoutz
tr,t f
td mcl ksyn ch
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9.7.14 PCM Slave Timing
Symbol Parameter Min Typ Max Unit
fsclk PCM clock frequency (Slave mode: input) 64 - 2048 kHz
fsclk PCM clock frequency (GCI mode) 128 - 4096 kHz
tsclkl PCM_CLK low time 200 - - ns
tsclkh PCM_CLK high time 200 - - ns
thsclksynch Hold time from PCM_CLK low to PCM_SYNC high 30 - - ns
tsusclksynch Set-up time for PCM_SYNC high to PCM_CLK low 30 - - ns
tdpout Delay time from PCM_SYNC or PCM_CLK whichever is
later, to valid PCM_OUT data (Long Frame Sync only) - - 20 ns
tdsclkhpout Delay time from CLK high to PCM_OUT valid data - - 20 ns
tdpoutz Delay time from PCM_SYNC or PCM_CLK low, whichever
is later, to PCM_OUT data line high impedance - - 20 ns
tsupinsclkl Set-up time for PCM_IN valid to CLK low 30 - - ns
thpinsclkl Hold time for PCM_CLK low to PCM_IN invalid 30 - ns
Table 9.12: PCM Slave Timing
Figure 9.36: PCM Slave Timing Long Frame Sync
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN MSB (LSB) LSB (MSB)
fscl k
tsclkh tt scl kl
thscl ksynch tsu scl ksynch
tdpout tdsclkhpout tdpoutz
tdpoutz
tsu pi n scl kl th pi n scl kl
tr,t f
LSB (MSB)MSB (LSB)
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Figure 9.37: PCM Slave Timing Short Frame Sync
9.7.15 PCM_CLK and PCM_SYNC Generation
BlueCore3-ROM has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis (DDS) from BlueCore3-ROM internal 4MHz clock (which is
used in BlueCore3-ROM). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock which allows a
greater range of frequencies to be generated with low jitter but consumes more power. This second method is
selected by setting bit ‘48M_PCM_CLK_GEN_EN’ in PSKEY_PCM_CONFIG32.
Note:
The bit ‘SLAVE_MODE_EN’ should also be set. When in this mode and with long frame sync, the length of
PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by ‘LONG_LENGTH_SYNC_EN’ in
PSKEY_PCM_CONFIG32.
The Equation 9.8 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
Equation 9.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
Equation 9.9: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
MHz24
LIMIT_CNT
RATE_CNT
f×=
8LIMIT_SYNC
CLK_PCM
f×
=
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN MSB (LSB) LSB (MSB)
fscl k
tscl kh ttsclkl
thscl ksynch
tsuscl ksynch
tdpoutz
tdpoutz
tsu pi n scl kl thpinsclkl
tr,t f
LSB (MSB)
MSB (LSB)
td scl khp o ut
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9.7.16 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and
PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. PSKEY_PCM_CONFIG32.
The default for this key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame
sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tristating of
PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 9.14.
Name Bit Position Description
- 0 Set to 0.
SLAVE_MODE_EN 1
0 selects Master mode with internal generation of
PCM_CLK and PCM_SYNC. 1 selects Slave mode
requiring externally generated PCM_CLK and
PCM_SYNC. This should be set to 1 if
48M_PCM_CLK_GEN_EN (bit 11) is set.
SHORT_SYNC_EN 2
0 selects long frame sync (rising edge indicates start of
frame), 1 selects short frame sync (falling edge indicates
start of frame).
- 3 Set to 0.
SIGN_EXTEND_EN 4
0 selects padding of 8 or 13-bit voice sample into a 16-bit
slot by inserting extra LSBs, 1 selects sign extension.
When padding is selected with 13-bit voice sample, the 3
padding bits are the audio gain setting; with 8-bit
samples the 8 padding bits are zeroes.
LSB_FIRST_EN 5
0 transmits and receives voice samples MSB first, 1 uses
LSB first.
TX_TRISTATE_EN 6
0 drives PCM_OUT continuously, 1 tri-states PCM_OUT
immediately after the falling edge of PCM_CLK in the last
bit of an active slot, assuming the next slot is not active.
TX_TRISTATE_RISING_EDGE_EN 7
0 tristates PCM_OUT immediately after the falling edge
of PCM_CLK in the last bit of an active slot, assuming
the next slot is also not active. 1 tristates PCM_OUT after
the rising edge of PCM_CLK.
SYNC_SUPPRESS_EN 8
0 enables PCM_SYNC output when master, 1
suppresses PCM_SYNC whilst keeping PCM_CLK
running. Some CODECS utilise this to enter a low power
state.
GCI_MODE_EN 9 1 enables GCI mode.
MUTE_EN 10 1 forces PCM_OUT to 0.
48M_PCM_CLK_GEN_EN 11
0 sets PCM_CLK and PCM_SYNC generation via DDS
from internal 4 MHz clock, as for BlueCore3-ROM. 1 sets
PCM_CLK and PCM_SYNC generation via DDS from
internal 48 MHz clock.
LONG_LENGTH_SYNC_EN 12
0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1
sets length to 16 PCM_CLK cycles. Only applies for long
frame sync and with 48M_PCM_CLK_GEN_EN set to 1.
- [20:16] Set to 0b00000.
MASTER_CLK_RATE [22:21]
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz
PCM_CLK frequency when master and
48M_PCM_CLK_GEN_EN (bit 11) is low.
ACTIVE_SLOT [26:23] Default is ‘0001’. Ignored by firmware.
SAMPLE_FORMAT [28:27]
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit
sample with 16 cycle slot duration or 8 (0b11) bit sample
with 8 cycle slot duration.
Table 9.13: PSKEY_PCM_CONF IG32 Description
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Name Bit Position Description
CNT_LIMIT [12:0] Sets PCM_CLK counter limit.
CNT_RATE [23:16] Sets PCM_CLK count rate.
SYNC_LIMIT [31:24] Sets PCM_SYNC division relative to PCM_CLK.
Table 9.14: PSKEY_PCM_LOW_JITT E R_CONF IG Descrip tion
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9.8 I/O Parallel Ports
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered
from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_MEM.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines
are configured as inputs with weak pull-downs at reset.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general
use.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO [2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore3-ROM is provided from a system application specific integrated circuit (ASIC). Using
PSKEY_CLOCK_REQUEST_ENABLE, (0x246) this terminal can be configured to be low when BlueCore3-ROM
is in deep sleep and high when a clock is required. The clock must be supplied within 4ms of the rising edge of
PIO[6] or PIO[2] to avoid losing timing accuracy in certain Bluetooth operating modes.
BlueCore3-ROM has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2]. These are used
to access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip bandgap
reference voltage, the other two may be configured to provide additional functionality.
Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for
battery voltage measurement. Signals selectable at these pins include the bandgap reference voltage and a
variety of clock signals; 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals the
voltage range is constrained by the analogue supply voltage (1.8V). When configured to drive out digital level
signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by
VDD_MEM (1.8V).
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9.9 I2C Interface
PIO[8:6] can be used to form a Master I2C interface. The interface is formed using software to drive these lines.
Therefore it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (LCD),
keyboard scanner or EEPROM.
Notes:
PIO lines need to be pulled-up through 2.2kΩ resistors.
PIO[7:6] dual functions, UART bypass and EEPROM support, therefore devices using an EEPROM cannot
support UART bypass mode
For connection to EEPROMs, refer to CSR documentation on I2C EEPROMS for use with BlueCore. This
provides information on the type of devices which are currently supported.
Figure 9.38: Example EEPROM Connection
9.10 TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore3-ROM where either device
can turn on the clock without having to wake up the other device. PIO[3] can be used as the Host clock enable
input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore3-ROM.
BlueCore System
GSM System
TCXO
VDD
Enable
CLK IN
CLK IN
CLK REQ IN/
PIO[3]
CLK REQ OUT/
PIO[2]
CLK REQ OUT
Figure 9.39: Example TXCO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-stated. Therefore, the developer must
ensure that the circuitry connected to this pin is pulled via a 470k resistor to the appropriate power rail. This
ensures that the TCXO is oscillating at start up.
Seria l EEPROM
(AT24C16A)
4
3
2
1
5
6
7
8
PIO[8]
PIO[7]
PIO[6]
U2
VCC
WP
SCL
SDA
A0
A1
A2
GND
2.2KΩ2.2KΩ2.2KΩ
+1.8V
10nF
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9.11 RESET an d RESETB
BlueCore3-ROM may be reset from several sources: RESET or RESETB pins, power on reset, a UART break
character or via a software configured watchdog timer.
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A
reset will be performed between 1.5 and 4.0ms following RESET being active. CSR recommends that RESET is
applied for a period greater than 5ms. The RESETB pin is the active low version of RESET and is ‘ORed’ on-chip
with the active high RESET with either causing the reset function.
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when
VDD_CORE rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-stated. The PIOs have weak
pull-downs.
Following a reset, BlueCore3-ROM assumes the maximum XTAL_IN frequency which ensures that the internal
clocks run at a safe (low) frequency until BlueCore-ROM is configured for the actual XTAL_IN frequency. If no
clock is present at XTAL_IN, the oscillator in BlueCore3-ROM free runs, again at a safe frequency.
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9.11.1 Pin States on Reset
Table 9.15 shows the pin states of BlueCore3-ROM on reset.
Pin name State: BlueCore3-ROM
PIO[11:0] Input with weak pull-down
PCM_OUT Tri-stated with weak pull-down
PCM_IN Input with weak pull-down
PCM_SYNC Input with weak pull-down
PCM_CLK Input with weak pull-down
UART_TX Output tri-stated with weak pull-up
UART_RX Input with weak pull-down
UART_RTS Output tri-stated with weak pull-up
UART_CTS Input with weak pull-down
USB_DP Input with weak pull-down
USB_DN Input with weak pull-down
SPI_CSB Input with weak pull-up
SPI_CLK Input with weak pull-down
SPI_MOSI Input with weak pull-down
SPI_MISO Output tri-stated with weak pull-down
AIO[3:0] Output, driving low
RESET Input with weak pull-down
RESETB Input with weak pull-up
TEST_EN Input with strong pull-down
AUX_DAC High impedance
RX_IN High impedance
XTAL_IN High impedance, 250k to XTAL_OUT
XTAL_OUT High impedance, 250k to XTAL_IN
Table 9.15: Pin States of BlueCo re3-ROM on Reset
9.11.2 Status after Reset
The chip status after a reset is as follows:
! Warm Reset: Baud rate and RAM data remain available
! Cold Reset(1): Baud rate and RAM data not available
Note:
(1) Cold Reset consititutes one of the following:
! Power cycle
! System reset (firmware fault code)
! Reset signal, see Section 9.11
Device Terminal Descriptions
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9.12 Power Supply
9.12.1 Voltage Regulator
An on-chip linear voltage regulator can be used to power the 1.8V dependant supplies. It is advised that a
smoothing circuit using a 2.2μF low ESR capacitor and 2.2Ω resistor be placed on the output VDD_ANA.
VREG_EN is provided so that the regulator can be turned off when the line is pulled low.
The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the
on-chip regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to
VDD_ANA.
Important note
If BlueCore3-ROM Flash is being used as a development part to replicate BlueCore3-ROM functionality then
VREG_EN must be pulled high externally to replicate the ROM devices functionality. If VREG_EN is not
being used then connect pin VREG_EN to VREG_IN.
9.12.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO, VDD_VCO and VDD_MEM are powered at the same time.
The order of powering supplies for VDD_CORE, VDD_PIO, VDD_PADS and VDD_USB is not important.
However, if VDD_CORE is not present all inputs have a weak pull-down irrespective of the reset state.
9.12.3 Sensitivity to Disturbances
It is recommended that if you are supplying BlueCore3-ROM from an external voltage source that VDD_VCO,
VDD_ANA and VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. Single tone
frequencies are also to be avoided. A simple RC filter is recommended for VDD_CORE as this reduces transients
put back onto the power supply rails.
The transient response of the regulator is also important as at the start of a packet, power consumption will jump
to the levels defined in average current consumption section. It is essential that the power rail recovers quickly,
so the regulator should have a response time of 20μs or less.
Application Schematic
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10 Application Schematic
10.1 6 x 6mm VFBGA 84-Ball Package
Figure 10.1: Application Circuit for Radio Characteristics Specification for 6 x 6mm VFBGA Package
TX
TP1
AIO[1]
AIO[0]
RESET
UART_TX
UART_CTS
USB_DN
SPI_CSB
SPI_CLK
SPI_MISO
PCM_CLK
PCM_OUT
PCM_SYNC
SWITCH_RT
WHEEL_B
PWR_HOLD
E2SDA
E2WP
SCLK
PD
C11
15p
C13
2p2
2p2
C12
10n
C4
+1V8 +1V8
10n
C14 C5
10n
+1V8 +3V15
C1
2u2
+3V15
+1V8
26MHz
X1
WHEEL_EN
RESET
SPI_MOSI
UART_RX
USB_DP
SWITCH_LT
WHEEL_A
W2SCL
PCM_IN
SDIO
10p
C10
SWITCH_M/EFC
L3
3n9
L2
3n9
4
OUT
1IN
2GND 3
GND
MDR771F
U2
SMA-PCB-EDGE
J1
L1
22n
C6
15p
2R2
R2
C7
2u2
+1V8 +3V15
10n
C15
+1V8
3p3
C9
5 4
1 2 3
6
N/C
T1
HHM-1517
D2
VSS_RADIO
C1 VDD_RADIO
D9
VSS_PADS
A9 VDD_MEM
J2
VSS_A
N
A
K7
VDD_MEM
VSS_MEM
E10 VDD_CORE
B7
VSS_MEM
VSS_MEM
K9 VDD_USB
K6 VREG_I
N
K5
VREG_E
N
G3
VDD_PRG
J3 XTAL_OUT
F3
VSS
E2
VSS_RADIO
F2
VSS_RADIO
A1
VSS_PADS
H1 VDD_VCO
C2 VDD_RADIO
K4 VDD_A
N
A
K10
VSS_PADS J9
VSS_PADS
K2
VSS_A
N
A
E9
VSS_CORE
A6
VDD_MEM
H6 VDD_MEM
A7
VDD_MEM
J6
VDD_MEM
B8 FLASH_E
N
B10
A10
VSS_MEM
J7
B5
VSS_MEM
A3 VDD_PIO
D10 VDD_PADS
K3 XTAL_I
N
G2 VSS_VCO
H2 LOOP_FILTER
H4
AIO[0]
C6
TEST_EN
H8
UART_CTS
B9
SPI_MISO
H10
PCM_CLK
G10
PCM_SYNC
B2
PIO[1]
E8
PIO[4]
F9
PIO[7]
C4
PIO[10]
G1 VSS_VCO
D3 AUX_DAC
E1 TX_B
F1 TX_A
D1 RF_IN
J5
AIO[2]
C7
RESET D8
RESETB
H7
UART_RTS
H9
UART_RX J10
UART_TX
J8
USB_DP
G9
PCM_IN
C9
SPI_CSB
C8
SPI_MOSI
C10
SPI_CLK
G8
PCM_OUT
B1
PIO[0]
B4
PIO[3]
F10
PIO[6]
C3
PIO[9]
F8
PIO[5]
B3
PIO[2]
C5
PIO[8]
A2
VSS_PADS
H5
AIO[1]
K8
USB_DN
E3
PIO[11]
J4
VSS_A
N
A
TXEN
RXEN
BC313143A
U1
PCB Design and Assembly Considerations
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11 PCB Design and Assembly Considerations
11.1 VFBGA 84-Ball Package
The following list details the recommendations to achieve maximum board-level reliability of the BlueCore3-ROM
6 x 6mm VFBGA 84-ball package:
! Non solder mask defined (NSMD) lands – lands smaller than the solder mask aperture – are preferred,
because of the greater accuracy of the metal definition process compared to the solder mask process. With
solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land
interface, which can cause stress concentration and act as a point for crack initiation
! Ideally, via-in-pad technology should be employed to achieve truly NSMD lands. Where this is not possible, a
maximum of one trace connected to each land is preferred and this trace should be as thin as possible –
taking into consideration its current carrying and the radio frequency (RF) requirements
! 35 micron thick (1 oz.) copper lands are recommended rather than 17 micron thick (1/2 oz.), because this
results in a greater standoff which has been proven to provide greater reliability during thermal cycling
! Land diameter should be 260 microns +/-10 microns to achieve optimum reliability
! Solder paste is preferred to flux during the assembly process, as this adds to the final volume of solder in the
joint, increasing its reliability
! Where a nickel gold plating finish is used, the gold thickness should be kept below 0.5 microns in order to
prevent brittle gold/tin intermetallics forming in the solder
Package Dimensions
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12 Package Dimensions
12.1 6 x 6mm VFBGA 84-Ball Package
Figure 12.1: BlueCore3-ROM VFBGA Package Dimensions
Package Dimensions
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12.2 6.5 x 6.5mm VFBGA 84-Ball Package
Figure 12.2: BlueCore3-ROM Flash TFBGA Package Dimensions
6.5 x 6.5 x 1.2m m TFBG A
DIM MIN TYP MAX NOTES
A 1.2
A1 0.18 0.28
A2 0.21
DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER PAR ALLEL TO D ATUM PLANE Z
A3 0.7
B 0.27 0.37
D 6.5
DATUM Z IS DEFINED BY THE SPHERICAL CROWNS OF THE
SOLDER BA LLS
E 6.5
e 0.5
D1 4.5
PARALLELISM ME ASUREMENT SHALL EXCLUD E ANY
EFFECT OF MARK ON TOP SU RFACE OF PACAKGE
E1 4.5
UNIT
84-Ball TFBGA
6.5 x 6.5 x 1.2mm
(JEDEC M O-195) MM
Top View Bottom View
Solder Profiles
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13 Solder Profiles
The soldering profile depends on various parameters necessitating a set up for each application. The data here
is given only for guidance on solder re-flow. There are four zones:
1. Preheat Zone: This zone raises the temperature at a controlled rate, typically 1-2.5°C/s.
2. Equilibrium Zone: This zone brings the board to a uniform temperature and also activates the flux. The
duration in this zone (typically 2-3 minutes) will need to be adjusted to optimise the out gassing of the
flux.
3. Reflow Zone: The peak temperature should be high enough to achieve good wetting but not so high as
to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth
which can result in a brittle joint.
4. Cooling Zone: The cooling rate should be fast, to keep the solder grains small which will give a longer
lasting joint. Typical rates will be 2-5°C/s.
13.1 Example Solder Re-flow Profile for Devices with Lead-Free Solder Balls
Composition of the solder ball: Sn 95.5%, Ag 4.0%, Cu 0.5%
Figure 13.1: Typical Lead-F ree Re-flow Solder Profile
Key features of the profile:
! Initial Ramp = 1-2.5°C/sec to 175°C±25°C equilibrium
! Equilibrium time = 60 to 180 seconds
! Ramp to Maximum temperature (250°C) = 3°C/sec max.
! Time above liquidus temperature (217°C): 45-90 seconds
! Device absolute maximum reflow temperature: 260°C
Devices will withstand the specified profile.
Lead-free devices will withstand up to 3 reflows to a maximum temperature of 260°C.
Lead-F re e R e flo w So ld e r Pro file 2
0
50
100
150
200
250
300
0 50 100 150 200 250 300 350 400 450 500
Time (s)
Temperature (°C)
Solder Profiles
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13.2 Example Solder Re-Flow Profile for Devices with Tin / Lead Solder Balls
Composition of the solder ball: Sn 62%, Pb 36.0%, Ag 2.0%
Figure 13.2: Typical Re-flow Solder Profile
Key features of the profile:
! Initial Ramp = 1-2.5°C/sec to 125°C±25°C equilibrium
! Equilibrium time = 60 to 120 seconds
! Ramp to Maximum temperature (210°C to 220°C) = 3°C/sec max.
! Time above liquidus (183°C): 45 to 90 seconds
! Device absolute maximum re-flow temperature 240°C
Devices will withstand the specified profile.
Lead-free devices will withstand up to 3 re-flows to a maximum temperature of 240°C.
Leaded R eflow S older Profile 1
0
50
100
150
200
250
0 50 100 150 200 250 300 350 400
Time (s)
Temperature (°C)
Product Reliability Tests
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14 Product Reliability Tests
Die Test Conditions Specification Sample Size
ESD Human Body Model JEDEC 30
ESD Machine Model JEDEC 30
Latch-up ±200mA JEDEC 6
Early Life 125°C 48 – 168 hours 160
Hot Life Test 125°C 1000 hours 80 (73 FITs)
Package Test Conditions Specification Sample Size
Moisture Sensitivity
Precon
JEDEC Level 3
(125°C 24 hours)
30°C/60%RH
192 hours five re-flow
simulation cycles 231
Temperature Cycling -65°C to +150°C 500 cycles 77 from Precon
AutoClave (Steam) 121°C at 100% RH 96 hours 77 from Precon
Thermal Shock -55°C to 125°C 100 cycles 77 from Precon
Highly Accelerated Stress
Test 130°C at 85% RH 96 hours 77 from Precon (1)
High Temperature Storage 150°C 1000 hours 77
Note:
(1) Same material set as BlueCore2-ROM PnG
Ordering Information
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15 Ordering Information
15.1 BlueCore3-ROM
Package
Interface Version Type Size
Shipment
Method
Order Number
84-Ball VFBGA 6 x 6 x 1mm Tape and reel BC313143AXX-IEK-E4
UART and USB 84-Ball VFBGA
(Pb free) 6 x 6 x 1mm Tape and reel BC313143AXX-IRK-E4
Note:
XX denotes firmware type and firmware version status. These are determined on a customer and project
basis.
Minimum Order Quantity
2kpcs Taped and Reeled
15.2 BlueCore3-ROM Flash Software Prototyping Device
Package
Interface Version Type Size
Shipment
Method
Order Number
UART and USB 84-Ball TFBGA
(Pb free)
6.5 x 6.5 x
1.2mm Tape and reel BC31A159A-ES-ITK
Maximum Order Quantity
500pcs Taped and Reeled
Tape and Reel Information
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16 Tape and Reel Information
Tape and reel is in accordance with EIA-481-2.
16.1 Tape Orientation and Dimensions
The general orientation of the BGA in the tape is as shown in Figure 16.1.
Figure 16.1: Tape and Reel Orientation
User Direction of Feed
BGA
Circular Holes
Tape and Reel Information
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As a detailed example, the diagram shown in Figure 16.2 outlines the dimensions of the tape used for
6 x 6 x 1mm VFBGA devices:
Notes:
1. 10 sprocket hole pitch cumulative tolerance ± 02.
2. Camber not to exceed 1mm in 100mm.
3. Material: PS + C.
4. Ao and Bo measured as indicated.
5. Ko measured from a plane on the inside bottom of
the pocket to the top surface of the carrier.
6. Pocket position relative to sprocket hole measured as
true
p
osition of
p
ocket, not
p
ocket hole.
Ø1.5 +0.1/-0.0
Ø1.5 MIN
Ao = 6.3 mm
Bo = 6.3 mm
Ko = 1.1 mm
4.0
•See Note 1
12.0
0.25
R0.25
Bo
Ao
Ko
1.75
2.0
•See Note 6
0.30 ± 0.05
16.0 ± 0.
3
Direction of feed
Section A-A
7.5
•See Note 6
R0.3 MAX
BGA
Figure 16.2: Tape Dimensions
The cover tape has a total peel strength of 0.1N to 1.3N. The direction of the pull should be opposite in the
direction of the carrier tape such that the cover tape makes an angle of between 165° and 180° with the top of
the carrier tape. The carrier and/or cover tape should be pulled with a velocity of 300±10mm during peeling.
Maximum component rotation inside the cavity is 10° in accordance with EIA-481-2. The cavity pitch tolerance
(dimension P1) is ±0.1mm.
The reel is made of high impact injection molded polystyrene. The carrier tape is made of polystyrene with
carbon. The cover tape is made of antistatic polyester film and an antistatic heat activated adhesive coating.
Tape and Reel Information
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16.2 Reel Information
A
D
See Note 1
B
See Note 1
See Note 1
If present, tape slot in core
for tape start: 2.5mm min.
width x 10.0mm min. depth
Full Radius,
See Note 1 Access Hole at
Slot Location
(
∅
40 mm min.)
N
C
(Arbor hole
diameter)
W
3
(Includes flange distortio
n
at outer edge)
(Hub diameter,
see Note 2,
Table 1))
W2
(Measured at hub)
W1
(Measured at hub)
(All dimensions in millimeters)
R
ee
l
di
mens
i
ons
1. Drive spokes optional; if used , dimensions B and D shall apply.
2. Maximum weight of reel and contents 13.6kg.
Notes:
Figure 16.3: Reel Dimensions
Tape Width B Min C D Min N Min W1
16mm 1.5mm 13.0+0.5/-0.2mm 20.2mm 50mm 16.4+2.0/-0.0mm
Table 16.1: Reel Dimensions
Reel Diameter, A
330mm
Tape Size W2 Max W3
16mm 22.4mm 15.9mm Min
19.4mm Max
Table 16.2: Diameter Depen dent Dimensions
Tape and Reel Information
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16.3 Dr y Pack Information (6 x 6mm VFBGA 84-Ball Package Only)
The primary packed product is dry packed in accordance with Joint IPC / JEDEC J-STD-033.
All materials used in dry packing conform to EIA-541 and EIA-583.
Some illustrative views of reel dry packs are shown in Figure 16.4.
Humidity Indicator Card 10% ~ 30%
Desiccant: two units bags each containing 2 units of desiccant
Cube of pink foam to protect tape from crushing
Desiccant and Humidity Indicator Card are put on the bottom side of the
reel.
Position of label on reel.
Caution Label is printed on dry pack bag.
Dry pack bag.
Figure 16.4: Tape and Reel Packaging
Devices shipped in dry-pack bags will withstand storage in normal environmental conditions, such as 30°C and
70% RH for a minimum of one year as long as the dry-pack bag has not become punctured. Humidity indicators
inside the dry-pack bag will confirm this when the bag is opened.
Tape and Reel Information
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16.4 Baking Conditions
Devices may, if necessary, be re-baked at 125°C for 24 hours. If devices are still on the reel, which cannot
withstand such high temperatures, they should be baked at 45°C for 192 hours at relative humidity less than 5%.
Solder wettability of parts will be unaffected by three such bakes.
16.5 Product Information
Example product information labels are shown is Figure 16.5.
Figure 16.5: Product Information Labels
A product information label is placed on each reel, primary package and shipment package.
Contact Information
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17 Contact Information
CSR UK
Cambridge Science Park
Milton Road
Cambridge, CB4 0WH
United Kingdom
Tel: +44 (0) 1223 692 000
Fax: +44 (0) 1223 692 001
e-mail: sales@csr.com
CSR Denmark
Novi Science Park
Niels Jernes Vej 10
9220 Aalborg East
Denmark
Tel: +45 72 200 380
Fax: +45 96 354 599
e-mail: sales@csr.com
CSR U.S.
2425 N. Central Expressway
Suite 1000
Richardson
Texas 75080
USA
Tel: +1 (972) 238 2300
Fax: +1 (972) 231 1440
e-mail: sales@csr.com
CSR Korea
CSR Korea
2nd floor, Hyo-Bong Building
1364-1, SeoCho-dong
Seocho-gu
Seoul 137-863
Korea
Tel: + 82 2 3473 2372
Fax : +82 2 3473 2205
e-mail: sales@csr.com
CSR Taiwan
6th Floor, No. 407
Rui Guang Road
NeiHu, Taipei 114
Taiwan, R.O.C.
Tel: +886 2 7721 5588
Fax: +886 2 7721 5589
e-mail: sales@csr.com
CSR Japan
9F Kojimachi KS Square 5-3-3,
Kojimachi, Chiyoda-ku,
Tokyo 102-0083
Japan
Tel: +81 3 5276 2911
Fax: +81 3 5276 2915
e-mail: sales@csr.com
To contact a CSR representative, go to http://www.csr.com/contacts.htm
Document References
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18 Document References
Document Reference
Specification of the Bluetooth system v1.2, 0.95, 10 October 2002
Universal Serial Bus Specification v1.1, 23 September 1998
Selection of I2C™ EEPROMS for use with BlueCore bcore-an-008Pa, October 2002
Restrictions of Hazardous Substances RoHS directive 2002/95/EC
Terms and Definitions
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Terms and Definitions
BlueCore Group term for CSR’s range of Bluetooth chips
Bluetooth A set of technologies providing audio and data transfer over short-range radio connections
ACL Asynchronous Connection-Less. A Bluetooth data packet
AC Alternating Current
ADC Analogue to Digital Converter
AFH Adaptive Frequency Hopping
AGC Automatic Gain Control
AIO Asynchronous Input/Output
API Application Programming Interface
BCCMD BlueCore Command
BCSP BlueCore™ Serial Protocol
BER Bit Error Rate. Used to measure the quality of a link
BGA Ball Grid Array
BIST Built-In Self-Test
BMC Burst Mode Controller
C/I Carrier Over Interferer
CDMA Code Division Multiple Access
CMOS Complementary Metal Oxide Semiconductor
CODEC Coder Decoder
CQDDR Channel Quality Driven Data Rate
CSB Chip Select (Active Low)
CSR Cambridge Silicon Radio
CTS Clear to Send
CVSD Continuous Variable Slope Delta Modulation
DAC Digital to Analogue Converter
dBm Decibels relative to 1mW
DC Direct Current
DDS Direct Digital Synthesis
DFU Device Firmware Upgrade
EEPROM Electrically Erasable Programmable Read Only Memory
eSCO Extended Synchronous Connection-Oriented
ESR Equivalent Series Resistance
FSK Frequency Shift Keying
GCI General Circuit Interface
GSM Global System for Mobile communications
HCI Host Controller Interface
HV Header Value
I/O Input Output
IQ Modulation In-Phase and Quadrature Modulation
IF Intermediate Frequency
ISDN Integrated Services Digital Network
ISM Industrial, Scientific and Medical
ksamples/s kilosamples per second
Terms and Definitions
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L2CAP Logical Link Control and Adaptation Protocol (protocol layer)
LC Link Controller
LCD Liquid Crystal Display
LED Light Emitting Diode
LM Link Manager
LNA Low Noise Amplifier
LSB Least-Significant Bit
μ-law Audio Encoding Standard
MMU Memory Management Unit
MISO Master In Serial Out
NRE Non Recurring Engineering
NSMD Non Solder Mask Defined
OHCI Open Host Controller Interface
PA Power Amplifier
PCB Printed Circuit Board
PCM Pulse Code Modulation. Refers to digital voice data
PDA Personal Digital Assistant
PICS Protocol Implementation Conformance Statement
PIO Parallel Input Output
PLL Phase Lock Loop
ppm parts per million
PS Key Persistent Store Key
RAM Random Access Memory
RF Radio Frequency
RFCOMM Protocol layer providing serial port emulation over L2CAP
RISC Reduced Instruction Set Computer
rms root mean squared
ROM Read Only Memory
RoHS Restrictions of Hazardous Substances
RSSI Receive Signal Strength Indication
RTS Ready To Send
RX Receive or Receiver
SCO Synchronous Connection-Oriented. Voice oriented Bluetooth packet
SDK Software Development Kit
SDP Service Discovery Protocol
SIG Special Interest Group
SPI Serial Peripheral Interface
SSI Signal Strength Indication
TBA To Be Announced
TCXO Temperature Controlled crystal Oscillator
TFBGA Thin Fine-Pitch Ball Grid Array
TX Transmit or Transmitter
UART Universal Asynchronous Receiver Transmitter
UHCI Upper Host Control Interface
USB Universal Serial Bus or Upper Side Band (depending on context)
Terms and Definitions
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VCO Voltage Controlled Oscillator
VFBGA Very Fine Ball Grid Array
VM Virtual Machine
W-CDMA Wideband Code Division Multiple Access
Document History
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Document History
Date: Revision: Reason for Change:
11 FEB 03 a Original publication of Advance Information Product Data Sheet (CSR reference
BC313143A-ds-001Pa
JUL 03 b Pinout information for 6 x 6 VFBGA corrected.
SEP 03 c Radio Characterisation section updated to include design target figures for -20°C to
105°C temperature ranges.
OCT 03 d CSP Pinout information and RoHS statement added.
18 DEC 03 e Pinout information for 6 x 6 VFBGA modified
Device terminal descriptions layout brought inline with rest of BlueCore3 family
05 APR 04 f S-parameter data, RF characteristics and BlueCore3-ROM Flash added. Status
moved to Production
05 MAY 04 g Production information added.
07 MAY 04 h Ordering codes amended.
02 JUN 04 i Power consumption figure corrected for Master ACL with file transfer @115200
30 JUL 04 j BC31A159A-ES-ITK ordering code amended.
03 FEB 05 k Device diagrams and application schematic amended.
09 FEB 05 l Application schematic and pin-out information amended.
27 JUN 05 m
Linear Regulator maximum load current figure corrected in Electrical
Characteristics.
Input range for On-chip Linear Regulator amended in Key Features
Amended footnote to Linear Regulator table concerning VREG_IN and VREG_EN in
Electrical Characteristics.
Title of Record of Changes changed to Document History; Acronyms and Definitions
to Terms and Definitions
Updated copyright information in Status Information
07 JUL 05 n Updated Contact Information
BlueCore™3-ROM
Product Data Sheet
BC313143A-ds-001Pn
July 2005
