HY62UF16201 Series 128Kx16bit full CMOS SRAM PRELIMINARY DESCRIPTION FEATURES The HY62UF16201 is a high speed, low power and 2M bit full CMOS SRAM organized as 131,072 words by 16bit. The HY62UF16201 uses high performance full CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.5V. * Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(LL-part) - 1.5V(min) data retention * Standard pin configuration - 48ball uBGA Product Voltage Speed Operation Standby Current(uA) No. (V) (ns) Current(mA) LL-part HY62UF16201 3.0 85/100/120 15 15 HY62UF16201-I 3.0 85/100/120 15 15 Note 1. E.T. : Extended Temperature, Normal : Normal Temperature 2. Current value is max. A4 /CS IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 NC A7 IO4 Vcc A12 A15~A16 A8 A10 Vcc IO13 NC A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 A13 A14 A0 A3 A5 IO16 NC A12 A13 /WE IO8 NC A9 A8 A10 A11 NC A11 ROW DECODER MEMORY ARRAY 512x128x32 I/O1 OUTPUT BUFFER IO9 /UB A3 A9 WRITE DRIVER NC COLUMN DECODER A2 BLOCK DECODER A1 PRE-DECODER /OE A0 ADD INPUT BUFFER /LB ADD INPUT BUFFER A1,A2 A4, A6~A7 SENSE AMP BLOCK DIAGRAM ADD INPUT BUFFER PIN CONNECTION ( Top View ) Temperature (C) 0~70(Normal) -40~85(E.T.) I/O8 I/O9 I/O16 /CS /OE /LB /UB /WE PIN DESCRIPTION Pin Name /CS /WE /OE /LB /UB Pin Funtion Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A16 Vcc Vss NC Pin Funtion Data Input/Output Address Input Power(2.7V ~ 3.3V) Ground No Connection This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 /Mar.99 Hyundai Semiconductor HY62UF16201 Series ORDERING INFORMATION Part No. HY62UF16201LLM HY62UF16201LLM-I Speed 85/100/120 85/100/120 Power LL-part LL-part Temp. E.T. Package uBGA uBGA Note 1. E.T. : Extended Temperature, Blank : Normal Temperature ABSOLUTE MAXIMUM RATING (1) Symbol VIN, VOUT Vcc TA Parameter Input/Output Voltage Power Supply Operating Temperature TSTG PD TSOLDER Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.2 to 3.6 -0.5 to 4.6 0 to 70 -40 to 85 -55 to 150 200 260 * 10 Unit V V C C C mW C * sec Remark HY62UF16201 HY62UF16201-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.0 -0.2(1) Typ. 3.0 0 - Max. 3.3 0 Vcc+0.3 0.4 Unit V V V V Note : 1. VIL = -1.5V for pulse width less than 30ns TRUTH TABLE /CS /WE /OE /LB /UB H L L L X H X H X H X L X X H L H L L H L X X H H L L H L L L L Rev.03 /Mar.99 X Mode Not Selected Output Disabled Not Selected Read Write I/O Pin I/O1~I/O8 I/O9~I/O16 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z DOUT DOUT DOUT DIN Hi-Z Hi-Z DIN DIN DIN Supply Current ISB, ISB1 Icc ISB, ISB1 Icc1 Icc1 2 HY62UF16201 Series Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When UB is LOW, data is written or read to the Upper byte, I/O 9 -I/O 16. DC ELECTRICAL CHARACTERISTICS Vcc = 3.0V10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.) Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or /OE = VIH or /WE = VIL or /UB = VIH and /LB = VIH Icc Operating Power Supply /CS = VIL, VIN = VIH or VIL, Current II/O = 0mA ICC1 Average Operating Current /CS = VIL, Min Duty Cycle = 100% II/O = 0mA ISB TTL Standby Current /CS = VIH or /CS = VIL, (TTL Input) /UB, /LB = VIH ISB1 Standby Current /CS Vcc - 0.2V or (CMOS Input) /UB, /LB Vcc - 0.2V VOL Output Low Voltage Vcc = 3.0V IOL = 2.1mA VOH Output High Voltage Vcc = 3.0V IOH = -1.0mA Min. -1 -1 Typ. - Max. 1 1 Unit uA uA - 8 15 mA - - 80 mA - - 1 mA - - 15 uA 2.4 - 0.4 - V V Note : Typical values are at Vcc = 3.0V, TA = 25C Rev.03 /Mar.99 3 HY62UF16201 Series AC CHARACTERISTICS Vcc = 3.0V10%, TA = 0C to 70C (Normal)/ -40C to 85C (E.T.), unless otherwise specified -85 -10 -12 # Symbol Parameter Min. Max. Min. Max. Min Max. READ CYCLE 1 TRC Read Cycle Time 85 100 120 2 TAA Address Access Time 85 100 120 3 TACS Chip Select Access Time 85 100 120 4 TOE Output Enable to Output Valid 45 50 60 5 TBA /LB, /UB Access Time 85 100 120 6 TCLZ Chip Select to Output in Low Z 10 20 20 7 TOLZ Output Enable to Output in Low Z 5 5 10 8 TBLZ /LB, /UB Enable to Output in Low Z 10 10 10 9 TCHZ Chip Deselection to Output in High Z 0 30 0 30 0 40 10 TOHZ Out Disable to Output in High Z 0 30 0 30 0 40 11 TBHZ /LB, /UB Disable to Output in High Z 0 25 0 30 0 40 12 TOH Output Hold from Address Change 10 15 15 WRITE CYCLE 13 TWC Write Cycle Time 85 100 120 14 TCW Chip Selection to End of Write 70 80 100 15 TAW Address Valid to End of Write 70 80 100 16 TBW /LB, /UB Valid to End of Write 70 80 100 17 TAS Address Set-up Time 0 0 0 18 TWP Write Pulse Width 55 75 85 19 TWR Write Recovery Time 0 0 0 20 TWHZ Write to Output in High Z 0 30 0 35 0 40 21 TDW Data to Write Time Overlap 35 45 50 22 TDH Data Hold from Write Time 0 0 0 23 TOW Output Active from End of Write 5 10 10 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = 0C to 70C (Normal) / -40C to 85C (E.T.), unless otherwise specified PARAMETER Value Input Pulse Level 0.4V to 2.0V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 100pF + 1TTL Load Rev.03 /Mar.99 4 HY62UF16201 Series AC TEST LOADS VTM(2) 3070 Ohm DOUT CL(1) 3150 Ohm Note 1. Including jig and scope capacitance 2. VTM = 2.8V for Vcc = 3.0V : HY62UF16201-(I) CAPACITANCE (Temp = 25C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS, /WE, /UB, /LB, /OE) COUT Output Capacitance(I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF Note : These parameters are sampled and not 100% tested TIMING DIAGRAM READ CYCLE 1(Note 1) tRC ADDR tAA OE tOE tOH tOLZ(5) BC1 BC2 tOHZ(5) tACS, tBA tCLZ, tBLZ(5) Data Out Rev.03 /Mar.99 High-Z tCHZ, tBHZ(5) Data Valid 5 HY62UF16201 Series READ CYCLE 2(Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,3,4) BC1 BC2 tACS tCLZ(5) tCHZ(5) Data Out Data Valid Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. BC1 in high for the standby, low for active BC2 in high for the standby, low for active WRITE CYCLE 1 tWC ADDR tWR(2) tCW BC1 BC2 tAS tAW tAS tWP(1) WE tDW Data In tDH Data Valid tOHZ(3,9) Data Out Rev.03 /Mar.99 6 HY62UF16201 Series WRITE CYCLE 2 (Note 5) tWC ADDR tAW tCW tWR BC1 BC2 tAS tWP WE tDW Data In tDH Data Valid tWHZ tWHZ (6) (7) Data Out Notes: 1. A write occurs whenever a low on the /WE while /UB and/or /LB and /CS are in active state. 2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low(/OE=VIL) 6. Q(data out) is the same phase with the write data of this write cycle. 7. Q(data out) is the read data of the next address. 8. Transition is measured +200mV from steady state. This parameter is sampled and not 100% tested. 9. BC1 is high for the standby, low for active BC2 is high for the standby, low for active Rev.03 /Mar.99 7 HY62UF16201 Series DATA RETENTION ELECTRIC CHARACTERISTIC TA=0C to 70C (Normal)/-40C to 85C (E.T.) Symbol Parameter Test Condition VDR Vcc for Data Retention /CS Vcc - 0.2V ICCDR Data Retention Current Vcc = 2.0V, /CS Vcc - 0.2V, Vss < VIN < Vcc TCDR Chip Deselect to Data See Data Retention Timing Diagram Retention Time TR Operating Recovery Time Min 1.5 - Typ - Max 3.3 15 Unit V uA 0 - - ns tRC(2) - - ns Notes: 1. Typical values are under the condition of TA = 25C. 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 2.2V tCDR tR VIH VDR CS>VCC-0.2V CS VSS RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP Rev.03 /Mar.99 TEST SPEC. 2500V 250V < -200mA < 200mA 8 HY62UF16201 Series PACKAGE INFORMATION 48ball Micro Ball Grid Array Package(M) B A A1 CORNER INDEX AREA 6 5 4 3 2 1 A A B C D C C1 E 3.0 X 5.0 MIN FLAT AREA F G C1/2 H B1/2 B1 BUMP VIEW TOP VIEW 6 E1 E2 C E SEATING PLANE A 4 r 3 D(DIAMETER) SIDE VIEW Symbol A B B1 C C1 D E E1 E2 r Min. 6.65 9.2 0.3 0.85 0.6 0.2 - Typ. 0.75 3.75 6.7 5.25 9.25 0.35 0.9 0.65 0.25 - Max. 6.8 9.35 0.4 0.95 0.7 0.3 0.08 Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. SM-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. SOLDER BALL ARRAY MAY BE DEPOPULATED BY OMISSION BALLS FROM A FULL MATRIX. NO SHIFTING OF MATRIX PATTERN IS ALLOWED. 6. THIS IS A CONTROLLING DIMENSION. Rev.03 /Mar.99 9