SEPTEMBER 2008
DSC-3622/07
1
©2008 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆512K x 8 advanced high-speed CMOS Static RAM
◆◆
◆◆
◆JEDEC Center Power / GND pinout for reduced noise
◆◆
◆◆
◆Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
◆◆
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◆Single 3.3V power supply
◆◆
◆◆
◆One Chip Select plus one Output Enable pin
◆◆
◆◆
◆ Bidirectional data inputs and outputs directly
TTL-compatible
◆◆
◆◆
◆Low power consumption via chip deselect
◆◆
◆◆
◆Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O CONTROL
•
•
•
A
0
A
18
8
8
I/O
0
- I/O
7
8
CONTROL
LOGIC
WE
OE
CS
3622 drw 01
•
•
•
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
IDT71V424S/YS/VS
IDT71V424L/YL/VL
6.422
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
NC
NC
A9
A8
A7
WE
I/03
I/02
V
SS
V
DD
I/01
I/00
CS
A2
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A15
OE
I/07
I/06
V
SS
V
DD
I/05
I/04
A14
A13
A11
A10
NC
NC
NC
NC
A12
SO44-2
3622 drw 11
NC
NC
A3
A4
A6
A16
A17
A18
A0
A1
A2
A3
CS
I/O 0
V
DD
V
SS
I/O 2
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A18
A17
A16
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
A14
A13
A12
A11
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SO36-1
17
18 19
20
I/O 1
I/O3 I/O4
NC
A8
A9
A10
A15
3622 drw 02
SOJ
Top View
Pin Configuration
Truth Table(1,2)
Capacitance
(TA = +25°C, f = 1.0MH z, SOJ package)
Pin Configuration
TSOP
Top View
A
0
– A
18
Address Input s Input
CS Chip Se lect Inpu t
WE Write Enable Input
OE Output Enable Input
I/O
0
- I/O
7
Data Input/Output I/O
V
DD
3. 3V Pow e r Pow er
V
SS
G round Gnd
3622 tbl 02
Pin Description
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 8 pF
3622 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
CS OE WE I/O Function
LLHDATA
OUT Read Data
LXLDATA
IN Wri t e Da ta
L H H High-Z Output Disabled
H X X High-Z Deselected - Standby (ISB)
VHC
(3)
X X High-Z Deselected - Sta ndby (ISB1)
3622 tbl 01
NOTES:
1 . H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3 . Other inputs ≥VHC or ≤VLC.
6.42
3
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability. NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol Rating Value Unit
V
DD
Supply Voltage Relative to
V
SS
-0.5 to +4.6 V
V
IN
, V
OUT
Term inal Voltage Relativ e
to V
SS
-0.5 to V
DD
+0.5 V
T
BIAS
Tem perature Under Bias -55 to +125
o
C
T
STG
Storage Te mperature -55 to +125
o
C
P
T
Pow er D issipation 1 W
I
OUT
DC Out put Current 50 m A
3622 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage 3.0 3. 3 3. 6 V
V
SS
Ground 0 0 0 V
V
IH
In put H igh Voltage 2.0
____
V
DD
+0.3
(1)
V
V
IL
In put Low Volt age -0.3
(2)
____
0.8 V
3622 tbl 06
Grade Temperature V
SS
V
DD
C omme rcia l 0 ° C t o + 70 °C 0V Se e B e low
Ind ustrial –40° C t o +85° C 0V See Be low
3 622 tbl 0 5
Symbol Parameter Test Condition
IDT71V424
Min. Max. Unit
|I
LI
| Inp ut Leakage C urrent V
DD
= Max., V
IN
= V
SS
to V
DD
___
5µA
|I
LO
| O ut p ut L eakage C urrent V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5µA
V
OL
Output Low Voltage I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA, V
DD
= M in. 2.4
___
V
3622 tbl 0 7
Symbol Parameter
71V424S/ L 10 71V424S/L 12 71V424S /L 15 Unit
Com'l. Ind.
(5)
Com'l. Ind.
(5)
Com'l. Ind.
(5)
I
CC
Dynamic Ope rating Curre nt
CS < V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S 180 180 170 170 160 160 mA
L 165
___
155 155 145 145 mA
I
SB
Dynamic Standby Po wer S upply Curre nt
CS > V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S606055555050mA
L55
___
50 50 45 45 mA
I
SB1
Full Stand b y Po we r S up p ly Curre nt (static)
CS > V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S202020202020mA
L10
___
10 10 10 10 mA
3622 tb l 08
6.424
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
AC Test Loads
AC Test Conditions
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 3. Output Capacitive Derating
*Including jig and scope capacitance.
3622 drw 04
320Ω
350Ω5pF*
DATA
OUT
3.3V
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
∆t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3622 drw 05
•
•
•
•
•
•
•
+1.5V
50Ω
I/O Z
0
=50Ω
3622 drw 03
30pF
Input Pulse Levels
Input Rise/Fall Tim es
Input Tim ing Reference Levels
Output Reference Lev els
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3622 tbl 09
6.42
5
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
71V424S/L10
(2)
71V424S/L12 71V424S/L15
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Re ad Cy cle Tim e 10 ____ 12 ____ 15 ____ ns
t
AA
Addre ss A ccess Time ____ 10 ____ 12 ____ 15 ns
t
ACS
Ch ip Se lect Access T ime ____ 10 ____ 12 ____ 15 ns
t
CLZ
(1)
Ch ip S ele ct t o O u tp ut in Lo w -Z 4 ____ 4____ 4____ ns
t
CHZ
(1)
Chip Deselect to Output in High-Z ____ 5____ 6____ 7ns
t
OE
Ou t put Enable to Out put Valid ____ 5____ 6____ 7ns
t
OLZ
(1)
Out put Enable to Out put in Low -Z 0 ____ 0____ 0____ ns
t
OHZ
(1)
Out put Disable to Out put in High-Z ____ 5____ 6____ 7ns
t
OH
Out put Hold f rom Address Chan ge 4 ____ 4____ 4____ ns
t
PU
(1)
Chip Select to Pow er Up Tim e 0 ____ 0____ 0____ ns
t
PD
(1)
Chip Deselect t o Pow er Dow n Tim e ____ 10 ____ 12 ____ 15 ns
WRITE CYC LE
t
WC
Write Cycle Tim e 10 ____ 12 ____ 15 ____ ns
t
AW
Ad dress Valid t o En d of Writ e 8 ____ 8____ 10 ____ ns
t
CW
Ch ip Se lect to En d o f Writ e 8 ____ 8____ 10 ____ ns
t
AS
Addre ss S et-up Tim e 0 ____ 0____ 0____ ns
t
WP
Writ e Pu lse Widt h 8 ____ 8____ 10 ____ ns
t
WR
Write R e cove ry T ime 0 ____ 0____ 0____ ns
t
DW
Da t a Va lid t o End of Write 6 ____ 6____ 7____ ns
t
DH
Data Hold Time 0 ____ 0____ 0____ ns
t
OW
(1)
Output Active from End of Write 3 ____ 3____ 3____ ns
t
WHZ
(1)
Write Enable t o O utput in High-Z ____ 6____ 7____ 7ns
3622 t bl 10
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0ºC to +70ºC temperature range only for low power 10ns (L10) speed grade.
AC Electrical Characteristics
(VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
6.426
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1, 2, 4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
3622 drw 06
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
DATA
OUT
ADDRESS
3622 drw 07
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
6.42
7
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4 . If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW
write period.
5. Transition is measured ±200mV from steady state.
ADDRESS
CS
WE
DATA
OUT
DATA
IN
3622 drw 08
(5)
(2)
(5)
(5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
(3)(3)
CS
ADDRESS
DATA
IN
3622 drw 09
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
6.428
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Ordering Information
6.42
9
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Datasheet Document History
8/13/99 Updated to new format
Pg. 2 Removed SO44-1 from TSOP pinout
Pg. 7 Revised footnotes on Write Cycle No. 1 diagram
Removed footnote for tWR on Write Cycle No. 2 diagram
Pg. 9 Added Datasheet Document History
8/31/99 Pg. 1–9 Added Industrial temperature range offerings
11/22/02 Pg. 8 Added die revision option to ordering information
07/31/03 Pg. 8 Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y.
07/28/04 Pg. 3 Increased ISB for all "L" and S15 speeds by 10mA and increased for S12 speed by 5mA (refer to
PCN# SR-0402-02).
Pg. 8 Added "Restricted hazardous substance device" to the ordering information.
09/20/08 Pg. 1, 8 Added Y and V step part numbers to front page and ordering information. Updated the ordering
information by removing the “IDT” notation.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
