32K x 8 Reprogrammable Registered PROM
CY7C277
Cypress Semiconductor Corporation • 3901 North F irs t Street • San Jose • CA 95134 • 408-94 3-2 600
Document #: 38-04006 Rev. *B Revised December 27, 2002
1CY7C277
Features
• Window ed for reprogramm abi lity
• CMOS for optimum speed/power
• High speed
—30-ns address set-up
—15-ns clock to output
• Low power
—60 mW (commercial)
—715 mW (military)
• Programmable address latch enable input
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered output registers
• EPROM technology, 100% programmable
• Slim 300-mil, 28-pin plastic or hermetic DIP
•5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
PROGRAMMABLE
MULTIPLEXER
PROGRAMMABLE
CP/ALEOPTIONS
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A10
A11
A12
A13
A14
ALE
CP
E/ES
O7
O6
O4
O5
O3
15
A14
A13
A12
A11
A10
A9
A8
8-BIT
1 OF 128
MUX
A7
A6
A5
A4
A3
A2
A1
A0
E/ES
CP
15-BIT
ADDRESS
TRANSPARENT/
LATCH
256 x 1024
PROGRAMMABLE
ARRAY
8-BIT
EDGE-
TRIGGERED
REGISTER
ROW
DECODER
1OF256
ALE
COLUMN
DECODER
1OF32
ALE
CP
D
C
Q
DIP/Flatpack
Top View
Y
ADDRESS
X
ADDRESS
O7
O6
O5
O4
O3
O2
O1
O0
Selection Guide
7C277-30 7C277-40 Unit
Minimum Address Set-Up Time 30 40 ns
Maximum Clock to Output 15 20 ns
Maxi mu m Op er at ing
Current Com’l 120 mA
Mil 130 mA
CY7C277
Document #: 38-04006 Rev. *B Page 2 of 8
Functional Description
The CY7C277 is a high-performance 32 K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package.
The ceramic package may be equipped with an erasure
window; when exposed to UV light, the PROM is erased and
can then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
locatio n is writ ten into, era sed, and repea tedly ex ercis ed prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that the product will meet DC and AC
specification limits after customer programming.
On the CY7C277, the outputs are pipelined through a
master-s lave regi ster. On the risi ng edge of CP, dat a is lo aded
into the 8-bit edge triggered output register. The E/ES input
provide s a pr ogra mmable bit to selec t betwee n a synchro nous
and synchronous operation. The default condition is
async hronous. Wh en the asynch ronous mo de is sele cted, the
E/ES pin operates as an asynchronous output enable. If the
synch ronous mode i s selected, t he E/ES pin is sa mpled on th e
rising edge of CP to enable and disable the outputs. The
7C277 also provides a programmable bit to enable the
Address Latch input. If this bit is not programmed, the device
will ignore the ALE pin and the address will enter the device
asynchronously. If the ALE function is selected, the address
enters the PROM while the AL E pin is active, and is captured
when ALE is deasserted. The user may define the polarity of
the ALE signal, with the default being active HIGH.
Maximum Ratings[1]
(Above whi ch the us eful li fe m ay be im p a ired . Fo r us er g uid e-
lines, not tes ted .)
Storage Temperature ....................................−65°C to +150°C
Ambient Temper atu re with
Power Applied.................................................−55°C to +125°C
Supply Voltag e to Ground Potential.................−0.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z Sta te.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure...................................................7258 Wsec/cm2
Stat ic Discha rge Volt ag e..... ...... .................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[2] −55°C to +125°C 5V ±10%
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
7C277-30 7C277-40
Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min ., IOH = − 2.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min ., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical HIGH
Voltage for All Inputs 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Logical LOW
Voltage for All Inputs 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 µA
VCD Input Clamp Diode Voltage Note 4
IOZ Output Leakage Current 0 < VOUT < VCC, Output Disabled[5] −40 +40 −40 +40 µA
IOS Output Short Circuit Current VCC = Max ., VOUT = 0.0V[6] −20 −90 −20 −90 mA
ICC Power Supply Current VCC = Max., CS > VIH
IOUT = 0 mA Commercial 120 mA
Military 130
VPP Programming Supply Voltage 12 13 12 13 V
IPP Programming Supply Current 50 50 mA
VIHP Input HIGH Programming Voltage 3.0 3.0 V
VILP Input LOW Programming Voltage 0.4 0.4 V
Notes:
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is the “inst ant on” case te mperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C277
Document #: 38-04006 Rev. *B Page 3 of 8
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 5.0 V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms[4]
3.0V
5V
OUTPUT
R1 500Ω
R2
333Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns <5ns
5V
OUTPUT
R1 500Ω
R2
333Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) NormalLoad (b) HighZ Load
OUTPUT 2.0V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
(658Ω MIL)
(403Ω MIL) (403Ω MIL)
OUTPUT 1.9V
Commercial Military
(658Ω MIL)
200Ω250Ω
CY7C277 Switching Characteristics Over the Operating Range[3, 4]
7C277-30 7C277-40
Parameter Description Min. Max. Min. Max. Unit
tAL Address Set-Up to ALE Inactive 510 ns
tLA Address Hold from ALE Inactive 10 10 ns
tLL ALE Pulse Width 10 10 ns
tSA Address Set-Up to Clock HIGH 30 40 ns
tHA Address Hold from Clock HIGH 0 0 ns
tSES ES Set-Up to Cloc k HIGH 12 15 ns
tHES ES Hold from Clock HIGH 510 ns
tCO Clock HIGH to Output Valid 15 20 ns
tPWC Clock Pulse Width 15 20 ns
tLZC[7] Output Valid from Clock HIGH 15 20 ns
tHZC Output High Z from Clock HIGH 15 20 ns
tLZE[8] Output Valid from E LOW 15 20 ns
tHZE[8] Output High Z from E HIGH 15 20 ns
Notes:
7. Applies only when the synchronous (ES) f uncti on is u sed.
8. Applies only when the asynchronous (E) fu nctio n is us ed.
CY7C277
Document #: 38-04006 Rev. *B Page 4 of 8
Architecture Byte (8000)
D7 D0
C7C6C5C4 C3 C
2 C
1 C
0
Architecture Configuration Bits
Architecture Bit Architecture Verify D7–D0Function
ALE D10 = DEFAULT Input Transparent
1 = PGMED Input Latched
ALEP D20 = DEFAULT ALE = Active HIGH
1 = PGMED ALE = Active LOW
E/ESD00 = DEFAULT Asynchronous Output Enable (E)
1 = PGMED Synchronous Output Enable (ES)
Bit Map
Programme r Address
(Hex.) RAM Data
0000
.
.
.
7FFF
8000
Data
.
.
.
Data
Control Byte
Note:
9. ALE is shown with positive polarity.
tHZE tLZE
tSES
tSES
tLZC
tHZC
tCO
tHES tHES
HIGHZHIGHZ
tAL tLA
tLL
tSA tHA
A0–A14
ALE
ES
(SYNCH)
CP
O0–O7
ES
(ASYNCH)
tPWC
tPWC
Timing Diagram (Input Latched)
[9]
tLZE
tHZE
tSES
tHZC
Timing Diagram (Input Transparent)
tSES
tLZC
tCO
tHES tHES
HIGHZ HIGHZ
tSA tHA
A0–A14
ES
(SYNCH)
CP
O0–O7
ES
(ASYNCH)
tPWC
tPWC
CY7C277
Document #: 38-04006 Rev. *B Page 5 of 8
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Progr amming algorithms can
be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function[10]
Read or Output Disable A14–A0E, ESCP ALE O7–O0
Mode Other A14–A0VFY PGM VPP D7–D0
Read A14–A0VIL VIH VIL O7–O0
Output Disable A14–A0VIH X X High Z
Program A14–A0VIHP VILP VPP D7–D0
Program Verify A14–A0VILP VIHP/VILP VPP O7–O0
Pro gram Inhibit A14–A0VIHP VIHP VPP High Z
Blank Check A14–A0VILP VIHP/VILP VPP O7–O0
Note:
10. X = “don’t care” but not to exceed VCC ±5%.
Figure 1. Programming Pinouts
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
A10
A11
A12
A13
A14
VPP
PGM
VFY
D7
D6
D4
D5
D3
15
DIP
Top View
CY7C277
Document #: 38-04006 Rev. *B Page 6 of 8
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUP PLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C)
0.6
1.2
NORMALIZED ACCESS TIME
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I
CC
NORMALIZED I
CC
VCC =5.0V
TA=25°C
60
50
40
30
20
10
0 1.0 2.0 3.0
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPA CITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
0
OUTPUT SOURCE CURRENT
vs. VOLTAGE
4.0
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET - UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
0.4
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SU PPLY VO LTA GE
TA=25°C
1.0
0.8
0.6
C277-12
CY7C277
Document #: 38-04006 Rev. *B Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other ri ghts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-suppor t systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
All product and company names mentioned in this document may be the trademarks of their respective holders.
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
30 CY7C277-30WC W22 28-Lead (300-Mil) Windowed CerDIP Commercial
40 CY7C277-40WMB W22 28-Lead (300-Mil) Windowed CerDIP Military
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
Package Diagrams
28-Lead
(300-Mil)
Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087-**
CY7C277
Document #: 38-04006 Rev. *B Page 8 of 8
Document History Page
Document Title: CY7C277 32K x 8 Programmable Registered PROM
Document Number: 38-04006
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113862 3/8/02 DSG Change from Spec number: 38-00085 to 38-04006
*A 118901 10/09/02 GBI U pda te orde ring inform ati on
*B 122247 12/27/02 RBI Add power up requirements to Operating Conditions information
