OM13053,598 - NXP SEMICONDUCTORS

UM10601

LPC81x User manual

Rev. 1.6 — 2 April 2014 User manual

Document information

Info Content

Keywords ARM Cortex M0+, LPC800, LPC800 UM, LPC81x, LPC81x UM, USART,

I2C, LPC811M001JDH16, LPC812M101JDH16, LPC812M101JD20,

LPC812M101JDH20, LPC810M021FN8, LPC812M101JTB16

Abstract LPC81x user manual

User manual Rev. 1.6 — 2 April 2014 2 of 370

NXP Semiconductors UM10601

LPC81x User manual

Revision history

Rev Date Description

1.6 20140402 LPC81x user manual

PDF output size corrected.

1.5 20140306 LPC81x user manual

Modifications: •Table 147 “SCT configuration example” corrected.

•Figure 43 “Boot ROM structure” corrected.

1.4 20140207 LPC81x user manual

Modifications: •Editorial updates in the SPI chapter. Bit FLEN renamed to LEN in the TXDATCTL and TXCTL registers.

•Bit description of the FRAME_DELAY bit in the SPI DELAY register updated. See Table 205.

•Chapter 2 9 “LPC81x Code examples” added.

•SCT behavior in undefined state described in Section 10.7.5.

•Clarify write access to the following registers in the SCT: COUNT, STATE, MATCH, FRACMAT, and

OUTPUT. Writes are only allowed when the counter is halted.

•Clarify repeated access to SCT CTRL register.

•Reset value of the SYSAHBCLKCTRL register corrected. See Table 30.

•Part LPC812M101JTB16 added.

•Code examples corrected in Chapter 23 “LPC81x Power profile API ROM driver”, Chapter 25 “LPC81x

USART API ROM driver routines”, and Chapter 24 “LPC81x I2C-bus ROM API” to comply with

LPCOpen code.

•Remark about 5 V tolerance added for digital pins with confi gurable open-drain mode. See

Section 6.4.4.

•Description of the EVn_STATE register clarified. See Table 142 “SCT event state mask registers 0 to 5

(EV[0:5]_STATE, addresses 0x5000 4300 (EV0 _STATE) to 0x5000 4328 (EV5_STATE)) bit

description”.

•Description of SLEEPFLAG bit corrected in the PCON register. Reading a 1 indicates that the part was

in sleep, deep-sleep, or power-down mode before wake-up. See Table 55 “Register overview: PMU

(base address 0x4002 0000)”.

•Added recommendation to use a software delay after power-up of the system oscillator. See

Section 4.6.32 “Power configuration register”.

•Section 4.7.1 “Reset”, Section 4.7.2 “Start-up behavior”, Section 4.7.3 “Brown-out detection” added for

clarity.

•Description of Go command clarified. See Section 22.5.1.8 “Go <address> <mode>”.

•Description of the ARM STIR register removed. This register is no t implemented in the ARMv6-M

architecture.

•Name “SCT” changed to “SCTimer/PWM” for clarity where appropriate throughout the document.

•Behavior of data stalls for different settings of the SPI TXDAT CT L re gister bit EOT clarified.

Section 17.6.7 “SPI Transmitter Data and Control register”.

•Add clock frequency parameter to IAP commands “Copy RAM to flash”, “Erase page”, and “Erase

sector”. Table 258, Table 259, Table 266. This parameter has been removed in error in v. 1.3.

•Description of MRT one-shot bus stall mode added. See Section 11.5.3 “One-shot bus stall mode” and

Table 151 “Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 403 8 (CTRL3)) bit

description”.

User manual Rev. 1.6 — 2 April 2014 3 of 370

NXP Semiconductors UM10601

LPC81x User manual

1.3 20130722 LPC800 user manual

Modifications: •More explanation added to the SPI Transmitter data and control register. See Table 211.

•Changed the ISP entry pin from PIO0_1 to PIO0_12 for TSSOP and SOP packages. See Table 234

“LPC800 flash and ISP configurations” and Table 232 “Pin locatio n in ISP mode”.

•Requirement added for entering low power modes: switch the main clock source to IRC before entering

Deep-sleep and Power-down modes. See Section 5.5, Section 5.7.5.2, and Section 5.7.6.2.

•Section 3.4 added.

•Type numbers updated throughout the document to reflect new operating temperature range. See

Table 1 “Ordering information” and Ta ble 2 “Ordering options”.

•Boot Rom revision updated. See Tabl e 231 “Boot loader versions”.

•Description of boot loader updated. See Section 21.5.1.

•ADDRDET bit description corrected in Table 175 “USART Control register (CTL, address 0x4006 4004

(USART0), 0x4006 8004 (USART1), 0x4006 C004 (USART2)) bit description”. 0 = disabled, 1 =

enabled.

•Remove clock frequency parameter from IAP commands “Copy RAM to flash”, “Erase page”, and

“Erase sector”. See Section 22.5.2 “IAP commands”.

•IDLE bit renamed to MSTIDLE in Section 17.6.3 “SPI Status register”.

•Update IAP description. See Section 22.5.2 “IAP commands”.

•Editorial updates. Some register and bit na mes corrected.

1.2 20130314 LPC800 user manual

Modifications: •Editorial updates.

•Table 53 “PLL configuration examples” upda ted.

•Register bit description of Table 105 “Pattern match bit-slice source register (PMSRC, address 0xA000

402C) bit description” updated.

•Chapter 5 “LPC800 Reduced power modes and Power Management Unit (PMU)” updated.

•Section 5.3.1 “Low power modes in the ARM Cortex-M0+ core” added.

•Removed dependency on system frequency for flash access times in Table 227 “Flash configuration

•Instructions on how to prevent floating internal pins added. See Section 6.3.

•Figure 31 “I2C clocking” updated.

•Description of the NMISRC register updated. See Section 4.6.26 “NMI source selection register”.

•Section 16.3.1 “I2C transmit/receive in master mode” added.

•Chapter 14 “LPC800 ARM Cortex SysTick Timer (SysTick)” added.

•Address offset of the DEVICE_ID register corrected. See Table 51 “Device ID register (DEVICE_ID,

address 0x4004 83F8) bit description”.

•BOD reset level 0 changed to reserved in Table 41 “BOD control register (BODCTRL, address 0x4004

8150) bit description”.

Revision history …continued

Rev Date Description

User manual Rev. 1.6 — 2 April 2014 4 of 370

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors UM10601

LPC81x User manual

1.1 20130124 LPC800 user manual

Modifications: •Flash signature creation al gorithm corrected. See Section 19.5.1 “Flash signature generation”.

•System PLL output frequency restricted to < 100 MHz.

•MTB register memory space changed to 1 kB in Figure 2 “LPC800 Memory mapping”.

•Description of the External trace buffer command register updated. See Section 4.6.20 “External trace

buffer command register”.

•Flash interrupt removed in Table 3.

•Chapter 27 summarizing the ARM Cortex-M0+ instruction set added.

•ISP Read CRC checksum command added. See Section 21.5.1.15 “Read CRC checksum <address>

<no of bytes>”.

•Section 20.3.1 “Boot loader versions” added.

•MRT implementation changed to 31-bit timer. See Chapter 11. Bit description of Table 140 “Idle

channel register (IDLE_CH, address 0x4000 40F4) bit de scription” corrected.

•Updates for clarification in Chapter 17 “LPC800 SPI0/1”.

•Updates for clarification in Chapter 16 “LPC800 I2C-bus interface”.

•Updates for clarification in Chapter 15 “LPC800 USART0/1/2”.

•Updates for clarification in Chapter 8 “LPC800 Pin interrupts/pattern match engine”.

•Updates for clarification in Section 9.4 (switch matrix-to-pin functional diagram).

•Updates for clarification in Chapter 5 “LPC800 Reduced power modes and Power Management Unit

(PMU)”.

•Section 3.3.2 “Non-Maskable Interrupt (NMI)” and Section 3.3.3 “Vector table offset” added.

•Bit fields corrected in Section 10.6.

•USART baudrate clock output removed from USART features.

1 20121109 Preliminary LPC800 user manual

Revision history …continued

Rev Date Description

User manual Rev. 1.6 — 2 April 2014 5 of 370

1.1 Introduction

The LPC81x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC81x support up to 16 kB of flash memory and

4 kB of SRAM.

The peripheral comple ment of the LPC81x includes a CRC engine, on e I2C-bus interface,

up to three USARTs, up to two SPI interfaces, one multi-rate timer , self wake-up timer , and

state-configura ble timer, one comparator, function-configurable I/O port s th rough a switch

matrix, an input pattern match engine, and up to 18 general-purpose I/O pins.

For additional documentation related to this part see Section 30.2 “References”.

1.2 Features

•System:

–ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with

single-cycle multiplier and fast sing le-cycle I/O port.

–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

–System tick timer.

–Serial Wire Debug (SWD) and JTAG boundary scan modes (BSDL) supported.

–Micro Trace Buffer (MTB) supported.

•Memory:

–Up to 16 kB on-chip flash programming memory with 64 Byte page write and

erase.

–4 kB SRAM.

•ROM API support:

–Boot loader.

–USART drivers.

–I2C drivers.

–Power profiles.

–Flash In-Applica tio n Pro gra mm in g (IAP) and In-System Pro gr a mm in g (ISP ).

•Digital peripherals:

–High-speed GPIO in te r face connected to the ARM Cort ex -M 0 + IO bu s with up to

18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter.

–High-current source output driver (20 mA) on four pins.

–High-current sink driver (20 mA) on two true open-drain pins.

–GPIO interrupt generation capability with boolean pattern-matching feature on

eight GPIO inputs.

–Switch matrix for flexible configuration of each I/O pin function.

UM10601

Chapter 1: LPC81x Introductory information

Rev. 1.6 — 2 April 2014 User manual

User manual Rev. 1.6 — 2 April 2014 6 of 370

NXP Semiconductors UM10601

Chapter 1: LPC81x Introductory information

–State Configurable Timer (SCTimer/PWM or SCT) with input and output functions

(including captur e an d ma tch) assigned to pins through the switch matrix.

–Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

–Self Wake-up Timer (WKT) clocked from either the IRC or a low-power,

low-frequency internal oscillator.

–CRC engine.

–Windowed Watchdog timer (WWDT).

•Analog peripherals:

–Compara tor with external voltage reference with pin functions assigned or enabled

through the switc h ma tr ix.

•Serial interfaces:

–Three USART interfaces with pin functions assigned through the switch matrix.

–Two SPI controllers with pin functions assigned through the switch matrix.

–One I2C-bus interface with pin functions assigned through the switch matrix.

•Clock generation :

–12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

–Crystal oscillator with an operating range of 1 MHz to 25 MHz.

–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

–10 kHz low-power oscillator for the WKT.

–PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input CLKIN, or the internal RC oscillator.

–Clock output function with div ider that can reflect the cry stal oscillator, the main

clock, the IRC, or the watchdog oscillator.

•Power control:

–Integrated PMU (Power Management Unit) to minimize power consumption.

–Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

–Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,

and I2C peripherals.

–Timer-controlled self wake-up from Deep power-down mode.

–Power-On Reset (POR).

–Brownout detect.

•Unique device serial number for identification.

•Single power supply.

•Operating temperature range -40 °C to 105 °C except for the DIP8 package, which is

available for a temperature range of -40 °C to 85 °C

•Available as DIP8, XSON16, TSSOP16, SO20, and TSSOP20 package.

User manual Rev. 1.6 — 2 April 2014 7 of 370

NXP Semiconductors UM10601

Chapter 1: LPC81x Introductory information

1.3 Ordering information

Ta ble 1. Ordering information

Type number Package

Name Description Version

LPC810M021FN8 DIP8 plastic dual in-l ine package; 8 leads (300 mil) SOT097-2

LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

LPC812M101JD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

LPC812M101JTB16 XSON16 plastic extremely thin small outline package; no leads; 16 terminals; body

2.5  3.2  0.5 mm SOT1341-

Table 2. Ordering options

Type number Flash/kB SRAM/kB USART I2CSPI Comparator GPIO Package

LPC810M021FN8 4 1 2 1 1 1 6 DIP8

LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16

LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16

LPC812M101JD20 16 4 2 1 1 1 18 SO20

LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20

LPC812M101JTB16 16 4 3 1 2 1 14 XSON16

User manual Rev. 1.6 — 2 April 2014 8 of 370

NXP Semiconductors UM10601

Chapter 1: LPC81x Introductory information

1.4 Block diagram

Fig 1. LPC81x block di ag ram

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User manual Rev. 1.6 — 2 April 2014 9 of 370

NXP Semiconductors UM10601

Chapter 1: LPC81x Introductory information

1.5 General description

1.5.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in

the core are the NVIC an d Ser ial Wir e Deb ug with four b re akpoints and two watch points.

The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO

access at address 0xA000 0000. The ARM Cortex M0+ core revision is r0p0.

The core includes a single-cycle multiplier and a system tick timer (SysT ick).

User manual Rev. 1.6 — 2 April 2014 10 of 370

2.1 How to read this chapter

The memory mapping is identical for all LPC81x parts. Different LPC81x parts support

different flash and SRAM memory sizes.

2.2 General description

The LPC81x incorporates several distinct m em o ry regio n s. Figure 2 shows the overall

map of the entire address space from the user program viewpoint following reset.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral is allocated 16 kB of space simplifying the address decoding.

The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and

sleep mode contr ol, ar e loc at ed on the pr iva te pe rip h er al bu s.

The GPIO port and pin interrupt/pattern match registers are accessed by the ARM

Cortex-M0+ single-cycle I/O enabled port (IOP).

UM10601

Chapter 2: LPC81x Memory mapping

Rev. 1.6 — 2 April 2014 User manual

User manual Rev. 1.6 — 2 April 2014 11 of 370

NXP Semiconductors UM10601

Chapter 2: LPC81x Memory mapping

2.2.1 Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC81x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 26.5.4.

The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.

Fig 2. LPC81x Memory mapping

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User manual Rev. 1.6 — 2 April 2014 12 of 370

3.1 How to read this chapter

The NVIC is identical on all LPC81x parts.

The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and

LPC812M101FDH16 only.

3.2 Features

•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.

•Tightly coupled interrupt controller provides low interrupt latency.

•Controls system exceptions and peripheral interrupts.

•The NVIC supports 32 vectored interrupts.

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation using the ARM exceptions SVCall and PendSV (see

Ref. 3).

•Support for NMI .

•ARM Cortex M0+ Vector table offset register VTOR implemented.

3.3 General description

The Nested V ectore d Interrupt Controller (NVIC) is an integral p art of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

3.3.1 Interrupt sources

Table 3 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. Interrupts with the same priority level are

serviced in the order of their interrupt number.

See Ref. 3 for a detailed description of the NVIC and the NVIC register description.

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(NVIC)

Rev. 1.6 — 2 April 2014 User manual

Table 3. Co nnection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

0 SPI0_IRQ SPI0 interrupt See Table 207 “SPI Interrupt Enable read and Set register

(INTENSET, addresses 0x4005 800 C (SPI0) , 0x4005 C00C

(SPI1)) bit description”.

1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ

2 - Reserved -

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3 UART0_IRQ USART0 interrupt See Table 176 “USART Interrupt Enable read and set register

(INTENSET, address 0x4006 400C (USART0), 0x4006 800C

(USART1), 0x4006 C00C (USART2)) bit description”

4 UART1_IRQ USART1 interrupt Same as UART0_IRQ

5 UART2_IRQ USART2 interrupt Same as UART0_IRQ

6 - Reserved -

7 - Reserved -

8 I2C0_IRQ I2C0 interrupt See Table 190 “Interrupt Enable Clea r register (INTENCLR,

address 0x4005 000C) bit description”.

9 SCT_IRQ State configurable timer

interrupt EVFLAG SCT event

10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt.

GFLAG0

GFLAG1

GFLAG2

GFLAG3

11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit

12 WDT_IRQ Windowed watchdog timer

interrupt WARNINT - watchdog warning interrupt

13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level

14 - - Reserved

15 WKT_IRQ Self wake-up timer interrupt ALARMFLAG

23:16 - Reserved -

24 PININT0_IRQ Pin interrupt 0 or pattern

match engine slice 0

interrupt

PSTAT - pin interrupt status

25 PININT1_IRQ Pin interrupt 1 or pattern

match engine slice 1

interrupt

PSTAT - pin interrupt status

26 PININT2_IRQ Pin interrupt 2 or pattern

match engine slice 2

interrupt

PSTAT - pin interrupt status

27 PININT3_IRQ Pin interrupt 3 or pattern

match engine slice 3

interrupt

PSTAT - pin interrupt status

28 PININT4_IRQ Pin interrupt 4 or pattern

match engine slice 4

interrupt

PSTAT - pin interrupt status

Table 3. Co nnection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

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3.3.2 Non-Maskable Interrupt (NMI)

The LPC81x supports the NMI, which can be triggered by an peripheral interrupt or

triggered by software. The NMI has the highest priority exception other than the reset.

You can set up any peripheral interrupt listed in Table 3 as NMI using the NMISRC register

in the SYSCON block (Table 43). To avoid using the same peripher al interrupt as NMI

exception and normal interrupt, disable the interrupt in the NVIC when you configure it as

NMI.

3.3.3 Vector table offset

The vector ta ble contains the reset value of the st ack pointer and the star t addresses, also

called exception vectors, for all exception handlers. On system reset, the vector table is

located at address 0x0000 0000. Software can write to the VTOR register in the NVIC to

relocate the vector table start address to a different memory location. For a description of

the VTOR register, see Ref. 5.

29 PININT5_IRQ Pin interrupt 5 or pattern

match engine slice 5

interrupt

PSTAT - pin interrupt status

30 PININT6_IRQ Pin interrupt 6 or pattern

match engine slice 6

interrupt

PSTAT - pin interrupt status

31 PININT7_IRQ Pin interrupt 7 or pattern

match engine slice 7

interrupt

PSTAT - pin interrupt status

Table 3. Co nnection of interrupt sources to the NVIC

Interrupt

number Name Description Flags

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3.4 Register description

The NVIC registers are located on the ARM private peripheral bus.

3.4.1 Interrupt Set Enable Register 0 register

The ISER0 register allows to enable peripheral interrupts or to read the enabled state of

those interrupts. Disable interrupts through the ICER0 (Section 3.4.2).

Table 4. Register overview: NVIC (base address 0xE000 E000)

Name Access Address

offset Description Reset

value Reference

ISER0 RW 0x100 Interrupt Set Enab le Register 0. This register allows enabling

interrupts and reading back the interrupt enables for specific

peripheral functi ons.

0Table 5

- - 0x104 Reserved. - -

ICER0 RW 0x180 I nterrupt Clear Enable Register 0. This register allows disabling

interrupts and reading back the interrupt enables for specific

peripheral functi ons.

0Table 6

- - 0x184 Reserved. 0 -

ISPR0 RW 0x200 Interrupt Set Pending Register 0. This register allows changing the

interrupt state to pending and reading back the interrupt pending

state for specific peripheral functions.

0Table 7

- - 0x204 Reserved. 0 -

ICPR0 RW 0x280 Interrupt Clear Pending Register 0. This register allows changing the

interrupt state to not pending and reading back the interrupt pending

state for specific peripheral functions.

0Table 8

- - 0x284 Reserved. 0 -

IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the

current interrupt active state for specific peripheral functions. 0Table 9

- - 0x304 Reserved. 0 -

IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 0 to 3.

0Table 10

IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 4 to 7.

0Table 11

IPR2 RW 0x408 Interrupt Priority Registers 2. This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 8 to 11.

0Table 12

IPR3 RW 0x40C Interrupt Priority Registers 3. This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 12 to 15.

0Table 13

- - 0x410 Reserved. 0 -

- - 0x414 Reserved. 0 -

IPR6 RW 0x418 Interrupt Priority Registers 6. This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 24 to 27.

0Table 14

IPR7 RW 0x41C Interrupt Priority Registers 7. This register allows assigning a priority

to each interrupt. This register contains the 2-bit priority fields for

interrupts 28 to 31.

0Table 15

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The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 enables the interrupt.

Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrup t is enabled.

3.4.2 Interrupt clear enable register 0

The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled

state of those interrupts. Enable interrupts through the ISER0 registers (Section 3.4.1).

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 disables the interrupt.

Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrup t is enabled.

Table 5. Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit

description

Bit Symbol Description Reset value

0 ISE_SPI0 Interrupt enable. 0

1 ISE_SPI1 Interrupt enable. 0

2- Reserved. -

3 ISE_UART0 Interrupt enable. 0

4 ISE_UART1 Interrupt enable. 0

5 ISE_UART2 Interrupt enable. 0

6- Reserved. -

7- Reserved. -

8 ISE_I2C Interrupt enable. 0

9 ISE_SCT Interrupt enable. 0

10 ISE_MRT Interrupt enable. 0

11 ISE_CMP Interrupt enable. 0

12 ISE_WDT Interrupt enable. 0

13 ISE_BOD Interrupt enable. 0

14 ISE_FLASH Interrupt enable. 0

15 ISE_WKT Interrupt enable. 0

23:16 - Reserved. -

24 ISE_PININT0 Interrupt enable. 0

25 ISE_PININT1 Interrupt enable. 0

26 ISE_PININT2 Interrupt enable. 0

27 ISE_PININT3 Interrupt enable. 0

28 ISE_PININT4 Interrupt enable. 0

29 ISE_PININT5 Interrupt enable. 0

30 ISE_PININT6 Interrupt enable. 0

31 ISE_PININT7 Interrupt enable. 0

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3.4.3 Interrupt Set Pending Register 0 register

The ISPR0 registe r allo ws se tting th e pe nd in g state of the per iph er al int er rupts, or for

reading the pendin g state of those inte rrupts. Clea r the pending st ate of interrupt s through

the ICPR0 registe rs (Section 3.4.4).

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.

Read — 0 indicates that the interrupt is not pending, 1 indicates th at th e int er ru pt is

pending.

Table 6. Interr up t clear enable register 0 (ICER0, address 0xE000 E180)

Bit Symbol Description Reset value

0 ICE_SPI0 Interrupt disable. 0

1 ICE_SPI1 Interrupt disable. 0

2 - Reserved. -

3 ICE_UART0 Interrup t disa ble. 0

4 ICE_UART1 Interrup t disa ble. 0

5 ICE_UART2 Interrup t disa ble. 0

6 - Reserved. -

7 - Reserved. -

8 ICE_I2C Interrupt disable. 0

9 ICE_SCT Interrupt disable. 0

10 ICE_MRT Interrupt disable. 0

11 ICE_CMP Interrupt disable. 0

12 ICE_WDT Interrupt disable. 0

13 ICE_BOD I nterrupt disable. 0

14 ICE_FLASH Interrupt disable. 0

15 ICE_WKT Interrupt disable. 0

23:16 - Reserved. -

24 ICE_PININT0 Interrupt disable. 0

25 ICE_PININT1 Interrupt disable. 0

26 ICE_PININT2 Interrupt disable. 0

27 ICE_PININT3 Interrupt disable. 0

28 ICE_PININT4 Interrupt disable. 0

29 ICE_PININT5 Interrupt disable. 0

30 ICE_PININT6 Interrupt disable. 0

31 ICE_PININT7 Interrupt disable. 0

Table 7. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit

description

Bit Symbol Description Reset value

0 ISP_SPI0 Interrupt pending set. 0

1 ISP_SPI1 Interrupt pending set. 0

2 - Reserved. -

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3.4.4 Interrupt Clear Pending Register 0 register

The ICPR0 register allows clearing the pending state of the peripheral interrupts, or for

reading the pend in g state of thos e int er ru pts. Set the pe ndin g state of inter ru p ts through

the ISPR0 register (Section 3.4.3).

The bit description is as follows for all bits in this register:

Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.

Read — 0 indicates that the interrupt is not pending, 1 indicates th at th e int er ru pt is

pending.

3 ISP_UART0 Interrupt pending set. 0

4 ISP_UART1 Interrupt pending set. 0

5 ICE_UART2 Interrupt pending set. 0

6 - Reserved. -

7 - Reserved. -

8 ISP_I2C Interrupt pending set. 0

9 ISP_SCT Interrupt pending set. 0

10 ISP_MRT Interrupt pending set. 0

11 ISP_CMP Interrupt pending set. 0

12 ISP_WDT Interrupt pending set. 0

13 ISP_BOD Interrupt pending set. 0

14 ISP_FLASH Interrupt pending set. 0

15 ISP_WKT Interrupt pending set. 0

23:16 - Reserved. -

24 ISP_PININT0 Interrupt pending set. 0

25 ISP_PININT1 Interrupt pending set. 0

26 ISP_PININT2 Interrupt pending set. 0

27 ISP_PININT3 Interrupt pending set. 0

28 ISP_PININT4 Interrupt pending set. 0

29 ISP_PININT5 Interrupt pending set. 0

30 ISP_PININT6 Interrupt pending set. 0

31 ISP_PININT7 Interrupt pending set. 0

Table 7. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit

description …continued

Bit Symbol Description Reset value

Table 8. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit

description

Bit Symbol Function Reset value

0 ICP_SPI0 Interrupt pending clear. 0

1 ICP_SPI1 Interrupt pending clear. 0

2- Reserved. -

3 ICP_UART0 Interrupt pending clear. 0

4 ICP_UART1 Interrupt pending clear. 0

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3.4.5 Interrupt Active Bit Register 0

The IABR0 register is a read-only register that allows reading the active st ate of the

peripheral interrupts. Use this register to determine which peripherals are asserting an

interrupt to the NV IC an d ma y als o be pend i ng if there ar e en a ble d.

The bit description is as follows for all bits in this register:

Write — n/a.

Read — 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

5 ICP_UART2 Interrupt pending clear. 0

6- Reserved. -

7- Reserved. -

8 ICP_I2C Interrupt pending clear. 0

9 ICP_SCT Interrupt pending clear. 0

10 ICP_MRT Interrupt pending clear. 0

11 ICP_CMP Interrupt pending clear. 0

12 ICP_WDT Interrupt pending clear. 0

13 ICP_BOD Interrupt pending clear. 0

14 ICP_FLASH Interrupt pending clear. 0

15 ICP_WKT Interrupt pending clear. 0

23:16 - Reserved. -

24 ICP_PININT0 Interrupt pending clear. 0

25 ICP_PININT1 Interrupt pending clear. 0

26 ICP_PININT2 Interrupt pending clear. 0

27 ICP_PININT3 Interrupt pending clear. 0

28 ICP_PININT4 Interrupt pending clear. 0

29 ICP_PININT5 Interrupt pending clear. 0

30 ICP_PININT6 Interrupt pending clear. 0

31 ICP_PININT7 Interrupt pending clear. 0

Table 8. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit

description …continued

Bit Symbol Function Reset value

Table 9. Interr up t Active Bit Register 0 (IABR0, address 0xE000 E300) bit description

Bit Symbol Function Reset value

0 IAB_SPI0 I nter rupt active. 0

1 IAB_SPI1 I nter rupt active. 0

2- Reserved. -

3 IAB_UA RT0 Interrupt acti ve . 0

4 IAB_UA RT1 Interrupt acti ve . 0

5 IAB_UA RT2 Interrupt acti ve . 0

6- Reserved. -

7- Reserved. -

8 IAB_I2C I nt errupt active. 0

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3.4.6 Interrupt Priority Register 0

The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

3.4.7 Interrupt Priority Register 1

The IPR1 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

9 IAB_SCT Inter rupt active. 0

10 IAB_MRT Interrupt active. 0

11 IAB_CMP Int errupt active. 0

12 IAB_WDT Interrupt active. 0

13 IAB_BOD Interrupt active. 0

14 IAB_FLASH Interrupt active. 0

15 IAB_WKT Interrupt active. 0

23:16 - Reserved. -

24 IAB_PININT0 Interrupt active. 0

25 IAB_PININT1 Interrupt active. 0

26 IAB_PININT2 Interrupt active. 0

27 IAB_PININT3 Interrupt active. 0

28 IAB_PININT4 Interrupt active. 0

29 IAB_PININT5 Interrupt active. 0

30 IAB_PININT6 Interrupt active. 0

31 IAB_PININT7 Interrupt active. 0

Table 9. Interr up t Active Bit Register 0 (IABR0, address 0xE000 E300) bit description

Bit Symbol Function Reset value

Table 10. Interrupt Priority Register 0 (IPR0, address 0xE000 E400) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_SPI0 In terru pt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_SPI1 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

21:16 - These bits ignore writes, and read as 0.

23:22 - Reserved.

29:24 - These bits ignore writes, and read as 0.

31:30 IP_UART0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

Table 11. Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_UART1 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_UART2 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

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3.4.8 Interrupt Priority Register 2

The IPR2 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

3.4.9 Interrupt Priority Register 3

The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

21:16 - These bits ignore writes, and read as 0.

23:22 - Reserved.

29:24 - These bits ignore writes, and read as 0.

31:30 - Reserved.

Table 11. Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description

Bit Symbol Description

Table 12. Interrupt Priority Register 2 (IPR2, address 0xE000 E408) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_I2C Interrupt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_SCT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

21:16 - These bits ignore writes, and read as 0.

23:22 IP_MRT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

29:24 - These bits ignore writes, and read as 0.

31:30 IP_CMP Interrupt Priority. 0 = highest priority. 3 = lowest priority.

Table 13. Interrupt Priority Register 3 (IPR3, address 0xE000 E40C) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_WDT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_BOD Interrupt Priority. 0 = highest priority. 3 = lowest priority.

21:16 - These bits ignore writes, and read as 0.

23:22 IP_FLASH Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

29:24 - These bits ignore writes, and read as 0.

31:30 IP_WKT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

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3.4.10 Interrupt Priority Register 6

The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

3.4.11 Interrupt Priority Register 7

The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can

have one of 4 priorities, where 0 is the highest priority.

Table 14. Interrupt Priority Register 6 (IPR6, address 0xE000 E418) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_PININT0 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_PININT1 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

21:16 - These bits ignore writes, and read as 0.

23:22 IP_PININT2 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

29:24 - These bits ignore writes, and read as 0.

31:30 IP_PININT3 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

Table 15. Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description

Bit Symbol Description

5:0 - These bits ignore writes, and read as 0.

7:6 IP_PININT4 Interrupt Priority. 0 = highest priority. 3 = lowest priority.

13:8 - These bits ignore writes, and read as 0.

15:14 IP_PININT5 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

21:16 - These bits ignore writes, and read as 0.

23:22 IP_PININT6 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

29:24 - These bits ignore writes, and read as 0.

31:30 IP_PININT7 Interrupt Priority. 0 = highest priority. 3 = lowe st priority.

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4.1 How to read this chapter

The system configuration block is identical for all LPC81x parts. USART2 and SPI1 are

only available on parts LPC812M101JDH20 and LPC812M101JDH16 and the corresponding

clocks, reset, and wake-up control bits are reserved for all other parts.

4.2 Features

•Clock control

–Configure the system PLL.

–Configure system oscillator and watchdog oscillator.

–Enable clocks to individual peripherals and memories.

–Configure clock output.

–Configure clock dividers, digital filter clock, and USART bau d rate clock.

•Monitor and release reset to individual peripherals.

•Select pins for external pin interrupts and pattern match engine.

•Configuration of reduced power modes.

•Wake-up control.

•BOD configuration.

•MTB trace start and stop.

•Interrupt latency control.

•Select a source for the NMI.

•Calibrate system tick timer.

4.3 Basic configuration

Configure the SYSCON block as follows:

•The SYSCON uses the CLKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure

the pin functions through the switch matrix. See Section 4.4.

•No clock configuration is needed . The clock to the SYSCON bl ock is always enabled.

By default, the SYSCON block is clocked by the IRC.

4.3.1 Set up the PLL

The PLL creates a stable output clock at a higher frequency than the input clock. If you

need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to

boost the input frequency.

1. Power up the system PLL in the PDRUNCFG register.

Section 4.6.32 “Power configuration register”

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2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input

options:

–IRC: 12 MHz internal oscillator.

–System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.

–External clock input CLKIN. Select this pin through the switch matrix.

Section 4.6.8 “System PLL clock source select register”

3. Update the PLL clock source in the SYSPLLCLKUEN register.

Section 4.6.9 “System PLL clock source update register”

4. Configure the PLL M and N dividers.

Section 4.6.3 “System PLL control register”

5. Wait for the PLL to lock by monitoring the PLL lock status.

Section 4.6.4 “System PLL status registe r”

4.3.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main

clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL.

The divided main clock is called the system clock and clocks the core, the memories, and

the peripherals (register interfaces and peripheral clocks).

1. Select the main clock. You have the following options:

–IRC: 12 MHz internal oscillator (default).

–PLL output: You must configure the PLL to use the PLL output.

Section 4.6.10 “Main clock source select register”

2. Update the main clock source.

Section 4.6.11 “Main clock s ourc e up da te en ab le re gis te r”

3. Select the divider value for the system clock. A divider value of 0 disables th e system

clock.

Section 4.6.12 “System clock divider register”

4. Select the memories and peripherals that are operating in your application and

therefore must have an active clock. The core is always clocked.

Section 4.6.13 “System clock control register”

4.3.3 Set up the system oscillator using XTALIN and XTALOUT

If you want to use the system oscillator with the LPC81x, you need to assign the XTALIN

and XTALOUT pins, which connect to th e external crystal, throug h the fixed-pin function in

the switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and

PIO0_9.

1. In the IOCON block, remove the pull-up and pull-down resistors in the IOCON

registers for pins PIO0_8 and PIO0_9.

2. In the switch matrix block, enable the 1-bit functions for XTALIN and XTALOUT.

3. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator

frequency range according to the desired oscillator output clock.

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Related registers:

Table 75 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description”

Table 74 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description”

Table 118 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description”

Table 22 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description”

4.4 Pin description

The SYSCON inputs and output s are assigned to external pins through the switch matrix.

See Section 9.3.1 “Connect an internal signal to a package pin” to assign the CLKOUT

function to a pin on the LPC81x package.

See Section 9.3.2 to enable the clock input, the oscillator pins, and the external reset

input.

4.5 General description

4.5.1 Clock generation

The system control block generates all clocks for the chip. Only the low-power oscillator

used for wake-up timing is controlled by the PMU. Except for the USART clock and the

clock to configure the glitch filters of the digital I/O pins, the clocks to the core and

peripheral s run at the same fr eq uen cy. The maximum system clock frequency is 30 MHz.

See Figure 3.

Remark: The main clock frequency is limited to 100 MHz.

Table 16. SYSCON pin description

Function Direction Pin Description SWM register Reference

CLKOUT O any CLKOUT clock output. PIN ASSIGN8 Table 117

CLKIN I PIO0_1/ACMP_I2/CLKIN External clock input to the system

PLL. Disable the ACMP_I2 function

in the PINENABLE register.

PINENABLE0 Table 118

XTALIN I PIO0_8/XTALIN Input to the system oscillator. PINENABLE0 Table 118

XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 118

RESET I RESET/PIO0_5 External reset input PINENABLE0 Table 118

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4.5.2 Power control of analog components

The system control block controls the power to the analog components such as the

oscillators and PLL, the BOD, and the analog comparator. For details, see the following

registers:

Section 4.6.30 “Deep-sleep mode configuration register”

Section 4.6.3 “System PLL control register”

Section 4.6.6 “Watchdog oscillator control register”

Section 4.6.5 “System oscillator control register”

Fig 3. LPC81x clock generatio n

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User manual Rev. 1.6 — 2 April 2014 27 of 370

NXP Semiconductors UM10601

Chapter 4: LPC81x System configuration (SYSCON)

4.5.3 Configuration of reduced power-modes

The system control block configures ana log blocks that can remain running in the reduced

power modes (the BOD and the watchdog oscillator for safe operation) and enables

various interrupts to wake up the chip when the internal clocks are shut down in

Deep-sleep and Power-down modes. For details, see the following registers:

Section 4.6.32 “Power configuration register”

Section 4.6.29 “Start logic 1 interrupt wake-up enable register”

4.5.4 Reset and interrupt control

The peripheral reset control register in the system control register allows to assert and

release individual peripheral resets. See Table 19.

Up to eight external pin interrupts can be assigned to any digital pin in the system control

block (see Section 4.6.27 “Pin interrupt select registers”).

4.6 Register description

All system control block registers reside on word address bo undaries. Details of the

registers appear in the description of each function.

Reset values describe the content of the registers after the boot loader has executed.

All address offsets not shown in Table 17 are reserved and should not be written to.

Table 17 . Register overview: System configuration (base address 0x4004 8000)

Name Access Offset Description Reset value Reference

SYSMEMREMAP R/W 0x000 System memory remap 0x2 Table 18

PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 1FFF Table 19

SYSPLLCTRL R/W 0x008 System PLL control 0 Table 20

SYSPLLSTAT R 0x00C System PLL status 0 Table 21

- - 0x010 Reserved - -

- - 0x014 Reserved - -

SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 22

WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 Table 23

- - 0x028 Reserved - -

- - 0x02C Reserved - -

SYSRSTSTAT R/W 0x030 System reset status register 0 Table 24

SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 Table 25

SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 Table 26

MAINCLKSEL R/W 0x070 Main clock source select 0 Table 27

MAINCLKUEN R/W 0x074 Main clock source update enable 0 Table 28

SYSAHBCLKDIV R/W 0x078 System clock divider 1 Table 29

SYSAHBCLKCTRL R/W 0x080 System clock control 0xDF Table 30

UARTCLKDIV R/W 0x094 USART clock divider 0 Table 31

- - 0x098 Reserved - -

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Chapter 4: LPC81x System configuration (SYSCON)

- - 0x09C Reserved - -

- - 0x0A0 -

0x0BC Reserved - -

- - 0x0CC Reserved - -

CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 Table 32

CLKOUTUEN R/W 0x0E4 CLKOUT clock source update ena ble 0 Table 33

CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 Table 34

UARTFRGDIV R/W 0x0F0 USART1 to USART4 common fractional

generator divider value 0Table 35

UARTFRGMULT R/W 0x0F4 USART1 to USART4 common fractional

generator multiplier value 0Table 36

EXTTRACECMD R/W 0x0FC External trace buffer command register 0 Table 37

PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent Table 38

- - 0x104 Reserved - -

IOCONCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

IOCONCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCON block for

programmable glitch filter 0x0000 0000 Table 39

BODCTRL R/W 0x150 Brown-Out Detect 0 Table 40

SYSTCKCAL R/W 0x154 System tick counter calibration 0x0 Table 41

- R/W 0x168 Reserved - -

IRQLATENCY R/W 0x170 IQR delay. Allows trade-off between interrupt

latency and determinism. 0x0000 0010 Table 42

NMISRC R/W 0x174 NMI Source Control 0 Table 43

PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 Table 44

PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 Table 44

PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 Table 44

PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 Table 44

PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 Table 44

PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 Table 44

PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 Table 44

PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 Table 44

STARTERP0 R/W 0x204 Start logic 0 pin wake-up enable register 0 Table 45

Table 17 . Register overview: System configuration (base address 0x4004 8000) …continued

Name Access Offset Description Reset value Reference

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.1 System memory remap register

The system memory remap register selects whether the exception vectors are read from

boot ROM, flash, or SRAM. By default, the flash memory is mapped to address

0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1,

the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory

map (addresses 0x0000 0000 to 0x0000 0200).

4.6.2 Peripheral reset control register

The PRESETCTRL register allows software to reset specific peripherals. A zero in any

assigned bit in this register reset s the specified peripheral. A 1 clear s the reset and allows

the peripheral to operate.

STARTERP1 R/W 0x214 Start logic 1 interrupt wa ke-up enable

PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF Table 47

PDAWAKECFG R/W 0x234 Power-down states for wake-up from

deep-sleep 0xEDF0 Table 48

PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 Table 49

DEVICE_ID R 0x3F8 Device ID part dependent Table 50

Table 17 . Register overview: System configuration (base address 0x4004 8000) …continued

Name Access Offset Description Reset value Reference

Table 18. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit Symbol Value Description Reset

value

1:0 MAP System memory remap. Value 0x3 is reserved. 0x2

0x0 Bo ot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

0x1 U ser RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

0x2 U ser Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

31:2 - - Reserved -

Table 19. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

0 SPI0_RST_N SPI0 reset control 1

0 Assert the SPI0 reset.

1 Clear the SPI0 reset.

1 SPI1_RST_N SPI1 reset control 1

0 Assert the SPI1 reset.

1 Clear the SPI1 reset.

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2 UARTFRG_RST_N USART fractional baud rate generator

(UARTFRG) reset control 1

0 Assert the UARTFRG reset.

1 Clear the UARTFRG reset.

3 UART0_RST_N USART0 reset control 1

0 Assert the USART0 reset.

1 Clear the USART0 reset.

4 UART1_RST_N USART1 reset control 1

0 Assert the USART reset.

1 Clear the USART1 reset.

5 UART2_RST_N USART2 reset control 1

0 Assert the USART2 reset.

1 Clear the USART2 reset.

6 I2C_RST_N I2C reset control 1

0 Assert the I2C reset.

1 Clear the I2C reset.

7 MRT_RST_N Multi-rate timer (MRT) reset control 1

0 Assert the MRT reset.

1 Clear the MRT reset.

8 SCT_RST_N SCT reset control 1

0 Asse r t the SCT reset.

1 Clear the SCT reset.

9 WKT_RST_N Self wake-up timer (WKT) reset control 1

0 Asse r t the WKT reset.

1 Clear the WKT reset.

10 GPIO_RST_N GPIO and GPIO pin interrupt reset control 1

0 Asse r t the GPIO reset.

1 Clear the GPIO reset.

11 FLASH_RST_N Flash controller reset control 1

0 Assert the flash controller reset.

1 Clear the flash controller reset.

12 ACMP_RST_N Analog comparator reset control 1

0 Asser t the analog comparator reset.

1 Clear the analog comparator controller reset.

31:13 - - Reserved -

Table 19. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.3 System PLL control register

This register conne ct s and e nables the system PL L and configur es the PLL multiplie r and

divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various

clock sources. The input frequency is multiplied to a higher frequency and then divided

down to provide the actual clock used by the CPU, peripherals, and memories. The PLL

can produce a clock up to the maximum allowed for the CPU.

Remark: The divider values for P and M must be selected so that the PLL output clock

frequency FCLKOUT is lower than 100 MHz.

4.6.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see

Section 4.7.4.1).

4.6.5 System oscillator control register

This register configures the frequency range for the system oscillator. The system

oscillator itself is powered on or off in the PDRUNCFG register. See Table 49.

Table 20. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

value

4:0 MSEL Feedback divider value. The divisio n value M is the

programmed MSEL value + 1.

00000: Division ratio M = 1

11111: Division ratio M = 32

6:5 PSEL Post divider ratio P. The division ratio is 2  P. 0

0x0 P = 1

0x1 P = 2

0x2 P = 4

0x3 P = 8

31:7 - - Reserved. Do not write ones to reserved bits. -

Table 21. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

value

0 LOCK PLL lock status 0

0 PLL not locked

1 PLL locked

31:1 - - Reserved -

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.6 Watchdog oscillator control register

This register configures the watchdog oscillator . The oscillator consists of an analog and a

digital p art. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the

required output clock frequency wdt_osc_clk. The ana log outp ut frequency (Fclkan a) can

be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as

wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the

listed frequency value. The watchdog oscillator is the clock source with the lowest power

consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog

oscillator frequency must be programmed by writing to the WDTOSCCTRL register before

using the watchdog oscillator.

Table 22. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit Symbol Value Description Reset

value

0 BYPASS Bypass system oscillator 0x0

0 Disabled. Oscillator is not bypassed.

1 Enabled. PLL inpu t (sys_osc_clk) is fed directly

from the XTALIN pin bypassing the oscillator. Use

this mode when using an external clock source

instead of the crystal oscillator.

1 FREQRANGE Determines oscillator frequency range. 0x0

0 1 - 20 MHz frequen cy range.

1 15 - 25 MHz freque ncy range

31:2 - - Reserved 0x00

Table 23. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

value

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/ (2  (1 + DIVSEL))

00000: 2  (1 + DIVSEL) = 2

00001: 2  (1 + DIVSEL) = 4

11111: 2  (1 + DIVSEL) = 64

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8:5 FREQSEL Select watchdog oscillator analog output frequency

(Fclkana). 0x00

0x1 0.6 MHz

0x2 1.05 MHz

0x3 1.4 MHz

0x4 1.75 MHz

0x5 2.1 MHz

0x6 2.4 MHz

0x7 2.7 MHz

0x8 3.0 MHz

0x9 3.25 MHz

0xA 3.5 MHz

0xB 3.75 MHz

0xC 4.0 MHz

0xD 4.2 MHz

0xE 4.4 MHz

0xF 4.6 MHz

31:9 - - Reserved 0x00

Table 23. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

value

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.7 System reset status register

If another reset signal - for example the external RESET pi n - remains asserted after the

POR signal is negated, then its bit is set to detected. Write a one to clear the reset.

The reset value given in Table 24 applies to the POR reset.

4.6.8 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register

(see Section 4.6.9) must be toggled from LOW to HIGH for the update to take effect.

Table 24. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description

Bit Symbol Value Description Reset

value

0 POR POR reset status 0

0 No POR detected

1 POR detected. Writing a one clears this reset.

1 EXTRST External reset status. 0

0 No reset event detect ed .

1 Reset detected. Writing a one clears this reset.

2 WDT Status of the Watchdog reset 0

0 No WDT reset detected

1 WDT reset detected. Writing a one clears this reset.

3 BOD Status of the Brown-out detect reset 0

0 No BOD reset detected

1 BOD reset detected. Writing a one clears this reset.

4 SYSRST Status of the software system reset 0

0 No System reset detected

1 System reset detected. Writing a one clears this reset.

31:5 - - Reserved -

Table 25. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

bit description

Bit Symbol Value Description Reset

value

1:0 SEL System PLL clock source 0

0x0 IRC

0x1 Crystal Oscillator (SYSOSC)

0x2 Reserved.

0x3 C LKIN. External clock input.

31:2 - - Reserved -

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.9 System PLL clock source update register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first

write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

4.6.10 Main clock source select register

This register selects the main system clock, which can be the system PLL (sys_pllclkout),

or the watchdog oscillator, or the IRC oscillator. The main system clock clocks the core,

the peripherals, and the memories.

Bit 0 of the MAINCLKUEN reg ister (see Section 4.6.11) must be toggled from 0 to 1 for the

update to take effect.

4.6.11 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write

a zero to bit 0 of this register, then write a one.

Table 26. System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Bit Symbol Value Description Reset value

0 ENA Enable syste m PLL clock source update 0

0 No change

1 Update clock source

31:1 - - Reserved -

Table 27. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0

0x0 IRC Osci llator

0x1 PLL input

0x2 Watchdog oscillator

0x3 PLL output

31:2 - - Reserved -

Table 28. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

bit description

Bit Symbol Value Description Reset value

0 ENA Enable main clock source update 0

0 No change

1 Update clock source

31:1 - - Reserved -

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.12 System clock divider register

This register controls how the main clock is divided to provide the system clock to the

core, memories, and the peripherals. The system clock can be shut down completely by

setting the DIV field to zero.

4.6.13 System clock control register

The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral

blocks. The system clock (b it 0) provide s th e clock for the AHB, the APB bridge , th e ARM

Cortex-M0+, the SYSCON block, and the PMU. This clock cannot be disabled.

Table 29. System clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit

description

Bit Symbol Description Reset

value

7:0 DIV System AHB clock divider values

0: System clock disabled.

1: Divide by 1.

255: Divid e by 25 5.

0x01

31:8 - Reserved -

Table 30. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description

Bit Symbol Value Description Reset

value

0 SYS Enables the clock for the AHB, the APB bridge, the

Cortex-M0+ core clocks, SYSCON, and the PMU.

This bit is read only and always reads as 1.

0 Reserved

1 Enable

1 ROM Enables clock for ROM. 1

0 Disable

1 Enable

2 RAM Enables clock for SRAM. 1

0 Disable

1 Enable

3 FLASHREG Enables clock for flash register interface. 1

0 Disable

1 Enable

4 FLASH Enables clock for flash. 1

0 Disable

1 Enable

5 I2C Enables clock for I2C. 0

0 Disable

1 Enable

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Chapter 4: LPC81x System configuration (SYSCON)

6 GPIO E nables clock for GPIO port registers and GPIO pin

interrupt registers. 1

0 Disable

1 Enable

7 SWM Enables clock for switch matrix. 1

0 Disable

1 Enable

8 SCT Enables clock for state configurable timer. 0

0 Disable

1 Enable

9 WKT Enables clock for self wake-up timer. 0

0 Disable

1 Enable

10 MRT Enables clock for multi-rate timer.

0 Disable

1 Enable

11 SPI0 Enables clock for SPI0. 0

0 Disable

1 Enable

12 SPI1 Enables clock for SPI1.

0 Disable

1 Enable

13 CRC Enables clock for CRC. 0

0 Disable

1 Enable

14 UART0 Enables clock for USART0. 0

0 Disable

1 Enable

15 UART1 Enables clock for USART1. 0

0 Disable

1 Enable

16 UART2 Enables clock for USART2. 0

0 Disable

1 Enable

17 WWDT Enables clock for WWDT. 0

0 Disable

1 Enable

18 IOCON Enables clock for IOCON block. 0

0 Disable

1 Enable

Table 30. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit Symbol Value Description Reset

value

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.14 USART clock divider register

This register configures the clock for the fractional baud rate generator and all USARTs.

The UART clock can be disabled by setting the DIV field to zero (this is the default

setting).

4.6.15 CLKOUT clock source select register

This register select s the signal visible on the CLKOUT pin. Any oscillator or the main clock

can be selected.

Bit 0 of the CLKOUTUEN register (see Section 4.6.16) must be toggled from 0 to 1 for the

update to take effect.

4.6.16 CLKOUT clock source update enable register

This register updates the clock source of the CLKOUT pin with the new clock after the

CLKOUTSEL register has been written to. In order for the update to t ake effect at the input

of the CLKOUT pin, first write a zero to bit 0 of this register, then write a one.

19 ACMP Enables clock to analog comparator. 0

0 Disable

1 Enable

31:20 - - Reserved -

Table 30. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit

description …continued

Bit Symbol Value Description Reset

value

Table 31. USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit description

Bit Symbol Description Reset

value

7:0 DIV USART fractional baud rate generator clock divider values.

0: Clock disabled.

1: Divide by 1.

255: Divid e by 25 5.

31:8 - Reserved -

Table 32. CLKOUT clock sou rce select register (CLKOUTSEL, addr ess 0x4004 80E0) bit

description

Bit Symbol Value Description Reset

value

1:0 SEL CLKOUT clock source 0

0x0 IRC oscil lator

0x1 Crystal oscillator (SYSOSC)

0x2 Watchdog oscillator

0x3 Mai n clock

31:2 - - Reserved 0

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Chapter 4: LPC81x System configuration (SYSCON)

4.6.17 CLKOUT clock divider register

This register determines the divider value for the signal on the CLKOUT pin.

4.6.18 USART fractional generator divider value register

All USART peripherals share a common clock U_PCLK, which can be adjusted by a

fractional divider:

U_PCLK = UARTCLKDIV/(1 + MULT/DIV).

UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.

The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider

registers in the SYSCON block:

1. The DIV value programmed in this register is the denominator of the divider used by

the fractional rate generator to create the fractional component of U_PCLK.

2. The MULT value of the fractional divider is programmed in the UARTFRGMULT

Remark: To use of the fractional bau d rate g enerato r, you must write 0xFF to this register

to yield a denominator value of 256. All other values are not supported.

Related links:

Section 8.7.2

8.6 Register description

8.6.1 Pin interrupt mode register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the ISEL register determines whether the interrupt is edge or level sensitive.

Table 92. Register ov erview: Pin interrupts and pattern match engine (base address:

0xA000 4000)

Name Access Address

offset Description Reset

value Reference

ISEL R/W 0x000 Pin Interrupt Mode register 0 Table 93

IENR R/W 0x004 Pin interrupt level or rising edge interrupt

enable register 0Table 94

SIENR WO 0x008 Pin interrupt level or rising edge interru pt

set register NA Table 95

CIENR WO 0x00C Pin interrupt level (rising edge interrupt)

clear register NA Table 96

IENF R/W 0x010 Pin interrupt active level or falling edge

interrupt enable register 0Table 97

SIENF WO 0x014 Pin interrupt active level or falling edge

interrupt set register NA Table 98

CIENF WO 0x018 Pin interrupt active level or falling edge

interrupt clear register NA Table 99

RISE R/W 0x01C Pin interrupt rising edge register 0 Table 100

FALL R/W 0x020 Pin interrupt falling edge register 0 Table 101

IST R/W 0x024 Pin interrupt status register 0 Table 102

PMCTRL R/W 0x028 Pattern match interrupt control register 0 Table 103

PMSRC R/W 0x02C Pattern match interrupt bit-slice source

PMCFG R/W 0x030 Pattern match interrupt bit slice

configuration register 0Table 105

Table 93. Pin interrupt mode register (ISEL, address 0xA000 4000) bit description

Bit Symbol Description Reset

value Access

7:0 PMODE Selects the interrupt mode for each pin interrupt. Bit n

configures the pin interrupt selected in PINTSELn.

0 = Edge sensitive

1 = Level sensitive

0R/W

31:8 - Reserved. - -

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Chapter 8: LPC81x Pin interrupts/pattern match engine

8.6.2 Pin interrupt level or rising edge interrupt enable register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the IENR register enables the interrupt depending on the pin interrupt mode

configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

enabled.

•If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.

The IENF register configures the active level (HIGH or LOW) for this interrupt.

8.6.3 Pin interrupt level or rising edge interrupt set register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the SIENR register set s the corresponding bit in the IENR re gister depending on

the pin interrupt mode configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

set.

•If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.

8.6.4 Pin interrupt level or rising edge interrupt clear register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the CIENR register clears the corresponding bit in the IENR register depending

on the pin interrupt mode configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is

cleared.

•If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.

Table 94. Pin interrupt leve l or rising edge interrupt enable register (IENR, address 0xA000

4004) bit description

Bit Symbol Description Reset

value Access

7:0 ENRL Enables the rising edge or level interrupt for each pin

interrupt. Bit n configures the pin interrupt selected in

PINTSELn.

0 = Disable rising edge or level interrupt.

1 = Enable rising edge or level interrupt.

0R/W

31:8 - Reserved. - -

Table 95. Pin interrupt leve l or rising edge interrupt set register (SIENR, address 0xA000

4008) bit description

Bit Symbol Description Reset

value Access

7:0 SETENRL Ones written to this address set bits in the IENR, thus

enabling interrupts. Bit n sets bit n in the IENR register.

0 = No operation.

1 = Enable rising edge or level interrupt.

NA WO

31:8 - Reserved. - -

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8.6.5 Pin interrupt active level or falling edge interrupt enable register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the IENF register enables the falling edge interrupt or the configures the level

sensitivity depending on the pin interrupt mode configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

enabled.

•If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level

interrupt (HIGH or LOW) is configured.

8.6.6 Pin interrupt active level or falling edge interrupt set register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the SIENF register set s the corresponding bit in the IENF re gister depen ding on

the pin interrupt mode configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

set.

•If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is

selected.

Table 96. Pin interrupt leve l or rising edge interrupt clear register (CIENR, address 0xA000

400C) bit description

Bit Symbol Description Reset

value Access

7:0 CENRL Ones written to this address clear bits in the IENR, thus

disabling the interrupts. Bit n clears bit n in the IENR

0 = No operation.

1 = Disable rising edge or level interrupt.

NA WO

31:8 - Reserved. - -

Table 97. Pin interrupt active level or falling edge interrupt enable register (IENF, address

0xA000 4010) bit description

Bit Symbol Description Reset

value Access

7:0 ENAF Ena bles the falling edge or configures the active level interrupt

for each pin interrupt. Bit n configures the pin interrupt selected

in PINTSELn.

0 = Disable falling edge interrup t or set active inte rrupt level

LOW.

1 = Enable falling edge interrupt enabled or set active interrup t

level HIGH.

0R/W

31:8 - Reserved. - -

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8.6.7 Pin interrupt active level or falling edge interrupt clear register

For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27),

one bit in the CIENF r egister set s th e correspo nding bit in the IENF register depending on

the pin interrupt mode configured in the ISEL register:

•If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is

cleared.

•If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is

selected.

8.6.8 Pin interrupt rising edge register

This register contains ones for pin interrupts selected in the PINTSELn registers (see

Section 4.6.27) on which a rising edge has been detected. Writing ones to this register

clears rising edge detection. Ones in this register assert an interrupt request for pins that

are enabled for rising-edge interrupts. All edges are detected for all pins selected by the

PINTSELn registers, regardless of whether they are interrupt-enabled.

Table 98. Pin interrupt active level or falling edge interrupt set register (SIENF, addr ess

0xA000 4014) bit description

Bit Symbol Description Reset

value Access

7:0 SETENAF Ones written to this address set bits in the IENF, thus

enabling interrupts. Bit n sets bit n in the IENF register.

0 = No operation.

1 = Select HIGH-active interrupt or enable falling edge

interrupt.

NA WO

31:8 - Reserved. - -

Table 99. Pin interrupt active level or falling edge interrupt clear register (CIENF, address

0xA000 4018) bit description

Bit Symbol Description Reset

value Access

7:0 CENAF Ones written to this address clears bits in the IENF, thus

disabling interrupts. Bit n clears bit n in the IENF register.

0 = No operation.

1 = LOW-active interrupt selected or falling edge interrupt

disabled.

NA WO

31:8 - Reserved. - -

Table 100 . Pin interrupt rising edge regi ster (RISE, addre ss 0xA000 401C) bit description

Bit Symbol Description Reset

value Access

7:0 RDET Rising edge detect. Bit n detects the rising edge of the pin

selected in PINTSELn.

Read 0: No rising edge has been detected on this pin since

Reset or the last time a one was written to this bit.

Write 0: no operation.

Read 1: a rising edge has been detected since Reset or the

last time a one was written to this bit.

Write 1: clear rising edge detection for this pin.

0R/W

31:8 - Reserved. - -

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8.6.9 Pin interrupt falling edge register

This register contains ones for pin interrupts selected in the PINTSELn registers (see

Section 4.6.27) on which a falling edge has been detected. Writing ones to this register

clears falling edge detection. Ones in this register assert an interrupt request for pins that

are enabled for falling-edge interrupts. All edges are detecte d for all pins selected by the

PINTSELn registers, regardless of whether they are interrupt-enabled.

8.6.10 Pin interrupt status register

Reading this register returns ones for pin interrupts that are currently requesting an

interrupt. For pins identifie d as edge-se nsitive in the Inter rupt Select register, writing ones

to this register clears both rising- and fall ing-ed ge detection for the p in. For level-sensitive

pins, writing ones inverts the corresponding bit in the Active level register, thus switching

the active level on the pin.

8.6.11 Patter n Match Interrupt Control Register

The pattern match control register contains one bit to select pattern-match interrupt

generation (as opposed to pin interrupts which share the same interrupt request lines),

and another to enable the RXEV output to the cpu. This register also allows the current

state of any pattern matches to be read.

If the pattern match feature is not used (either for interrupt generation or for RXEV

assertion) bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to

conserve power.

Table 101 . Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description

Bit Symbol Description Reset

value Access

7:0 FDET Falling edge detect. Bit n detects the falling edge of the pin

selected in PINTSELn.

Read 0: No falling edge has been detected on this pi n since

Reset or the last time a one was written to this bit.

Write 0: no operation.

Read 1: a falling edge has been detected since Reset or the

last time a one was written to this bit.

Write 1: clear falling edge detection for this pin.

0R/W

31:8 - Reserved. - -

Table 102. Pin interru pt status register (IST, address 0xA000 4024) bit d escription

Bit Symbol Description Reset

value Access

7:0 PSTAT Pin interrupt status. Bit n returns the sta tu s , clears the edge

interrupt, or inverts the active level of the pin selected in

PINTSELn.

Read 0: interrupt is not being requested for this interrupt pin.

Write 0: no operation.

Read 1: interrupt is being requested for this interru pt pin.

Write 1 (edge-sensitive): clear rising- and falling-edge

detection for this pin.

Write 1 (level-sensitive): switch the active level for this pin (in

the IENF register).

0R/W

31:8 - Reserved. - -

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Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers

before writing to th is register to enabl e (or re- enab le) the pattern-match functionality. This

eliminates the possibility of spurious interrupts as the feature is being enabled.

8.6.12 Pattern Match Interrupt Bit-Slice Source register

The bit-slice source register specifies the input sour ce for each of the eigh t pattern match

bit slices.

Each of the possible eight inputs is selected in the pin interrupt select registers in the

SYSCON block. See Section 4.6.27. Input 0 corresponds to the pin selected in the

PINTSEL0 register, input 1 corresponds to th e pin selecte d in the PINTSEL1 r egister, and

so forth.

Remark: Writing any value to either the PMCFG register or the PMSRC register, or

disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV

bits in the PMCTRL register to zeros) will erase all edge-detect history.

Table 103 . Pattern match interrupt control register (PMCTRL, address 0xA000 4028)

bit description

Bit Symbol Value Description Reset

value

0 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by

the pin interrupt function or by the pattern match

function.

0 Pin interrupt. Interrupts are driven in response to the

standard pin interrupt function

1 Pattern match . Inte rrupts are driven in response to

pattern matches.

1 ENA_RXEV Enables the RXEV output to the ARM cpu and/or to a

GPIO output when the specified boolean ex pression

evaluates to true.

0 Disabled. RXEV output to the cpu is disabled.

1 Enabled. RXEV output to the cpu is enabled.

23:2 - Reserved. Do not write 1s to unused bits. 0

31:24 PMAT - This field displays the current state of pattern matches.

A 1 in any bit of this field indicates that the

corresponding product term is matched by the current

state of the appropriate inputs.

0x0

Table 10 4. Pattern match bit-slice source regist er (PMSRC, address 0xA000 402C) bit description

Bit Symbol Value Description Reset value

7:0 Reserved Software should not write 1s to unused bits. 0

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10:8 SRC0 Se lects the input source for bit slice 0 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 0.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 0.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 0.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 0.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 0.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 0.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 0.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 0.

13:11 SRC1 Selects the input source for bit slice 1 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 1.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 1.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 1.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 1.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 1.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 1.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 1.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 1.

Table 10 4. Pattern match bit-slice source regist er (PMSRC, address 0xA000 402C) bit description

Bit Symbol Value Description Reset value

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16:14 SRC2 Selects the input source for bit slice 2 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 2.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 2.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 2.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 2.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 2.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 2.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 2.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 2.

19:17 SRC3 Selects the input source for bit slice 3 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 3.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 3.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 3.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 3.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 3.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 3.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 3.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 3.

Table 10 4. Pattern match bit-slice source regist er (PMSRC, address 0xA000 402C) bit description

Bit Symbol Value Description Reset value

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22:20 SRC4 Selects the input source for bit slice 4 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 4.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 4.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 4.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 4.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 4.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 4.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 4.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 4.

25:23 SRC5 Selects the input source for bit slice 5 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 5.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 5.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 5.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 5.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 5.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 5.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 5.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 5.

Table 10 4. Pattern match bit-slice source regist er (PMSRC, address 0xA000 402C) bit description

Bit Symbol Value Description Reset value

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8.6.13 Pattern Match Interrupt Bit Slice Configuration register

The bit-slice configuration regist er configures the detect logic and contains bits to select

from among eight alternative conditions for each bit slice that cause that bit slice to

contribute to a pattern match. The seven LSBs of this register specify which bit-slices are

the end-points of product terms in the boolean expression (i.e. where OR terms are to be

inserted in the expression).

Two types of edge detection on each input are possible:

28:26 SRC6 Selects the input source for bit slice 6 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 6.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 6.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 6.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 6.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 6.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 6.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 6.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 6.

31:29 SRC7 Selects the input source for bit slice 7 0

0x0 Input 0. Selects the pin selected in the PINTSEL0 register as the source

to bit slice 7.

0x1 Input 1. Selects the pin selected in the PINTSEL1 register as the source

to bit slice 7.

0x2 Input 2. Selects the pin selected in the PINTSEL2 register as the source

to bit slice 7.

0x3 Input 3. Selects the pin selected in the PINTSEL3 register as the source

to bit slice 7.

0x4 Input 4. Selects the pin selected in the PINTSEL4 register as the source

to bit slice 7.

0x5 Input 5. Selects the pin selected in the PINTSEL5 register as the source

to bit slice 7.

0x6 Input 6. Selects the pin selected in the PINTSEL6 register as the source

to bit slice 7.

0x7 Input 7. Selects the pin selected in the PINTSEL7 register as the source

to bit slice 7.

Table 10 4. Pattern match bit-slice source regist er (PMSRC, address 0xA000 402C) bit description

Bit Symbol Value Description Reset value

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•Sticky: A rising edge, a falling edge, or a rising or falling edge that is detected at any

time after the edge-detection mechanism has been cleared. The input qualifies as

detected (the detect logic output remains HIGH) until the pattern match engine detect

logic is cleared aga i n.

•Non-sticky: Every time an edge (rising or falling) is detected, the detect logic output

for this pin goes HIGH. This bit is cleared after one clock cycle, and the edge detect

logic can detect an ot he r ed g e,

Remark: To clear the pattern match engine detect logic, write any value to either the

PMCFG register or the PMSRC register, or disable the pattern-match feature (by clearing

both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros). This will

erase all edge-detect history.

To select whether a slice marks the final component in a minterm of the boolean

expression, write a 1 in the co rrespo ndin g PR OD_ENPTSn bit. Setting a ter m as the final

component has two effects:

1. The interrupt request associated with this bit slice will be asserted whenever a match to that

product term is detected.

2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an

OR will be inserted in th e boolean expression following the element controlled by this bit slice).

Table 10 5. Pattern match bit slice configuration register (PMCFG, address 0xA000 403 0) bit desc ription

Bit Symbol Value Description Reset

value

0 PROD_EN

DPTS0 Determines whether slice 0 is an endpoint. 0

0 No effect. Slice 0 is not an endpoint.

1 endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the

NVIC is raised if the minterm evaluates as true.

1 PROD_EN

DPTS1 Determines whether slice 1 is an endpoint. 0

0 No effect. Slice 1 is not an endpoint.

1 endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the

NVIC is raised if the minterm evaluates as true.

2 PROD_EN

DPTS2 Determines whether slice 2 is an endpoint. 0

0 No effect. Slice 2 is not an endpoint.

1 endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the

NVIC is raised if the minterm evaluates as true.

3 PROD_EN

DPTS3 Determines whether slice 3 is an endpoint. 0

0 No effect. Slice 3 is not an endpoint.

1 endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the

NVIC is raised if the minterm evaluates as true.

4 PROD_EN

DPTS4 Determines whether slice 4 is an endpoint. 0

0 No effect. Slice 4 is not an endpoint.

1 endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the

NVIC is raised if the minterm evaluates as true.

5 PROD_EN

DPTS5 Determines whether slice 5 is an endpoint. 0

0 No effect. Slice 5 is not an endpoint.

1 endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the

NVIC is raised if the minterm evaluates as true.

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6 PROD_EN

DPTS6 Determines whether slice 6 is an endpoint. 0

0 No effect. Slice 6 is not an endpoint.

1 endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the

NVIC is raised if the minterm evaluates as true.

7 - R eserved. Bit slice 7 is automatically considered a product end point. 0

10:8 CFG0 Specifies the match contribution condition for bit slice 0. 0b000

0x0 Constant HIGH. This bit slice always contributes to a product term match.

0x1 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred

since the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2 S ticky falling edge. Match occurs if a falling edge on the specified input has occurred

since the last time the edge detection for this bit slice was cleared. This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x3 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the

specified input has occurred since the last time the edge detection for this bit slice

was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are

written to.

0x4 High le vel. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5 Low level . Match occurs when there is a low level on the specified input.

0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any

unused bit slices).

0x7 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a

rising or falling edge is first detected on the specified input (this is a non-sti cky

version of value 0x3). This bit is cleared after one clock cycle.

13:11 CFG1 Specifies the match contribution condition for bit slice 1. 0b000