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Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
Rev. D Document Feedback
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FEATURES
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C T
JUNCTION
AEC-Q100 qualified for automotive applications
PERIPHERALS FEATURES
See Figure 1, Processor Block Diagram and Table 1, Processor
Comparison
MEMORY
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
Figure 1. Processor Block Diagram
PERIPHERALS
1× RTC
3× MDMA
STREAMS
1× MSI
(SD/SDIO)
2× UART
STATIC MEMORY
CONTROLLER
2× SPORT
1× PPI
8× TIMER
2× CAN
1× COUNTER
1× TWI
1× USB 2.0 HS OTG
GPIO
SYSTEM CONTROL BLOCKS
HARDWARE
FUNCTIONS
EXTERNAL
BUS
INTERFACES
LPDDR
DDR2
SYSTEM FABRIC
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
CONTROL WATCHDOG
16
MEMORY
PROTECTION
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
B
ANALOG
SUB
SYSTEM
CRYPTO ENGINE (SECURITY)
SYSTEM PROTECTION
512K BYTE
ROM
UP TO
1M BYTE SRAM
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
L2 MEMORY
HADC
OTP
MEMORY
DYNAMIC MEMORY
CONTROLLER
SPI HOST PORT
2× CRC
2x QUAD SPI
1x DUAL SPI
Rev. D | Page 2 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Peripherals Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Blackfin+ Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Processor Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Security Features Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Processor Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Processor Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power and Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ADSP-BF70x Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . 17
184-Ball CSP_BGA Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . 21
GPIO Multiplexing for 184-Ball CSP_BGA . . . . . . . . . . . . . . . . . . 28
12 mm × 12 mm 88-Lead LFCSP (QFN) Signal
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPIO Multiplexing for 12 mm × 12 mm 88-Lead
LFCSP (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADSP-BF70x Designer Quick Reference . . . . . . . . . . . . . . . . . . . . . . 37
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
HADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADSP-BF70x 184-Ball CSP_BGA Ball Assignments
(Numerical by Ball Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN)
Lead Assignments (Numerical by Lead Number) . . . . . . 108
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
REVISION HISTORY
2/2019—Rev. C to Rev. D
Deleted Package Information (Figure 7 and Table 27) in
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Changes to
TWI0VSEL Settings and VDD_EXT/VBUSTWI . . . . . . . . . . . 50
Changes to Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Changes to Output Enable Time Measurement . . . . . . . . . . . . 102
Changes to Output Disable Time Measurement . . . . . . . . . . . 102
Changes to Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Changes to Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Rev. D | Page 3 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
GENERAL DESCRIPTION
The ADSP-BF70x processor is a member of the Blackfin
®
family of products. The Blackfin processor combines a dual-
MAC 16-bit state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set architec-
ture. New enhancements to the Blackfin+ core add 32-bit MAC
and 16-bit complex MAC support, cache enhancements, branch
prediction and other instruction set improvements—all while
maintaining instruction set compatibility to previous Blackfin
products.
The processor offers performance up to 400 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), the Blackfin processor is the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation, video/image analysis,
biometric and power/motor control applications.
Table 1. Processor Comparison
Processor Feature
ADSP-
BF700
ADSP-
BF701
ADSP-
BF702
ADSP-
BF703
ADSP-
BF704
ADSP-
BF705
ADSP-
BF706
ADSP-
BF707
Maximum Speed Grade (MHz)
1
200 400
Maximum SYSCLK (MHz) 100 200
Package Options 88-Lead
LFCSP
184-Ball
CSP_BGA
88-Lead
LFCSP
184-Ball
CSP_BGA
88-Lead
LFCSP
184-Ball
CSP_BGA
88-Lead
LFCSP
184-Ball
CSP_BGA
GPIOs 43 47 43 47 43 47 43 47
Memory (bytes)
L1 Instruction SRAM 48K
L1 Instruction SRAM/Cache 16K
L1 Data SRAM 32K
L1 Data SRAM/Cache 32K
L1 Scratchpad (L1 Data C) 8K
L2 SRAM 128K 256K 512K 1024K
L2 ROM 512K
DDR2/LPDDR (16-bit) No Yes No Yes No Yes No Yes
I
2
C 1
Up/Down/Rotary Counter 1
GP Timer 8
Watchdog Timer 1
GP Counter 1
SPORTs 2
Quad SPI 2
Dual SPI 1
SPI Host Port 1
USB 2.0 HS OTG 1
Parallel Peripheral Interface 1
CAN 2
UART 2
Real-Time Clock 1
Static Memory Controller (SMC) Yes
Security Crypto Engine Yes
SD/SDIO (MSI) 4-bit 8-bit 4-bit8-bit4-bit8-bit4-bit8-bit
4-Channel 12-Bit ADC NoYesNoYesNoYesNoYes
1
Other speed grades available.
Rev. D | Page 4 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
BLACKFIN+ PROCESSOR CORE
As shown in Figure 1, the processor integrates a Blackfin+
processor core. The core, shown in Figure 2, contains two 16-bit
multipliers, one 32-bit multiplier, two 40-bit accumulators
(which may be used together as a 72-bit accumulator), two
40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit
shifter. The computation units process 8-, 16-, or 32-bit data
from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The core can perform two 16-bit by 16-bit multiply-accumu-
lates or one 32-bit multiply-accumulate in each cycle. Signed
and unsigned formats, rounding, saturation, and complex mul-
tiplies are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, divide primitives, saturation and rounding, and
sign/exponent detection. The set of video instructions include
byte alignment and packing operations, 16-bit and 8-bit adds
with clipping, 8-bit average operations, and 8-bit subtract/abso-
lute value/accumulate (SAA) operations. Also provided are the
compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If a second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
Figure 2. Blackfin+ Processor Core
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
A0 A1
8 8 8 8
40 40
DATA ARITHMETIC UNIT
CONTROL
UNIT
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
ASTAT
40 40
32 32
32
32
32
32
32
LD0
LD1
SD
DAG0
DAG1
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
SP
FP
P5
P4
P3
P2
P1
P0
DA1
DA0
32
32
32
PREG
RAB
32
TO MEMORY
BARREL
SHIFTER
16
3216
72
Rev. D | Page 5 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with dynamic branch prediction),
and subroutine calls. Hardware supports zero-overhead loop-
ing. The architecture is fully interlocked, meaning that the
programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor supports a modified Harvard architec-
ture in combination with a hierarchical memory structure. Level
1 (L1) memories are those that typically operate at the full pro-
cessor speed with little or no latency. At the L1 level, the
instruction memory holds instructions only. The data memory
holds data, and a dedicated scratchpad data memory stores
stack and local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
INSTRUCTION SET DESCRIPTION
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. The Blackfin proces-
sor supports a limited multi-issue capability, where a 32-bit
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Control of all asynchronous and synchronous events to the
processor is handled by two subsystems: the core event
controller (CEC) and the system event controller (SEC).
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
PROCESSOR INFRASTRUCTURE
The following sections provide information on the primary
infrastructure components of the ADSP-BF70x processor.
DMA Controllers
The processor uses direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processor can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory-to-
memory DMA stream uses two channels, where one channel is
the source channel, and the second is the destination channel.
All DMAs can transport data to and from all on-chip and off-
chip memories. Programs can use two types of DMA transfers,
descriptor-based or register-based. Register-based DMA allows
the processor to directly program DMA control registers to ini-
tiate a DMA transfer. On completion, the control registers may
be automatically updated with their original setup values for
continuous transfer. Descriptor-based DMA transfers require a
set of parameters stored within memory to initiate a DMA
sequence. Descriptor-based DMA transfers allow multiple
DMA sequences to be chained together and a DMA channel can
be programmed to automatically set up and start another DMA
transfer after the current sequence completes.
The DMA controller supports the following DMA operations.
• A single linear buffer that stops on completion.
• A linear buffer with negative, positive, or zero stride length.
• A circular, auto-refreshing buffer that interrupts when each
buffer becomes full.
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ADSP-BF700/701/702/703/704/705/706/707
• A similar buffer that interrupts on fractional buffers (for
example, 1/2, 1/4).
• 1D DMA—uses a set of identical ping-pong buffers defined
by a linked ring of two-word descriptor sets, each contain-
ing a link pointer and an address.
• 1D DMA—uses a linked list of 4 word descriptor sets con-
taining a link pointer, an address, a length, and a
configuration.
• 2D DMA—uses an array of one-word descriptor sets, spec-
ifying only the base DMA address.
• 2D DMA—uses a linked list of multi-word descriptor sets,
specifying everything.
Event Handling
The processor provides event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher-priority event takes precedence over ser-
vicing of a lower-priority event. The processor provides support
for five different types of events:
• Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor through the JTAG interface.
• Reset—This event resets the processor.
• Nonmaskable interrupt (NMI)—The NMI event can be
generated either by the software watchdog timer, by the
NMI input signal to the processor, or by software. The
NMI event is frequently used as a power-down indicator to
initiate an orderly shutdown of the system.
• Exceptions—Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts —Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
System Event Controller (SEC)
The SEC manages the enabling, prioritization, and routing of
events from each system interrupt or fault source. Additionally,
it provides notification and identification of the highest priority
active system interrupt request to the core and routes system
fault sources to its integrated fault management unit. The SEC
triggers core general-purpose interrupt IVG11. It is recom-
mended that IVG11 be set to allow self-nesting. The four lower
priority interrupts (IVG15-12) may be used for software
interrupts.
Trigger Routing Unit (TRU)
The TRU provides system-level sequence control without core
intervention. The TRU maps trigger masters (generators of trig-
gers) to trigger slaves (receivers of triggers). Slave endpoints can
be configured to respond to triggers in various ways. Common
applications enabled by the TRU include:
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers:
• GPIO direction control register—Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers—A write one to modify
mechanism allows any combination of individual GPIO
pins to be modified in a single instruction, without affect-
ing the level of any other GPIO pins.
• GPIO interrupt mask registers—Allow each individual
GPIO pin to function as an interrupt to the processor.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers—Specify whether indi-
vidual pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the ris-
ing and falling edges of the signal are significant.
Pin Interrupts
Every port pin on the processor can request interrupts in either
an edge-sensitive or a level-sensitive manner with programma-
ble polarity. Interrupt functionality is decoupled from GPIO
operation. Three system-level interrupt channels (PINT0–3) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin-by-pin basis. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half-port assignment and
interrupt management. This includes masking, identification,
and clearing of requests. These registers also enable access to the
respective pin states and use of the interrupt latches, regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
Pin Multiplexing
The processor supports a flexible multiplexing scheme that mul-
tiplexes the GPIO pins with various peripherals. A maximum of
4 peripherals plus GPIO functionality is shared by each GPIO
pin. All GPIO pins have a bypass path feature—that is, when the
Rev. D | Page 7 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
output enable and the input enable of a GPIO pin are both
active, the data signal before the pad driver is looped back to the
receive path for the same GPIO pin.
MEMORY ARCHITECTURE
The processor views memory as a single unified 4G byte address
space, using 32-bit addresses. All resources, including internal
memory, external memory, and I/O control registers, occupy
separate sections of this common address space. The memory
portions of this address space are arranged in a hierarchical
structure to provide a good cost/performance balance of some
very fast, low-latency core-accessible memory as cache or
SRAM, and larger, lower-cost and performance interface-acces-
sible memory systems. See Figure 3.
Internal (Core-Accessible) Memory
The L1 memory system is the highest-performance memory
available to the Blackfin+ processor core.
The core has its own private L1 memory. The modified Harvard
architecture supports two concurrent 32-bit data accesses along
with an instruction fetch at full processor speed which provides
high-bandwidth processor performance. In the core, a 64K byte
block of data memory partners with an 64K byte memory block
for instruction storage. Each data block is multibanked for effi-
cient data exchange through DMA and can be configured as
SRAM. Alternatively, 16K bytes of each block can be configured
in L1 cache mode. The four-way set-associative instruction
cache and the 2 two-way set-associative data caches greatly
accelerate memory access performance, especially when access-
ing external memories.
The L1 memory domain also features a 8K byte data SRAM
block which is ideal for storing local variables and the software
stack. All L1 memory is protected by a multi-parity-bit concept,
regardless of whether the memory is operating in SRAM or
cache mode.
Outside of the L1 domain, L2 and L3 memories are arranged
using a Von Neumann topology. The L2 memory domain is a
unified instruction and data memory and can hold any mixture
of code and data required by the system design. The L2 memory
domain is accessible by the Blackfin+ core through a dedicated
64-bit interface. It operates at SYSCLK frequency.
The processor features up to 1M byte of L2 SRAM, which is
ECC-protected and organized in eight banks. Individual banks
can be made private to any system master. There is also a
512K byte single-bank ROM in the L2 domain. It contains boot
code, security code, and general-purpose ROM space.
OTP Memory
The processor features 1 kB of one-time-programmable (OTP)
memory, which is memory-map accessible. This memory stores
a unique chip identification and is used to support secure-boot
and secure operation.
Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map
PROCESSOR MEMORY MAP
0x 0810 0000 -
EXTERNAL
MEMORY
INTERNAL
MEMORY
Reserved
DDR2 or LPDDR Memory (256 MB)
Reserved
Static Memory Block 1 (8 KB)
Reserved
Static Memory Block 0 (8 KB)
Reserved
Static
Memory
SPI2 Memory (128 MB)
Reserved
OTP Memory (1 KB)
Reserved
STM Memory (4 KB)
System MMR Registers (3 MB)
Core MMR Registers (4 MB)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
L1 Data Block C (8 KB)
L1 Instruction SRAM/Cache (16 KB)
L1 Instruction SRAM (48 KB)
L1 Data Block B SRAM/Cache (16 KB)
L1 Data Block B SRAM (16 KB)
L1 Data Block A SRAM/Cache (16 KB)
L1 Data Block A SRAM (16 KB)
L2 SRAM (1024 KB)
L2 ROM (448 KB)
Boot ROM (64 KB)
L1
Instruction
L1 Data
Block B
L1 Data
Block A
0x FFFF FFFF -
0x 9000 0000 -
0x 8000 0000 -
0x 7400 2000 -
0x 7400 0000 -
0x 7000 2000 -
0x 7000 0000 -
0x 4800 0000 -
0x 4000 0000 -
0x 3800 0500 -
0x 3800 0000 -
0x 2030 1000 -
0x 2030 0000 -
0x 2000 0000 -
0x 1FC0 0000 -
0x 11B0 2000 -
0x 11B0 0000 -
0x 11A1 0000 -
0x 11A0 C000 -
0x 11A0 0000 -
0x 1190 8000 -
0x 1190 4000 -
0x 1190 0000 -
0x 1180 8000 -
0x 1180 4000 -
0x 1180 0000 -
0x 0800 0000 -
0x 0408 0000 -
0x 0401 0000 -
0x 0400 0000 -
0x 0000 0000 -
Rev. D | Page 8 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Static Memory Controller (SMC)
The SMC can be programmed to control up to two blocks of
external memories or memory-mapped devices, with very flexi-
ble timing parameters. Each block occupies a 8K byte segment
regardless of the size of the device used.
Dynamic Memory Controller (DMC)
The DMC includes a controller that supports JESD79-2E com-
patible double-data-rate (DDR2) SDRAM and JESD209A low-
power DDR (LPDDR) SDRAM devices. The DMC PHY fea-
tures on-die termination on all data and data strobe pins that
can be used during reads.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses in a region of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting
The processor has several mechanisms for automatically loading
internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE input pins dedicated for this pur-
pose. There are two categories of boot modes. In master boot
mode, the processor actively loads data from serial memories. In
slave boot modes, the processor receives data from external host
devices.
The boot modes are shown in Table 2. These modes are imple-
mented by the SYS_BMODE bits of the reset configuration
register and are sampled during power-on resets and software-
initiated resets.
SECURITY FEATURES
The ADSP-BF70x processor supports standards-based hard-
ware-accelerated encryption, decryption, authentication, and
true random number generation.
The following hardware-accelerated cryptographic ciphers are
supported:
• AES in ECB, CBC, ICM, and CTR modes with 128-, 192-,
and 256-bit keys
• DES in ECB and CBC mode with 56-bit key
• 3DES in ECB and CBC mode with 3x 56-bit key
The following hardware-accelerated hash functions are
supported:
•SHA-1
• SHA-2 with 224-bit and 256-bit digest
• HMAC transforms for SHA-1 and SHA-2
Public key accelerator is available to offload computation-inten-
sive public key cryptography operations.
Both a hardware-based nondeterministic random number gen-
erator and pseudo-random number generator are available. The
TRNG also provides HW post-processing to meet NIST
requirements of FIPS 140-2, while the PRNG is ANSI X9.31
compliant.
Secure boot is also available with 224-bit elliptic curve digital
signatures ensuring integrity and authenticity of the boot
stream. Optionally, confidentiality is also ensured through AES-
128 encryption.
Secure debug is also employed to allow only trusted users to
access the system with debug tools.
SECURITY FEATURES DISCLAIMER
To our knowledge, the Security Features, when used in accor-
dance with the data sheet and hardware reference manual
specifications, provide a secure method of implementing code
and data safeguards. However, Analog Devices does not guaran-
tee that this technology provides absolute security.
ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS
ANY AND ALL EXPRESS AND IMPLIED WARRANTIES
THAT THE SECURITY FEATURES CANNOT BE
BREACHED, COMPROMISED, OR OTHERWISE CIRCUM-
VENTED AND IN NO EVENT SHALL ANALOG DEVICES
BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR
RELEASE OF DATA, INFORMATION, PHYSICAL PROP-
ERTY, OR INTELLECTUAL PROPERTY.
Table 2. Boot Modes
SYS_BMODE Setting Boot Mode
00 No Boot/Idle
01 SPI2 Master
10 SPI2 Slave
11 UART0 Slave
CAUTION
This product includes security features that can be
used to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device
(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices is
limited. Contact Analog Devices for details on the
failure analysis limitations for this device.
Rev. D | Page 9 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PROCESSOR SAFETY FEATURES
The ADSP-BF70x processor has been designed for functional
safety applications. While the level of safety is mainly domi-
nated by the system concept, the following primitives are
provided by the devices to build a robust safety concept.
Multi-Parity-Bit-Protected L1 Memories
In the processor’s L1 memory space, whether SRAM or cache,
each word is protected by multiple parity bits to detect the single
event upsets that occur in all RAMs. This applies both to L1
instruction and data memory spaces.
ECC-Protected L2 Memories
Error correcting codes (ECC) are used to correct single event
upsets. The L2 memory is protected with a single error correct-
double error detect (SEC-DED) code. By default ECC is
enabled, but it can be disabled on a per-bank basis. Single-bit
errors are transparently corrected.
Dual-bit errors can issue a system event or fault if enabled. ECC
protection is fully transparent to the user, even if L2 memory is
read or written by 8-bit or 16-bit entities.
CRC-Protected Memories
While parity bit and ECC protection mainly protect against ran-
dom soft errors in L1 and L2 memory cells, the CRC engines can
be used to protect against systematic errors (pointer errors) and
static content (instruction code) of L1, L2, and even L3 memo-
ries (DDR2, LPDDR). The processor features two CRC engines
which are embedded in the memory-to-memory DMA
controllers. CRC checksums can be calculated or compared on
the fly during memory transfers, or one or multiple memory
regions can be continuously scrubbed by a single DMA work
unit as per DMA descriptor chain instructions. The CRC engine
also protects data loaded during the boot process.
Memory Protection
The Blackfin+ core features a memory protection concept,
which grants data and/or instruction accesses to enabled mem-
ory regions only. A supervisor mode vs. user mode
programming model supports dynamically varying access
rights. Increased flexibility in memory page size options sup-
ports a simple method of static memory partitioning.
System Protection
The system protection unit (SPU) guards against accidental or
unwanted access to the MMR space of a peripheral by providing
a write-protection mechanism. The user is able to choose and
configure the peripherals that are protected as well as configure
which ones of the four system MMR masters (core, memory
DMA, the SPI host port, and Coresight debug) the peripherals
are guarded against.
The SPU is also part of the security infrastructure. Along with
providing write-protection functionality, the SPU is employed
to define which resources in the system are secure or non-secure
and to block access to secure resources from non-secure
masters.
Synonymously, the system memory protection unit (SMPU)
provides memory protection against read and/or write transac-
tions to defined regions of memory. There are two SMPU units
in the ADSP-BF70x processors. One is for the L2 memory and
the other is for the external DDR memory.
The SMPU is also part of the security infrastructure. It allows
the user to not only protect against arbitrary read and/or write
transactions, but it also allows regions of memory to be defined
as secure and prevent non-secure masters from accessing those
memory regions.
Watchpoint Protection
The primary purpose of watchpoints and hardware breakpoints
is to serve emulator needs. When enabled, they signal an emula-
tor event whenever user-defined system resources are accessed
or the core executes from user-defined addresses. Watchpoint
events can be configured such that they signal the events to the
fault management unit of the SEC.
Watchdog
The on-chip software watchdog timer can supervise the
Blackfin+ core.
Bandwidth Monitor
Memory-to-memory DMA channels are equipped with a band-
width monitor mechanism. They can signal a system event or
fault when transactions tend to starve because system buses are
fully loaded with higher-priority traffic.
Signal Watchdogs
The eight general-purpose timers feature modes to monitor off-
chip signals. The watchdog period mode monitors whether
external signals toggle with a period within an expected range.
The watchdog width mode monitors whether the pulse widths
of external signals are within an expected range. Both modes
help to detect undesired toggling (or lack thereof) of
system-level signals.
Up/Down Count Mismatch Detection
The GP counter can monitor external signal pairs, such as
request/grant strobes. If the edge count mismatch exceeds the
expected range, the GP counter can flag this to the processor or
to the fault management unit of the SEC.
Fault Management
The fault management unit is part of the system event controller
(SEC). Any system event, whether a dual-bit uncorrectable ECC
error, or any peripheral status interrupt, can be defined as being
a fault. Additionally, the system events can be defined as an
interrupt to the core. If defined as such, the SEC forwards the
event to the fault management unit, which may automatically
reset the entire device for reboot, or simply toggle the
SYS_FAULT output pin to signal off-chip hardware. Optionally,
the fault management unit can delay the action taken through a
keyed sequence, to provide a final chance for the Blackfin+ core
to resolve the issue and to prevent the fault action from being
taken.
Rev. D | Page 10 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADDITIONAL PROCESSOR PERIPHERALS
The processor contains a rich set of peripherals connected to the
core through several high-bandwidth buses, providing flexibility
in system configuration as well as excellent overall system per-
formance (see the block diagram on Page 1). The processor
contains high-speed serial and parallel ports, an interrupt con-
troller for flexible management of interrupts from the on-chip
peripherals or external sources, and power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
The following sections describe additional peripherals that were
not previously described.
Timers
The processor includes several timers which are described in the
following sections.
General-Purpose Timers
There is one GP timer unit, and it provides eight general-pur-
pose programmable timers. Each timer has an external pin that
can be configured either as a pulse width modulator (PWM) or
timer output, as an input to clock the timer, or as a mechanism
for measuring pulse widths and periods of external events.
These timers can be synchronized to an external clock input on
the TIMER_TMRx pins, an external TIMER_CLK input pin, or
to the internal SCLK0.
These timer units can be used in conjunction with the UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The GP timers can generate interrupts to the processor core,
providing periodic events for synchronization to either the sys-
tem clock or to external signals. Timer events can also trigger
other peripherals through the TRU (for instance, to signal a
fault). Each timer may also be started and/or stopped by any
TRU master without core intervention.
Core Timer
The processor core also has its own dedicated timer. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generating periodic operating
system interrupts.
Watchdog Timer
The core includes a 32-bit timer, which may be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state, through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer initial-
izes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts down to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software that would normally reset the
timer has stopped running due to an external noise condition or
software error.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in its
timer control register that is set only upon a watchdog-gener-
ated reset.
Serial Ports (SPORTs)
Two synchronous serial ports (comprised of four half-SPORTs)
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’ audio
codecs, ADCs, and DACs. Each half-SPORT is made up of two
data lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial port data can be automatically transferred to and from
on-chip memory/external memory through dedicated DMA
channels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this
configuration, one SPORT provides two transmit signals while
the other SPORT provides the two receive signals. The frame
sync and clock are shared.
Serial ports operate in six modes:
• Standard DSP serial mode
•Multichannel (TDM) mode
•I
2
S mode
•Packed I
2
S mode
• Left-justified mode
•Right-justified mode
General-Purpose Counters
A 32-bit counter is provided that can operate in general-pur-
pose up/down count modes and can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual
thumbwheels. Count direction is either controlled by a level-
sensitive input pin or by two edge detectors.
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumbwheel devices. All three pins have a programmable
debouncing circuit.
Internal signals forwarded to a GP timer enable this timer to
measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by inter-
rupts when programmed count values are exceeded.
Parallel Peripheral Interface (PPI)
The processor provides a parallel peripheral interface (PPI) that
supports data widths up to 18 bits. The PPI supports direct con-
nection to TFT LCD panels, parallel analog-to-digital and
digital-to-analog converters, video encoders and decoders,
image sensor modules, and other general-purpose peripherals.
Rev. D | Page 11 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
The following features are supported in the PPI module:
• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, and 18 bits per clock.
• Various framed, non-framed, and general-purpose operat-
ing modes. Frame syncs can be generated internally or can
be supplied by an external device.
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decode.
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is
enabled, endianness can be configured to change the order
of packing/unpacking of bytes/words.
• RGB888 can be converted to RGB666 or RGB565 for trans-
mit modes.
• Various de-interleaving/interleaving modes for receiv-
ing/transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable (DEN) output available on
Frame Sync 3.
Serial Peripheral Interface (SPI) Ports
The processors have three industry-standard SPI-compatible
ports that allow it to communicate with multiple SPI-compati-
ble devices.
The baseline SPI peripheral is a synchronous, four-wire inter-
face consisting of two data pins, one device select pin, and a
gated clock pin. The two data pins allow full-duplex operation
to other SPI-compatible devices. An additional two (optional)
data pins are provided to support quad SPI operation. Enhanced
modes of operation such as flow control, fast mode, and dual
I/O mode (DIOM) are also supported. In addition, a direct
memory access (DMA) mode allows for transferring several
words with minimal CPU interaction.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a multi-
master environment by interfacing with several other devices,
acting as either a master device or a slave device. In a multimas-
ter environment, the SPI peripheral uses open-drain outputs to
avoid data bus contention. The flow control features enable slow
slave devices to interface with fast master devices by providing
an SPI Ready pin which flexibly controls the transfers.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has integrated DMA channels for both
transmit and receive data streams.
SPI Host Port (SPIHP)
The processor includes one SPI host port which may be used in
conjunction with any available SPI port to enhance its SPI slave
mode capabilities. The SPIHP allows a SPI host device access to
memory-mapped resources of the processor through a SPI
SRAM/FLASH style protocol. The following features are
included:
• Direct read/write of memory and memory-mapped
registers
• Support for pre-fetch for faster reads
• Support for SPI controllers that implement hardware-
based SPI memory protocol
• Error capture and reporting for protocol errors, bus errors,
and over/underflow
UART Ports
The processor provides two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminated by a con-
figurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion FIFO levels.
To help support the local interconnect network (LIN) protocols,
a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
2-Wire Controller Interface (TWI)
The processor includes a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I
2
C bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitra-
tion. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compati-
ble with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
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Mobile Storage Interface (MSI)
The mobile storage interface (MSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), and secure digital input/output cards (SDIO). The
following list describes the main features of the MSI controller:
• Support for a single MMC, SD memory, and SDIO card
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for eMMC 4.5 embedded NAND flash devices
• Support for power management and clock control
• An eleven-signal external interface with clock, command,
optional interrupt, and up to eight data lines
• Card interface clock generation from SCLK0 or SCLK1
• SDIO interrupt and read wait features
Controller Area Network (CAN)
A CAN controller implements the CAN 2.0B (active) protocol.
This protocol is an asynchronous communications protocol
used in both industrial and automotive control systems. The
CAN protocol is well suited for control applications due to its
capability to communicate reliably over a network. This is
because the protocol incorporates CRC checking, message error
tracking, and fault node confinement.
The CAN controller offers the following features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-
rable for receive or transmit)
• Dedicated acceptance masks for each mailbox
• Additional data filtering on first two bytes
• Support for both the standard (11-bit) and extended
(29-bit) identifier (ID) message formats
• Support for remote frames
• Active or passive network support
• CAN wake-up from hibernation mode (lowest static power
consumption mode)
• Interrupts, including: TX complete, RX complete, error
and global
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a pro-
grammable divider.
USB 2.0 On-the-Go Dual-Role Device Controller
The USB 2.0 on-the-go (OTG) dual-role device controller pro-
vides a low-cost connectivity solution for the growing adoption
of this bus standard in industrial applications, as well as con-
sumer mobile devices such as cell phones, digital still cameras,
and MP3 players. The USB 2.0 controller allows these devices to
transfer data using a point-to-point USB connection without
the need for a PC host. The module can operate in a traditional
USB peripheral-only mode as well as the host mode presented
in the OTG supplement to the USB 2.0 specification.
The USB clock is provided through a dedicated external crystal
or crystal oscillator.
The USB OTG dual-role device controller includes a phase
locked loop with programmable multipliers to generate the nec-
essary internal clocking frequency for USB.
Housekeeping ADC (HADC)
The HADC provides a general-purpose, multichannel succes-
sive approximation analog-to-digital converter. It supports the
following features:
• 12-bit ADC core with built-in sample and hold
• 4 single-ended input channels
• Throughput rates up to 1 MSPS
• Single external reference with analog inputs between 0 V
and 3.3 V
• Selectable ADC clock frequency including the ability to
program a prescaler
• Adaptable conversion type: allows single or continuous
conversion with option of autoscan
• Auto sequencing capability with up to 4 autoconversions in
a single session. Each conversion can be programmed to
select any input channel.
• Four data registers (individually addressable) to store con-
version values
System Crossbars (SCB)
The system crossbars (SCB) are the fundamental building
blocks of a switch-fabric style for (on-chip) system bus inter-
connection. The SCBs connect system bus masters to system
bus slaves, providing concurrent data transfer between multiple
bus masters and multiple bus slaves. A hierarchical model—
built from multiple SCBs—provides a power and area efficient
system interconnect, which satisfies the performance and flexi-
bility requirements of a specific system.
The SCBs provide the following features:
• Highly efficient, pipelined bus transfer protocol for sus-
tained throughput
• Full-duplex bus operation for flexibility and reduced
latency
• Concurrent bus transfer support to allow multiple bus
masters to access bus slaves simultaneously
• Protection model (privileged/secure) support for selective
bus interconnect protection
POWER AND CLOCK MANAGEMENT
The processor provides three operating modes, each with a dif-
ferent performance/power profile. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 5 for a summary of the power settings for each mode.
Rev. D | Page 13 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
System Crystal Oscillator and USB Crystal Oscillator
The processor can be clocked by an external crystal (see
Figure 4), a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator. If an external clock is used, it
should be a TTL compatible signal and must not be halted,
changed, or operated below the specified frequency during nor-
mal operation. This signal is connected to the SYS_CLKIN pin
of the processor. When an external clock is used, the SYS_XTAL
pin must be left unconnected. Alternatively, because the proces-
sor includes an on-chip oscillator circuit, an external crystal
may be used.
For fundamental frequency operation, use the circuit shown in
Figure 4. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKIN and
SYS_XTAL pins. The on-chip resistance between SYS_CLKIN
and the SYS_XTAL pin is in the 500 kΩ range. Further parallel
resistors are typically not recommended.
The two capacitors and the series resistor shown in Figure 4
fine-tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 4 are typical values
only. The capacitor values are dependent upon the load capaci-
tance recommendations of the crystal manufacturer and the
PCB physical layout. The resistor value depends on the drive
level specified by the crystal manufacturer. The user should ver-
ify the customized values based on careful investigations on
multiple devices over the required temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP (www.ana-
log.com/ee-168).
The same recommendations may be used for the USB crystal
oscillator.
Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the processor.
Connect RTC pins RTC_CLKIN and RTC_XTAL with external
components as shown in Figure 5.
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low power state. The RTC provides several pro-
grammable interrupt options, including interrupt per second,
minute, hour, or day clock ticks, interrupt on programmable
stopwatch countdown, or interrupt at a programmed alarm
time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and a 32,768-day counter. When the alarm
interrupt is enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value in
the alarm control register. There are two alarms. The first alarm
is for a time of day. The second alarm is for a specific day and
time of that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch inter-
rupt is enabled and the counter underflows, an interrupt is
generated.
Clock Generation
The clock generation unit (CGU) generates all on-chip clocks
and synchronization signals. Multiplication factors are pro-
grammed to define the PLLCLK frequency. Programmable
values divide the PLLCLK frequency to generate the core clock
(CCLK), the system clocks (SYSCLK, SCLK0, and SCLK1), the
LPDDR or DDR2 clock (DCLK), and the output clock (OCLK).
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value, and the PLL logic executes the changes so that it
transitions smoothly from the current conditions to the new
ones.
Figure 4. External Crystal Connection
SYS_CLKIN
TO PLL
CIRCUITRY
FOR OVERTONE
OPERATION ONLY:
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18pF SHOULD BE TREATED AS A MAXIMUM.
18 pF* 18 pF*
*
BLACKFIN
ȍ
SYS_XTAL
ȍ
Figure 5. External Components for RTC
RTC_CLKIN RTC_XTAL
X1
R1
NOTE: CRYSTAL LOAD CAPACITORS
ARE NOT NECESSARY IN MOST CASES.
0ȍ
Rev. D | Page 14 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SYS_CLKIN oscillations start when power is applied to the
VDD_EXT pins. The rising edge of SYS_HWRST can be
applied after all voltage supplies are within specifications, and
SYS_CLKIN oscillations are stable.
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the SYS_
CLKIN input. Clock generation faults (for example, PLL
unlock) may trigger a reset by hardware. The clocks shown in
Table 3 can be output on the SYS_CLKOUT pin.
Power Management
As shown in Table 4, the processor supports multiple power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. There are no
sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate Specifi-
cations table for processor operating conditions; even if the
feature/peripheral is not used.
The dynamic power management feature of the processor
allows the processor’s core clock frequency (f
CCLK
) to be dynam-
ically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
See Table 5 for a summary of the power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core and to all synchronous
peripherals. Asynchronous peripherals may still be running but
cannot access internal resources or external memory.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core and to all of the
peripherals. This setting signals the external voltage regulator
supplying the VDD_INT pins to shut off using the SYS_
EXTWAKE signal, which provides the lowest static power
dissipation.
Any critical information stored internally (for example, mem-
ory contents, register contents, and other information) must be
written to a nonvolatile storage device (or self-refreshed
DRAM) prior to removing power if the processor state is to be
preserved.
Because the V
DD_EXT
pins can still be supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
Reset Control Unit
Reset is the initial state of the whole processor or the core and is
the result of a hardware- or software-triggered event. In this
state, all control registers are set to their default values and func-
tional units are idle. Exiting a full system reset starts with the
core being ready to boot.
The reset control unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional require-
ments and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions puts the system into an undefined state or causes
resources to stall. This is particularly important when the core is
reset (programs must ensure that there is no pending system
activity involving the core when it is being reset).
Table 3. Clock Dividers
Clock Source
Divider (if Available on
SYS_CLKOUT)
CCLK (Core Clock) By 16
SYSCLK (System Clock) By 8
SCLK0 (System Clock, All Periph-
erals not Covered by SCLK1)
By 1
SCLK1 (System Clock for Crypto
Engines and MDMA)
By 8
DCLK (LPDDR/DDR2 Clock) By 8
OCLK (Output Clock) Programmable
CLKBUF None, direct from SYS_CLKIN
Table 4. Power Domains
Power Domain V
DD
Range
All Internal Logic V
DD_INT
DDR2/LPDDR V
DD_DMC
USB V
DD_USB
OTP Memory V
DD_OTP
HADC V
DD_HADC
RTC V
DD_RTC
All Other I/O (Includes SYS, JTAG, and Ports Pins) V
DD_EXT
Table 5. Power Settings
Mode/State PLL
PLL
Bypassed f
CCLK
f
SYSCLK
,
f
DCLK
,
f
SCLK0
,
f
SCLK1
Core
Power
Full On Enabled No Enabled Enabled On
Deep Sleep Disabled — Disabled Disabled On
Hibernate Disabled — Disabled Disabled Off
Rev. D | Page 15 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
From a system perspective, reset is defined by both the reset tar-
get and the reset source described as follows in the following list.
Target defined:
• Hardware Reset—All functional units are set to their
default states without exception. History is lost.
• System Reset—All functional units except the RCU are set
to their default states.
• Core-only Reset—Affects the core only. The system soft-
ware should guarantee that the core, while in reset state, is
not accessed by any bus master.
Source defined:
• Hardware Reset—The SYS_HWRST input signal is
asserted active (pulled down).
• System Reset—May be triggered by software (writing to the
RCU_CTL register) or by another functional unit such as
the dynamic power management (DPM) unit (hibernate)
or any of the system event controller (SEC), trigger routing
unit (TRU), or emulator inputs.
• Core-only Reset—Triggered by software.
• Trigger request (peripheral).
Voltage Regulation
The processor requires an external voltage regulator to power
the VDD_INT pins. To reduce standby power consumption, the
external voltage regulator can be signaled through
SYS_EXTWAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.
While in the hibernate state, all external supply pins (VDD_
EXT, VDD_USB, and VDD_DMC) can still be powered, elimi-
nating the need for external buffers. The external voltage
regulator can be activated from this power down state by assert-
ing the SYS_HWRST pin, which then initiates a boot sequence.
SYS_EXTWAKE indicates a wake-up to the external voltage
regulator.
SYSTEM DEBUG
The processor includes various features that allow for easy sys-
tem debug. These are described in the following sections.
System Watchpoint Unit
The system watchpoint unit (SWU) is a single module which
connects to a single system bus and provides for transaction
monitoring. One SWU is attached to the bus going to each
system slave. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of regis-
ters with associated hardware. These four SWU match groups
operate independently, but share common event (interrupt,
trigger, and others) outputs.
Debug Access Port
The debug access port (DAP) provides IEEE-1149.1 JTAG
interface support through its JTAG debug and serial wire debug
port (SWJ-DP). SWJ-DP is a combined JTAG-DP and SW-DP
that enables either serial wire debug (SWD) or a JTAG emulator
to be connected to a target. SWD signals share the same pins as
JTAG. The DAP provides an optional instrumentation trace for
both the core and system. It provides a trace stream that con-
forms to MIPI System Trace Protocol version 2 (STPv2).
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (CrossCore
®
Embedded Studio),
evaluation products, emulators, and a wide variety of software
add-ins.
Integrated Development Environments (IDEs)
CrossCore Embedded Studio is based on the Eclipse
TM
frame-
work. Supporting most Analog Devices processor families, it is
the IDE of choice for future processors, including multicore
devices. CrossCore Embedded Studio seamlessly integrates
available software add-ins to support real time operating sys-
tems, file systems, TCP/IP stacks, USB stacks, algorithmic
software modules, and evaluation hardware board support
packages. For more information, visit www.analog.com/cces.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides a wide range
of EZ-KIT Lite
®
evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders
®
, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information,
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE, a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio installed (sold separately), engineers can
develop software for supported EZ-KITs or any custom system
utilizing supported Analog Devices processors.
Rev. D | Page 16 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF706 EZ-KIT Mini
The ADSP-BF706 EZ-KIT Mini
TM
product (ADZS-BF706-
EZMini) contains the ADSP-BF706 processor and is shipped
with all of the necessary hardware. Users can start their evalua-
tion immediately. The EZ-KIT Mini product includes the
standalone evaluation board and USB cable. The EZ-KIT Mini
ships with an on-board debug agent.
The evaluation board is designed to be used in conjunction with
the CrossCore Embedded Studio (CCES) development tools to
test capabilities of the ADSP-BF706 Blackfin processor.
Blackfin Low Power Imaging Platform (BLIP)
The Blackfin low power imaging platform (BLIP) integrates the
ADSP-BF707 Blackfin processor and Analog Devices software
code libraries. The code libraries are optimized to detect the
presence and behavior of humans or vehicles in indoor and out-
door environments. The BLIP hardware platform is delivered
preloaded with the occupancy software module.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
board support packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information, see the following web
pages:
•www.analog.com/ucos3
•www.analog.com/ucfs
•www.analog.com/ucusbd
•www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with CrossCore Embedded Studio. For more
information, visit www.analog.com and search on “Blackfin
software modules” or “SHARC software modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each DAP-enabled processor, Analog
Devices supplies an IEEE 1149.1 JTAG test access port (TAP),
serial wire debug port (SWJ-DP), and trace capabilities.
In-circuit emulation is facilitated by use of the JTAG or SWD
interface. The emulator accesses the processor’s internal fea-
tures through the processor’s TAP, allowing the developer to
load code, set breakpoints, and view variables, memory, and
registers. The emulators require the target board to include a
header(s) that supports connection of the processor’s DAP to
the emulator for trace and debug.
Analog Devices emulators actively drive JTG_TRST high.
Third-party emulators may expect a pull-up on JTG_TRST and
therefore will not drive JTG_TRST high. When using this type
of third-party emulator JTG_TRST must still be driven low
during power-up reset, but should subsequently be driven high
externally before any emulation or boundary-scan operations.
See Power-Up Reset Timing for more information on POR
specifications.
For more details on target board design issues including
mechanical layout, single processor connections, signal buffer-
ing, signal termination, and emulator pod logic, contact the
factory for more information.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF70x pro-
cessors can be accessed electronically on our website:
•ADSP-BF70x Blackfin+ Processor Hardware Reference
•ADSP-BF70x Blackfin+ Processor Programming Reference
•ADSP-BF70x Blackfin+ Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The application signal chains page in the Circuits from the Lab
®
site (http:\\www.analog.com\circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. D | Page 17 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF70x DETAILED SIGNAL DESCRIPTIONS
Table 6 provides a detailed description of each pin.
Table 6. ADSP-BF70x Detailed Signal Descriptions
Port Name Direction Description
CAN_RX Input Receive. Typically an external CAN transceiver’s RX output.
CAN_TX Output Transmit. Typically an external CAN transceiver’s TX input.
CNT_DG Input Count Down and Gate. Depending on the mode of operation this input acts either as a count down
signal or a gate signal Count Down - This input causes the GP counter to decrement Gate - Stops the
GP counter from incrementing or decrementing.
CNT_UD Input Count Up and Direction. Depending on the mode of operation this input acts either as a count up
signal or a direction signal Count Up - This input causes the GP counter to increment Direction - Selects
whether the GP counter is incrementing or decrementing.
CNT_ZM Input Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the
pressing of a pushbutton.
DMC_Ann Output Address n. Address bus.
DMC_BAn Output Bank Address Input n. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE
command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR,
EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command.
DMC_CAS Output Column Address Strobe. Defines the operation for external dynamic memory to perform in
conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.
DMC_CK Output Clock. Outputs DCLK to external dynamic memory.
DMC_CK Output Clock (Complement). Complement of DMC_CK.
DMC_CKE Output Clock enable. Active high clock enables. Connects to the dynamic memory’s CKE input.
DMC_CSn Output Chip Select n. Commands are recognized by the memory only when this signal is asserted.
DMC_DQnn I/O Data n. Bidirectional Data bus.
DMC_LDM Output Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_LDQS I/O Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_LDQS I/O Data Strobe for Lower Byte (complement). Complement of LDQS. Not used in single-ended mode.
DMC_ODT Output On-die termination. Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.
DMC_RAS Output Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
DMC_UDM Output Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_UDQS I/O Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_UDQS I/O Data Strobe for Upper Byte (complement). Complement of DMC_UDQS. Not used in single-ended
mode.
DMC_VREF Input Voltage Reference. Connect to half of the VDD_DMC voltage. Applies to the DMC0_VREF pin.
DMC_WE Output Write Enable. Defines the operation for external dynamic memory to perform in conjunction with
other DMC command signals. Connect to the WE input of dynamic memory.
PPI_CLK I/O Clock. Input in external clock mode, output in internal clock mode.
PPI_Dnn I/O Data n. Bidirectional data bus.
PPI_FS1 I/O Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.
PPI_FS2 I/O Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.
PPI_FS3 I/O Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details.
HADC_VINn Input Analog Input at channel n. Analog voltage inputs for digital conversion.
Rev. D | Page 18 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
HADC_VREFN Input Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
HADC_VREFP Input External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
MSI_CD Input Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket.
MSI_CLK Output Clock. The clock signal applied to the connected device from the MSI.
MSI_CMD I/O Command. Used to send commands to and receive responses from the connected device.
MSI_Dn I/O Data n. Bidirectional data bus.
MSI_INT Input eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card’s interrupt output. An
interrupt may be sampled even when the MSI clock to the card is switched off.
Px_nn I/O Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming
information.
RTC_CLKIN Input Crystal input/external oscillator connection. Connect to an external clock source or crystal.
RTC_XTAL Output Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving
RTC_CLKIN.
SMC_ABEn Output Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an
asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1=0 and SMC_ABE0=1.
When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1=1 and
SMC_ABE0=0.
SMC_AMSn Output Memory Select n. Typically connects to the chip select of a memory device.
SMC_AOE Output Output Enable. Asserts at the beginning of the setup period of a read access.
SMC_ARDY Input Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when
further transactions may proceed.
SMC_ARE Output Read Enable. Asserts at the beginning of a read access.
SMC_AWE Output Write Enable. Asserts for the duration of a write access period.
SMC_Ann Output Address n. Address bus.
SMC_Dnn I/O Data n. Bidirectional data bus.
SPI_CLK I/O Clock. Input in slave mode, output in master mode.
SPI_D2 I/O Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.
SPI_D3 I/O Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled.
SPI_MISO I/O Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual
and Quad modes. Open-drain when ODM mode is enabled.
SPI_MOSI I/O Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual
and Quad modes. Open-drain when ODM mode is enabled.
SPI_RDY I/O Ready. Optional flow signal. Output in slave mode, input in master mode.
SPI_SELn Output Slave Select Output n. Used in Master mode to enable the desired slave.
SPI_SS Input Slave Select Input. Slave mode - Acts as the slave select input. Master mode- Optionally serves as an
error detection input for the SPI when there are multiple masters.
SPT_ACLK I/O Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
SPT_AD0 I/O Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_AD1 I/O Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_AFS I/O Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_ATDV Output Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)
Port Name Direction Description
Rev. D | Page 19 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SPT_BCLK I/O Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
SPT_BD0 I/O Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_BD1 I/O Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_BFS I/O Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_BTDV Output Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
SYS_BMODEn Input Boot Mode Control n. Selects the boot mode of the processor.
SYS_CLKIN Input Clock/Crystal Input. Connect to an external clock source or crystal.
SYS_CLKOUT Output Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter
of the HRM for more details.
SYS_EXTWAKE Output External Wake Control. Drives low during hibernate and high all other times. Typically connected to
the enable input of the voltage regulator controlling the VDD_INT supply.
SYS_FAULT I/O Active-Low Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
SYS_HWRST Input Processor Hardware Reset Control. Resets the device when asserted.
SYS_NMI Input Non-maskable Interrupt. See the processor hardware and programming references for more details.
SYS_RESOUT Output Reset Output. Indicates that the device is in the reset or hibernate state.
SYS_WAKEn Input Power Saving Mode Wakeup n. Wake-up source input for deep sleep and/or hibernate mode.
SYS_XTAL Output Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving
CLKIN.
JTG_SWCLK Input Serial Wire Clock. Clocks data into and out of the target during debug.
JTG_SWDIO I/O Serial Wire DIO. Sends and receives serial data to and from the target during debug.
JTG_SWO Output Serial Wire Out. Provides trace data to the emulator.
JTG_TCK Input JTAG Clock. JTAG test access port clock.
JTG_TDI Input JTAG Serial Data In. JTAG test access port data input.
JTG_TDO Output JTAG Serial Data Out. JTAG test access port data output.
JTG_TMS Input JTAG Mode Select. JTAG test access port mode select.
JTG_TRST Input JTAG Reset. JTAG test access port reset.
TM_ACIn Input Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
TM_ACLKn Input Alternate Clock n. Provides an additional time base for use by an individual timer.
TM_CLK Input Clock. Provides an additional global time base for use by all the GP timers.
TM_TMRn I/O Timer n. The main input/output signal for each timer.
TRACE_CLK Output Trace Clock. Clock output.
TRACE_Dnn Output Trace Data n. Unidirectional data bus.
TWI_SCL I/O Serial Clock. Clock output when master, clock input when slave.
TWI_SDA I/O Serial Data. Receives or transmits data.
UART_CTS Input Clear to Send. Flow control signal.
UART_RTS Output Request to Send. Flow control signal.
UART_RX Input Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
UART_TX Output Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements
of the device being communicated with.
USB_CLKIN Input Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet
specifications for frequency/tolerance information.
Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)
Port Name Direction Description
Rev. D | Page 20 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
USB_DM I/O Data –. Bidirectional differential data line.
USB_DP I/O Data +. Bidirectional differential data line.
USB_ID Input OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type
plug is sensed (signifying that the USB controller is the A device), but the input is high when a B-type
plug is sensed (signifying that the USB controller is the B device).
USB_VBC Output VBUS Control. Controls an external voltage source to supply VBUS when in host mode. May be
configured as open-drain. Polarity is configurable as well.
USB_VBUS I/O Bus Voltage. Connects to bus voltage in host and device modes.
USB_XTAL Output Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.
Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)
Port Name Direction Description
Rev. D | Page 21 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
184-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processor’s pin definitions are shown in Table 7. The col-
umns in this table provide the following information:
• Signal Name: The Signal Name column in the table
includes the signal name for every pin and (where applica-
ble) the GPIO multiplexed pin function for every pin.
• Description: The Description column in the table provides
a verbose (descriptive) name for the signal.
• General-Purpose Port: The Port column in the table shows
whether or not the signal is multiplexed with other signals
on a general-purpose I/O port pin.
• Pin Name: The Pin Name column in the table identifies the
name of the package pin (at power on reset) on which the
signal is located (if a single function pin) or is multiplexed
(if a general-purpose I/O pin).
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions
Signal Name Description Port Pin Name
CAN0_RX CAN0 Receive C PC_02
CAN0_TX CAN0 Transmit C PC_03
CAN1_RX CAN1 Receive A PA_12
CAN1_TX CAN1 Transmit A PA_13
CNT0_DG CNT0 Count Down and Gate A PA_07
CNT0_UD CNT0 Count Up and Direction A PA_15
CNT0_ZM CNT0 Count Zero Marker A PA_13
DMC0_A00 DMC0 Address 0 Not Muxed DMC0_A00
DMC0_A01 DMC0 Address 1 Not Muxed DMC0_A01
DMC0_A02 DMC0 Address 2 Not Muxed DMC0_A02
DMC0_A03 DMC0 Address 3 Not Muxed DMC0_A03
DMC0_A04 DMC0 Address 4 Not Muxed DMC0_A04
DMC0_A05 DMC0 Address 5 Not Muxed DMC0_A05
DMC0_A06 DMC0 Address 6 Not Muxed DMC0_A06
DMC0_A07 DMC0 Address 7 Not Muxed DMC0_A07
DMC0_A08 DMC0 Address 8 Not Muxed DMC0_A08
DMC0_A09 DMC0 Address 9 Not Muxed DMC0_A09
DMC0_A10 DMC0 Address 10 Not Muxed DMC0_A10
DMC0_A11 DMC0 Address 11 Not Muxed DMC0_A11
DMC0_A12 DMC0 Address 12 Not Muxed DMC0_A12
DMC0_A13 DMC0 Address 13 Not Muxed DMC0_A13
DMC0_BA0 DMC0 Bank Address Input 0 Not Muxed DMC0_BA0
DMC0_BA1 DMC0 Bank Address Input 1 Not Muxed DMC0_BA1
DMC0_BA2 DMC0 Bank Address Input 2 Not Muxed DMC0_BA2
DMC0_CAS DMC0 Column Address Strobe Not Muxed DMC0_CAS
DMC0_CK DMC0 Clock Not Muxed DMC0_CK
DMC0_CKE DMC0 Clock enable Not Muxed DMC0_CKE
DMC0_CK DMC0 Clock (complement) Not Muxed DMC0_CK
DMC0_CS0 DMC0 Chip Select 0 Not Muxed DMC0_CS0
DMC0_DQ00 DMC0 Data 0 Not Muxed DMC0_DQ00
DMC0_DQ01 DMC0 Data 1 Not Muxed DMC0_DQ01
DMC0_DQ02 DMC0 Data 2 Not Muxed DMC0_DQ02
DMC0_DQ03 DMC0 Data 3 Not Muxed DMC0_DQ03
DMC0_DQ04 DMC0 Data 4 Not Muxed DMC0_DQ04
DMC0_DQ05 DMC0 Data 5 Not Muxed DMC0_DQ05
DMC0_DQ06 DMC0 Data 6 Not Muxed DMC0_DQ06
Rev. D | Page 22 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
DMC0_DQ07 DMC0 Data 7 Not Muxed DMC0_DQ07
DMC0_DQ08 DMC0 Data 8 Not Muxed DMC0_DQ08
DMC0_DQ09 DMC0 Data 9 Not Muxed DMC0_DQ09
DMC0_DQ10 DMC0 Data 10 Not Muxed DMC0_DQ10
DMC0_DQ11 DMC0 Data 11 Not Muxed DMC0_DQ11
DMC0_DQ12 DMC0 Data 12 Not Muxed DMC0_DQ12
DMC0_DQ13 DMC0 Data 13 Not Muxed DMC0_DQ13
DMC0_DQ14 DMC0 Data 14 Not Muxed DMC0_DQ14
DMC0_DQ15 DMC0 Data 15 Not Muxed DMC0_DQ15
DMC0_LDM DMC0 Data Mask for Lower Byte Not Muxed DMC0_LDM
DMC0_LDQS DMC0 Data Strobe for Lower Byte Not Muxed DMC0_LDQS
DMC0_LDQS DMC0 Data Strobe for Lower Byte (complement) Not Muxed DMC0_LDQS
DMC0_ODT DMC0 On-die termination Not Muxed DMC0_ODT
DMC0_RAS DMC0 Row Address Strobe Not Muxed DMC0_RAS
DMC0_UDM DMC0 Data Mask for Upper Byte Not Muxed DMC0_UDM
DMC0_UDQS DMC0 Data Strobe for Upper Byte Not Muxed DMC0_UDQS
DMC0_UDQS DMC0 Data Strobe for Upper Byte (complement) Not Muxed DMC0_UDQS
DMC0_VREF DMC0 Voltage Reference Not Muxed DMC0_VREF
DMC0_WE DMC0 Write Enable Not Muxed DMC0_WE
GND Ground Not Muxed GND
GND_HADC Ground HADC Not Muxed GND_HADC
HADC0_VIN0 HADC0 Analog Input at channel 0 Not Muxed HADC0_VIN0
HADC0_VIN1 HADC0 Analog Input at channel 1 Not Muxed HADC0_VIN1
HADC0_VIN2 HADC0 Analog Input at channel 2 Not Muxed HADC0_VIN2
HADC0_VIN3 HADC0 Analog Input at channel 3 Not Muxed HADC0_VIN3
HADC0_VREFN HADC0 Ground Reference for ADC Not Muxed HADC0_VREFN
HADC0_VREFP HADC0 External Reference for ADC Not Muxed HADC0_VREFP
JTG_SWCLK TAPC0 Serial Wire Clock Not Muxed JTG_TCK_SWCLK
JTG_SWDIO TAPC0 Serial Wire DIO Not Muxed JTG_TMS_SWDIO
JTG_SWO TAPC0 Serial Wire Out Not Muxed JTG_TDO_SWO
JTG_TCK TAPC0 JTAG Clock Not Muxed JTG_TCK_SWCLK
JTG_TDI TAPC0 JTAG Serial Data In Not Muxed JTG_TDI
JTG_TDO TAPC0 JTAG Serial Data Out Not Muxed JTG_TDO_SWO
JTG_TMS TAPC0 JTAG Mode Select Not Muxed JTG_TMS_SWDIO
JTG_TRST TAPC0 JTAG Reset Not Muxed JTG_TRST
MSI0_CD MSI0 Card Detect A PA_08
MSI0_CLK MSI0 Clock C PC_09
MSI0_CMD MSI0 Command C PC_05
MSI0_D0 MSI0 Data 0 C PC_08
MSI0_D1 MSI0 Data 1 C PC_04
MSI0_D2 MSI0 Data 2 C PC_07
MSI0_D3 MSI0 Data 3 C PC_06
MSI0_D4 MSI0 Data 4 C PC_10
MSI0_D5 MSI0 Data 5 C PC_11
MSI0_D6 MSI0 Data 6 C PC_12
MSI0_D7 MSI0 Data 7 C PC_13
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 23 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
MSI0_INT MSI0 eSDIO Interrupt Input C PC_14
PA_00-PA_15 Position 00 through Position 15 A PA_00-PA_15
PB_00-PB_15 Position 00 through Position 15 B PB_00-PB_15
PC_00-PC_14 Position 00 through Position 14 C PC_00-PC_14
PPI0_CLK EPPI0 Clock A PA_14
PPI0_D00 EPPI0 Data 0 B PB_07
PPI0_D01 EPPI0 Data 1 B PB_06
PPI0_D02 EPPI0 Data 2 B PB_05
PPI0_D03 EPPI0 Data 3 B PB_04
PPI0_D04 EPPI0 Data 4 B PB_03
PPI0_D05 EPPI0 Data 5 B PB_02
PPI0_D06 EPPI0 Data 6 B PB_01
PPI0_D07 EPPI0 Data 7 B PB_00
PPI0_D08 EPPI0 Data 8 A PA_11
PPI0_D09 EPPI0 Data 9 A PA_10
PPI0_D10 EPPI0 Data 10 A PA_09
PPI0_D11 EPPI0 Data 11 A PA_08
PPI0_D12 EPPI0 Data 12 C PC_03
PPI0_D13 EPPI0 Data 13 C PC_02
PPI0_D14 EPPI0 Data 14 C PC_01
PPI0_D15 EPPI0 Data 15 C PC_00
PPI0_D16 EPPI0 Data 16 B PB_08
PPI0_D17 EPPI0 Data 17 B PB_09
PPI0_FS1 EPPI0 Frame Sync 1 (HSYNC) A PA_12
PPI0_FS2 EPPI0 Frame Sync 2 (VSYNC) A PA_13
PPI0_FS3 EPPI0 Frame Sync 3 (FIELD) A PA_15
RTC0_CLKIN RTC0 Crystal input/external oscillator connection Not Muxed RTC0_CLKIN
RTC0_XTAL RTC0 Crystal output Not Muxed RTC0_XTAL
SMC0_A01 SMC0 Address 1 A PA_08
SMC0_A02 SMC0 Address 2 A PA_09
SMC0_A03 SMC0 Address 3 A PA_10
SMC0_A04 SMC0 Address 4 A PA_11
SMC0_A05 SMC0 Address 5 A PA_07
SMC0_A06 SMC0 Address 6 A PA_06
SMC0_A07 SMC0 Address 7 A PA_05
SMC0_A08 SMC0 Address 8 A PA_04
SMC0_A09 SMC0 Address 9 C PC_01
SMC0_A10 SMC0 Address 10 C PC_02
SMC0_A11 SMC0 Address 11 C PC_03
SMC0_A12 SMC0 Address 12 C PC_04
SMC0_ABE0 SMC0 Byte Enable 0 A PA_00
SMC0_ABE1 SMC0 Byte Enable 1 A PA_01
SMC0_AMS0 SMC0 Memory Select 0 A PA_15
SMC0_AMS1 SMC0 Memory Select 1 A PA_02
SMC0_AOE SMC0 Output Enable A PA_12
SMC0_ARDY SMC0 Asynchronous Ready A PA_03
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 24 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SMC0_ARE SMC0 Read Enable A PA_13
SMC0_AWE SMC0 Write Enable A PA_14
SMC0_D00 SMC0 Data 0 B PB_07
SMC0_D01 SMC0 Data 1 B PB_06
SMC0_D02 SMC0 Data 2 B PB_05
SMC0_D03 SMC0 Data 3 B PB_04
SMC0_D04 SMC0 Data 4 B PB_03
SMC0_D05 SMC0 Data 5 B PB_02
SMC0_D06 SMC0 Data 6 B PB_01
SMC0_D07 SMC0 Data 7 B PB_00
SMC0_D08 SMC0 Data 8 B PB_08
SMC0_D09 SMC0 Data 9 B PB_09
SMC0_D10 SMC0 Data 10 B PB_10
SMC0_D11 SMC0 Data 11 B PB_11
SMC0_D12 SMC0 Data 12 B PB_12
SMC0_D13 SMC0 Data 13 B PB_13
SMC0_D14 SMC0 Data 14 B PB_14
SMC0_D15 SMC0 Data 15 B PB_15
SPI0_CLK SPI0 Clock B PB_00
SPI0_CLK SPI0 Clock C PC_04
SPI0_D2 SPI0 Data 2 B PB_03
SPI0_D2 SPI0 Data 2 C PC_08
SPI0_D3 SPI0 Data 3 B PB_07
SPI0_D3 SPI0 Data 3 C PC_09
SPI0_MISO SPI0 Master In, Slave Out B PB_01
SPI0_MISO SPI0 Master In, Slave Out C PC_06
SPI0_MOSI SPI0 Master Out, Slave In B PB_02
SPI0_MOSI SPI0 Master Out, Slave In C PC_07
SPI0_RDY SPI0 Ready A PA_06
SPI0_SEL1 SPI0 Slave Select Output 1 A PA_05
SPI0_SEL2 SPI0 Slave Select Output 2 A PA_06
SPI0_SEL3 SPI0 Slave Select Output 3 C PC_11
SPI0_SEL4 SPI0 Slave Select Output 4 B PB_04
SPI0_SEL5 SPI0 Slave Select Output 5 B PB_05
SPI0_SEL6 SPI0 Slave Select Output 6 B PB_06
SPI0_SS SPI0 Slave Select Input A PA_05
SPI1_CLK SPI1 Clock A PA_00
SPI1_MISO SPI1 Master In, Slave Out A PA_01
SPI1_MOSI SPI1 Master Out, Slave In A PA_02
SPI1_RDY SPI1 Ready A PA_03
SPI1_SEL1 SPI1 Slave Select Output 1 A PA_04
SPI1_SEL2 SPI1 Slave Select Output 2 A PA_03
SPI1_SEL3 SPI1 Slave Select Output 3 C PC_10
SPI1_SEL4 SPI1 Slave Select Output 4 A PA_14
SPI1_SS SPI1 Slave Select Input A PA_04
SPI2_CLK SPI2 Clock B PB_10
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 25 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SPI2_D2 SPI2 Data 2 B PB_13
SPI2_D3 SPI2 Data 3 B PB_14
SPI2_MISO SPI2 Master In, Slave Out B PB_11
SPI2_MOSI SPI2 Master Out, Slave In B PB_12
SPI2_RDY SPI2 Ready A PA_04
SPI2_SEL1 SPI2 Slave Select Output 1 B PB_15
SPI2_SEL2 SPI2 Slave Select Output 2 B PB_08
SPI2_SEL3 SPI2 Slave Select Output 3 B PB_09
SPI2_SS SPI2 Slave Select Input B PB_15
SPT0_ACLK SPORT0 Channel A Clock A PA_13
SPT0_ACLK SPORT0 Channel A Clock C PC_09
SPT0_AD0 SPORT0 Channel A Data 0 A PA_14
SPT0_AD0 SPORT0 Channel A Data 0 C PC_08
SPT0_AD1 SPORT0 Channel A Data 1 C PC_00
SPT0_AFS SPORT0 Channel A Frame Sync A PA_12
SPT0_AFS SPORT0 Channel A Frame Sync C PC_05
SPT0_ATDV SPORT0 Channel A Transmit Data Valid A PA_15
SPT0_BCLK SPORT0 Channel B Clock B PB_04
SPT0_BCLK SPORT0 Channel B Clock C PC_04
SPT0_BD0 SPORT0 Channel B Data 0 B PB_05
SPT0_BD0 SPORT0 Channel B Data 0 C PC_06
SPT0_BD1 SPORT0 Channel B Data 1 B PB_07
SPT0_BD1 SPORT0 Channel B Data 1 C PC_01
SPT0_BFS SPORT0 Channel B Frame Sync B PB_06
SPT0_BFS SPORT0 Channel B Frame Sync C PC_07
SPT0_BTDV SPORT0 Channel B Transmit Data Valid A PA_15
SPT1_ACLK SPORT1 Channel A Clock A PA_08
SPT1_AD0 SPORT1 Channel A Data 0 A PA_10
SPT1_AD1 SPORT1 Channel A Data 1 A PA_11
SPT1_AFS SPORT1 Channel A Frame Sync A PA_09
SPT1_ATDV SPORT1 Channel A Transmit Data Valid A PA_07
SPT1_BCLK SPORT1 Channel B Clock B PB_00
SPT1_BCLK SPORT1 Channel B Clock C PC_10
SPT1_BD0 SPORT1 Channel B Data 0 B PB_02
SPT1_BD0 SPORT1 Channel B Data 0 C PC_12
SPT1_BD1 SPORT1 Channel B Data 1 B PB_03
SPT1_BD1 SPORT1 Channel B Data 1 C PC_13
SPT1_BFS SPORT1 Channel B Frame Sync B PB_01
SPT1_BFS SPORT1 Channel B Frame Sync C PC_11
SPT1_BTDV SPORT1 Channel B Transmit Data Valid A PA_07
SPT1_BTDV SPORT1 Channel B Transmit Data Valid C PC_14
SYS_BMODE0 Boot Mode Control 0 Not Muxed SYS_BMODE0
SYS_BMODE1 Boot Mode Control 1 Not Muxed SYS_BMODE1
SYS_CLKIN Clock/Crystal Input Not Muxed SYS_CLKIN
SYS_CLKOUT Processor Clock Output Not Muxed SYS_CLKOUT
SYS_EXTWAKE External Wake Control Not Muxed SYS_EXTWAKE
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 26 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SYS_FAULT Active-Low Fault Output Not Muxed SYS_FAULT
SYS_HWRST Processor Hardware Reset Control Not Muxed SYS_HWRST
SYS_NMI Nonmaskable Interrupt Not Muxed SYS_NMI
SYS_RESOUT Reset Output Not Muxed SYS_RESOUT
SYS_WAKE0 Power Saving Mode Wake-up 0 B PB_07
SYS_WAKE1 Power Saving Mode Wake-up 1 B PB_08
SYS_WAKE2 Power Saving Mode Wake-up 2 B PB_12
SYS_WAKE3 Power Saving Mode Wake-up 3 C PC_02
SYS_WAKE4 Power Saving Mode Wake-up 4 A PA_12
SYS_XTAL Crystal Output Not Muxed SYS_XTAL
TM0_ACI0 TIMER0 Alternate Capture Input 0 C PC_03
TM0_ACI1 TIMER0 Alternate Capture Input 1 B PB_01
TM0_ACI2 TIMER0 Alternate Capture Input 2 C PC_07
TM0_ACI3 TIMER0 Alternate Capture Input 3 B PB_09
TM0_ACI4 TIMER0 Alternate Capture Input 4 C PC_01
TM0_ACI5 TIMER0 Alternate Capture Input 5 C PC_02
TM0_ACI6 TIMER0 Alternate Capture Input 6 A PA_12
TM0_ACLK0 TIMER0 Alternate Clock 0 C PC_04
TM0_ACLK1 TIMER0 Alternate Clock 1 C PC_10
TM0_ACLK2 TIMER0 Alternate Clock 2 C PC_09
TM0_ACLK3 TIMER0 Alternate Clock 3 B PB_00
TM0_ACLK4 TIMER0 Alternate Clock 4 B PB_10
TM0_ACLK5 TIMER0 Alternate Clock 5 A PA_14
TM0_ACLK6 TIMER0 Alternate Clock 6 B PB_04
TM0_CLK TIMER0 Clock B PB_06
TM0_TMR0 TIMER0 Timer 0 A PA_05
TM0_TMR1 TIMER0 Timer 1 A PA_06
TM0_TMR2 TIMER0 Timer 2 A PA_07
TM0_TMR3 TIMER0 Timer 3 C PC_05
TM0_TMR4 TIMER0 Timer 4 A PA_09
TM0_TMR5 TIMER0 Timer 5 A PA_10
TM0_TMR6 TIMER0 Timer 6 A PA_11
TM0_TMR7 TIMER0 Timer 7 A PA_04
TRACE0_CLK TPIU0 Trace Clock B PB_10
TRACE0_D00 TPIU0 Trace Data 0 B PB_15
TRACE0_D01 TPIU0 Trace Data 1 B PB_14
TRACE0_D02 TPIU0 Trace Data 2 B PB_13
TRACE0_D03 TPIU0 Trace Data 3 B PB_12
TRACE0_D04 TPIU0 Trace Data 4 B PB_11
TRACE0_D05 TPIU0 Trace Data 5 A PA_02
TRACE0_D06 TPIU0 Trace Data 6 A PA_01
TRACE0_D07 TPIU0 Trace Data 7 A PA_00
TWI0_SCL TWI0 Serial Clock Not Muxed TWI0_SCL
TWI0_SDA TWI0 Serial Data Not Muxed TWI0_SDA
UART0_CTS UART0 Clear to Send C PC_03
UART0_RTS UART0 Request to Send C PC_02
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 27 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
UART0_RX UART0 Receive B PB_09
UART0_TX UART0 Transmit B PB_08
UART1_CTS UART1 Clear to Send B PB_14
UART1_RTS UART1 Request to Send B PB_13
UART1_RX UART1 Receive C PC_01
UART1_TX UART1 Transmit C PC_00
USB0_CLKIN USB0 Clock/Crystal Input Not Muxed USB0_CLKIN
USB0_DM USB0 Data – Not Muxed USB0_DM
USB0_DP USB0 Data + Not Muxed USB0_DP
USB0_ID USB0 OTG ID Not Muxed USB0_ID
USB0_VBC USB0 VBUS Control Not Muxed USB0_VBC
USB0_VBUS USB0 Bus Voltage Not Muxed USB0_VBUS
USB0_XTAL USB0 Crystal Not Muxed USB0_XTAL
VDD_DMC VDD for DMC Not Muxed VDD_DMC
VDD_EXT External VDD Not Muxed VDD_EXT
VDD_HADC VDD for HADC Not Muxed VDD_HADC
VDD_INT Internal VDD Not Muxed VDD_INT
VDD_OTP VDD for OTP Not Muxed VDD_OTP
VDD_RTC VDD for RTC Not Muxed VDD_RTC
VDD_USB VDD for USB Not Muxed VDD_USB
Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 28 of 114 | February 2019
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GPIO MULTIPLEXING FOR 184-BALL CSP_BGA
Table 8 through Table 10 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the 184-ball
CSP_BGA package.
Table 8. Signal Multiplexing for Port A
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PA_00 SPI1_CLK TRACE0_D07 SMC0_ABE0
PA_01 SPI1_MISO TRACE0_D06 SMC0_ABE1
PA_02 SPI1_MOSI TRACE0_D05 SMC0_AMS1
PA_03 SPI1_SEL2 SPI1_RDY SMC0_ARDY
PA_04 SPI1_SEL1 TM0_TMR7 SPI2_RDY SMC0_A08 SPI1_SS
PA_05 TM0_TMR0 SPI0_SEL1 SMC0_A07 SPI0_SS
PA_06 TM0_TMR1 SPI0_SEL2 SPI0_RDY SMC0_A06
PA_07 TM0_TMR2 SPT1_BTDV SPT1_ATDV SMC0_A05 CNT0_DG
PA_08 PPI0_D11 MSI0_CD SPT1_ACLK SMC0_A01
PA_09 PPI0_D10 TM0_TMR4 SPT1_AFS SMC0_A02
PA_10 PPI0_D09 TM0_TMR5 SPT1_AD0 SMC0_A03
PA_11 PPI0_D08 TM0_TMR6 SPT1_AD1 SMC0_A04
PA_12 PPI0_FS1 CAN1_RX SPT0_AFS SMC0_AOE TM0_ACI6/SYS_WAKE4
PA_13 PPI0_FS2 CAN1_TX SPT0_ACLK SMC0_ARE CNT0_ZM
PA_14 PPI0_CLK SPI1_SEL4 SPT0_AD0 SMC0_AWE TM0_ACLK5
PA_15 PPI0_FS3 SPT0_ATDV SPT0_BTDV SMC0_AMS0 CNT0_UD
Table 9. Signal Multiplexing for Port B
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PB_00 PPI0_D07 SPT1_BCLK SPI0_CLK SMC0_D07 TM0_ACLK3
PB_01 PPI0_D06 SPT1_BFS SPI0_MISO SMC0_D06 TM0_ACI1
PB_02 PPI0_D05 SPT1_BD0 SPI0_MOSI SMC0_D05
PB_03 PPI0_D04 SPT1_BD1 SPI0_D2 SMC0_D04
PB_04 PPI0_D03 SPT0_BCLK SPI0_SEL4 SMC0_D03 TM0_ACLK6
PB_05 PPI0_D02 SPT0_BD0 SPI0_SEL5 SMC0_D02
PB_06 PPI0_D01 SPT0_BFS SPI0_SEL6 SMC0_D01 TM0_CLK
PB_07 PPI0_D00 SPT0_BD1 SPI0_D3 SMC0_D00 SYS_WAKE0
PB_08 UART0_TX PPI0_D16 SPI2_SEL2 SMC0_D08 SYS_WAKE1
PB_09 UART0_RX PPI0_D17 SPI2_SEL3 SMC0_D09 TM0_ACI3
PB_10 SPI2_CLK TRACE0_CLK SMC0_D10 TM0_ACLK4
PB_11 SPI2_MISO TRACE0_D04 SMC0_D11
PB_12 SPI2_MOSI TRACE0_D03 SMC0_D12 SYS_WAKE2
PB_13 SPI2_D2 UART1_RTS TRACE0_D02 SMC0_D13
PB_14 SPI2_D3 UART1_CTS TRACE0_D01 SMC0_D14
PB_15 SPI2_SEL1 TRACE0_D00 SMC0_D15 SPI2_SS
Rev. D | Page 29 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 10. Signal Multiplexing for Port C
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PC_00 UART1_TX SPT0_AD1 PPI0_D15
PC_01 UART1_RX SPT0_BD1 PPI0_D14 SMC0_A09 TM0_ACI4
PC_02 UART0_RTS CAN0_RX PPI0_D13 SMC0_A10 TM0_ACI5/SYS_WAKE3
PC_03 UART0_CTS CAN0_TX PPI0_D12 SMC0_A11 TM0_ACI0
PC_04 SPT0_BCLK SPI0_CLK MSI0_D1 SMC0_A12 TM0_ACLK0
PC_05 SPT0_AFS TM0_TMR3 MSI0_CMD
PC_06 SPT0_BD0 SPI0_MISO MSI0_D3
PC_07 SPT0_BFS SPI0_MOSI MSI0_D2 TM0_ACI2
PC_08 SPT0_AD0 SPI0_D2 MSI0_D0
PC_09 SPT0_ACLK SPI0_D3 MSI0_CLK TM0_ACLK2
PC_10 SPT1_BCLK MSI0_D4 SPI1_SEL3 TM0_ACLK1
PC_11 SPT1_BFS MSI0_D5 SPI0_SEL3
PC_12 SPT1_BD0 MSI0_D6
PC_13 SPT1_BD1 MSI0_D7
PC_14 SPT1_BTDV MSI0_INT
Rev. D | Page 30 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
12 mm × 12 mm 88-LEAD LFCSP (QFN) SIGNAL DESCRIPTIONS
The processor’s pin definitions are shown in Table 11. The col-
umns in this table provide the following information:
• Signal Name: The Signal Name column in the table
includes the signal name for every pin and (where applica-
ble) the GPIO multiplexed pin function for every pin.
• Description: The Description column in the table provides
a verbose (descriptive) name for the signal.
• General-Purpose Port: The Port column in the table shows
whether or not the signal is multiplexed with other signals
on a general-purpose I/O port pin.
• Pin Name: The Pin Name column in the table identifies the
name of the package pin (at power on reset) on which the
signal is located (if a single function pin) or is multiplexed
(if a general-purpose I/O pin).
Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions
Signal Name Description Port Pin Name
CAN0_RX CAN0 Receive C PC_02
CAN0_TX CAN0 Transmit C PC_03
CAN1_RX CAN1 Receive A PA_12
CAN1_TX CAN1 Transmit A PA_13
CNT0_DG CNT0 Count Down and Gate A PA_07
CNT0_UD CNT0 Count Up and Direction A PA_15
CNT0_ZM CNT0 Count Zero Marker A PA_13
GND Ground Not Muxed GND
JTG_SWCLK TAPC0 Serial Wire Clock Not Muxed JTG_TCK_SWCLK
JTG_SWDIO TAPC0 Serial Wire DIO Not Muxed JTG_TMS_SWDIO
JTG_SWO TAPC0 Serial Wire Out Not Muxed JTG_TDO_SWO
JTG_TCK TAPC0 JTAG Clock Not Muxed JTG_TCK_SWCLK
JTG_TDI TAPC0 JTAG Serial Data In Not Muxed JTG_TDI
JTG_TDO TAPC0 JTAG Serial Data Out Not Muxed JTG_TDO_SWO
JTG_TMS TAPC0 JTAG Mode Select Not Muxed JTG_TMS_SWDIO
JTG_TRST TAPC0 JTAG Reset Not Muxed JTG_TRST
MSI0_CD MSI0 Card Detect A PA_08
MSI0_CLK MSI0 Clock C PC_09
MSI0_CMD MSI0 Command C PC_05
MSI0_D0 MSI0 Data 0 C PC_08
MSI0_D1 MSI0 Data 1 C PC_04
MSI0_D2 MSI0 Data 2 C PC_07
MSI0_D3 MSI0 Data 3 C PC_06
MSI0_D4 MSI0 Data 4 C PC_10
PA_00-PA_15 Position 00 through Position 15 A PA_00-PA_15
PB_00-PB_15 Position 00 through Position 15 B PB_00-PB_15
PC_00-PC_10 Position 00 through Position 10 C PC_00-PC_10
PPI0_CLK EPPI0 Clock A PA_14
PPI0_D00 EPPI0 Data 0 B PB_07
PPI0_D01 EPPI0 Data 1 B PB_06
PPI0_D02 EPPI0 Data 2 B PB_05
PPI0_D03 EPPI0 Data 3 B PB_04
PPI0_D04 EPPI0 Data 4 B PB_03
PPI0_D05 EPPI0 Data 5 B PB_02
PPI0_D06 EPPI0 Data 6 B PB_01
PPI0_D07 EPPI0 Data 7 B PB_00
Rev. D | Page 31 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PPI0_D08 EPPI0 Data 8 A PA_11
PPI0_D09 EPPI0 Data 9 A PA_10
PPI0_D10 EPPI0 Data 10 A PA_09
PPI0_D11 EPPI0 Data 11 A PA_08
PPI0_D12 EPPI0 Data 12 C PC_03
PPI0_D13 EPPI0 Data 13 C PC_02
PPI0_D14 EPPI0 Data 14 C PC_01
PPI0_D15 EPPI0 Data 15 C PC_00
PPI0_D16 EPPI0 Data 16 B PB_08
PPI0_D17 EPPI0 Data 17 B PB_09
PPI0_FS1 EPPI0 Frame Sync 1 (HSYNC) A PA_12
PPI0_FS2 EPPI0 Frame Sync 2 (VSYNC) A PA_13
PPI0_FS3 EPPI0 Frame Sync 3 (FIELD) A PA_15
RTC0_CLKIN RTC0 Crystal input/external oscillator connection Not Muxed RTC0_CLKIN
RTC0_XTAL RTC0 Crystal output Not Muxed RTC0_XTAL
SMC0_A01 SMC0 Address 1 A PA_08
SMC0_A02 SMC0 Address 2 A PA_09
SMC0_A03 SMC0 Address 3 A PA_10
SMC0_A04 SMC0 Address 4 A PA_11
SMC0_A05 SMC0 Address 5 A PA_07
SMC0_A06 SMC0 Address 6 A PA_06
SMC0_A07 SMC0 Address 7 A PA_05
SMC0_A08 SMC0 Address 8 A PA_04
SMC0_A09 SMC0 Address 9 C PC_01
SMC0_A10 SMC0 Address 10 C PC_02
SMC0_A11 SMC0 Address 11 C PC_03
SMC0_A12 SMC0 Address 12 C PC_04
SMC0_ABE0 SMC0 Byte Enable 0 A PA_00
SMC0_ABE1 SMC0 Byte Enable 1 A PA_01
SMC0_AMS0 SMC0 Memory Select 0 A PA_15
SMC0_AMS1 SMC0 Memory Select 1 A PA_02
SMC0_AOE SMC0 Output Enable A PA_12
SMC0_ARDY SMC0 Asynchronous Ready A PA_03
SMC0_ARE SMC0 Read Enable A PA_13
SMC0_AWE SMC0 Write Enable A PA_14
SMC0_D00 SMC0 Data 0 B PB_07
SMC0_D01 SMC0 Data 1 B PB_06
SMC0_D02 SMC0 Data 2 B PB_05
SMC0_D03 SMC0 Data 3 B PB_04
SMC0_D04 SMC0 Data 4 B PB_03
SMC0_D05 SMC0 Data 5 B PB_02
SMC0_D06 SMC0 Data 6 B PB_01
SMC0_D07 SMC0 Data 7 B PB_00
SMC0_D08 SMC0 Data 8 B PB_08
SMC0_D09 SMC0 Data 9 B PB_09
SMC0_D10 SMC0 Data 10 B PB_10
Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 32 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SMC0_D11 SMC0 Data 11 B PB_11
SMC0_D12 SMC0 Data 12 B PB_12
SMC0_D13 SMC0 Data 13 B PB_13
SMC0_D14 SMC0 Data 14 B PB_14
SMC0_D15 SMC0 Data 15 B PB_15
SPI0_CLK SPI0 Clock B PB_00
SPI0_CLK SPI0 Clock C PC_04
SPI0_D2 SPI0 Data 2 B PB_03
SPI0_D2 SPI0 Data 2 C PC_08
SPI0_D3 SPI0 Data 3 B PB_07
SPI0_D3 SPI0 Data 3 C PC_09
SPI0_MISO SPI0 Master In, Slave Out B PB_01
SPI0_MISO SPI0 Master In, Slave Out C PC_06
SPI0_MOSI SPI0 Master Out, Slave In B PB_02
SPI0_MOSI SPI0 Master Out, Slave In C PC_07
SPI0_RDY SPI0 Ready A PA_06
SPI0_SEL1 SPI0 Slave Select Output 1 A PA_05
SPI0_SEL2 SPI0 Slave Select Output 2 A PA_06
SPI0_SEL4 SPI0 Slave Select Output 4 B PB_04
SPI0_SEL5 SPI0 Slave Select Output 5 B PB_05
SPI0_SEL6 SPI0 Slave Select Output 6 B PB_06
SPI0_SS SPI0 Slave Select Input A PA_05
SPI1_CLK SPI1 Clock A PA_00
SPI1_MISO SPI1 Master In, Slave Out A PA_01
SPI1_MOSI SPI1 Master Out, Slave In A PA_02
SPI1_RDY SPI1 Ready A PA_03
SPI1_SEL1 SPI1 Slave Select Output 1 A PA_04
SPI1_SEL2 SPI1 Slave Select Output 2 A PA_03
SPI1_SEL3 SPI1 Slave Select Output 3 C PC_10
SPI1_SEL4 SPI1 Slave Select Output 4 A PA_14
SPI1_SS SPI1 Slave Select Input A PA_04
SPI2_CLK SPI2 Clock B PB_10
SPI2_D2 SPI2 Data 2 B PB_13
SPI2_D3 SPI2 Data 3 B PB_14
SPI2_MISO SPI2 Master In, Slave Out B PB_11
SPI2_MOSI SPI2 Master Out, Slave In B PB_12
SPI2_RDY SPI2 Ready A PA_04
SPI2_SEL1 SPI2 Slave Select Output 1 B PB_15
SPI2_SEL2 SPI2 Slave Select Output 2 B PB_08
SPI2_SEL3 SPI2 Slave Select Output 3 B PB_09
SPI2_SS SPI2 Slave Select Input B PB_15
SPT0_ACLK SPORT0 Channel A Clock A PA_13
SPT0_ACLK SPORT0 Channel A Clock C PC_09
SPT0_AD0 SPORT0 Channel A Data 0 A PA_14
SPT0_AD0 SPORT0 Channel A Data 0 C PC_08
SPT0_AD1 SPORT0 Channel A Data 1 C PC_00
Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 33 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SPT0_AFS SPORT0 Channel A Frame Sync A PA_12
SPT0_AFS SPORT0 Channel A Frame Sync C PC_05
SPT0_ATDV SPORT0 Channel A Transmit Data Valid A PA_15
SPT0_BCLK SPORT0 Channel B Clock B PB_04
SPT0_BCLK SPORT0 Channel B Clock C PC_04
SPT0_BD0 SPORT0 Channel B Data 0 B PB_05
SPT0_BD0 SPORT0 Channel B Data 0 C PC_06
SPT0_BD1 SPORT0 Channel B Data 1 B PB_07
SPT0_BD1 SPORT0 Channel B Data 1 C PC_01
SPT0_BFS SPORT0 Channel B Frame Sync B PB_06
SPT0_BFS SPORT0 Channel B Frame Sync C PC_07
SPT0_BTDV SPORT0 Channel B Transmit Data Valid A PA_15
SPT1_ACLK SPORT1 Channel A Clock A PA_08
SPT1_AD0 SPORT1 Channel A Data 0 A PA_10
SPT1_AD1 SPORT1 Channel A Data 1 A PA_11
SPT1_AFS SPORT1 Channel A Frame Sync A PA_09
SPT1_ATDV SPORT1 Channel A Transmit Data Valid A PA_07
SPT1_BCLK SPORT1 Channel B Clock B PB_00
SPT1_BCLK SPORT1 Channel B Clock C PC_10
SPT1_BD0 SPORT1 Channel B Data 0 B PB_02
SPT1_BD1 SPORT1 Channel B Data 1 B PB_03
SPT1_BFS SPORT1 Channel B Frame Sync B PB_01
SPT1_BTDV SPORT1 Channel B Transmit Data Valid A PA_07
SYS_BMODE0 Boot Mode Control 0 Not Muxed SYS_BMODE0
SYS_BMODE1 Boot Mode Control 1 Not Muxed SYS_BMODE1
SYS_CLKIN Clock/Crystal Input Not Muxed SYS_CLKIN
SYS_CLKOUT Processor Clock Output Not Muxed SYS_CLKOUT
SYS_EXTWAKE External Wake Control Not Muxed SYS_EXTWAKE
SYS_FAULT Active-Low Fault Output Not Muxed SYS_FAULT
SYS_HWRST Processor Hardware Reset Control Not Muxed SYS_HWRST
SYS_NMI Non-maskable Interrupt Not Muxed SYS_NMI
SYS_RESOUT Reset Output Not Muxed SYS_RESOUT
SYS_WAKE0 Power Saving Mode Wake-up 0 B PB_07
SYS_WAKE1 Power Saving Mode Wake-up 1 B PB_08
SYS_WAKE2 Power Saving Mode Wake-up 2 B PB_12
SYS_WAKE3 Power Saving Mode Wake-up 3 C PC_02
SYS_WAKE4 Power Saving Mode Wake-up 4 A PA_12
SYS_XTAL Crystal Output Not Muxed SYS_XTAL
TM0_ACI0 TIMER0 Alternate Capture Input 0 C PC_03
TM0_ACI1 TIMER0 Alternate Capture Input 1 B PB_01
TM0_ACI2 TIMER0 Alternate Capture Input 2 C PC_07
TM0_ACI3 TIMER0 Alternate Capture Input 3 B PB_09
TM0_ACI4 TIMER0 Alternate Capture Input 4 C PC_01
TM0_ACI5 TIMER0 Alternate Capture Input 5 C PC_02
TM0_ACI6 TIMER0 Alternate Capture Input 6 A PA_12
TM0_ACLK0 TIMER0 Alternate Clock 0 C PC_04
Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 34 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
TM0_ACLK1 TIMER0 Alternate Clock 1 C PC_10
TM0_ACLK2 TIMER0 Alternate Clock 2 C PC_09
TM0_ACLK3 TIMER0 Alternate Clock 3 B PB_00
TM0_ACLK4 TIMER0 Alternate Clock 4 B PB_10
TM0_ACLK5 TIMER0 Alternate Clock 5 A PA_14
TM0_ACLK6 TIMER0 Alternate Clock 6 B PB_04
TM0_CLK TIMER0 Clock B PB_06
TM0_TMR0 TIMER0 Timer 0 A PA_05
TM0_TMR1 TIMER0 Timer 1 A PA_06
TM0_TMR2 TIMER0 Timer 2 A PA_07
TM0_TMR3 TIMER0 Timer 3 C PC_05
TM0_TMR4 TIMER0 Timer 4 A PA_09
TM0_TMR5 TIMER0 Timer 5 A PA_10
TM0_TMR6 TIMER0 Timer 6 A PA_11
TM0_TMR7 TIMER0 Timer 7 A PA_04
TRACE0_CLK TPIU0 Trace Clock B PB_10
TRACE0_D00 TPIU0 Trace Data 0 B PB_15
TRACE0_D01 TPIU0 Trace Data 1 B PB_14
TRACE0_D02 TPIU0 Trace Data 2 B PB_13
TRACE0_D03 TPIU0 Trace Data 3 B PB_12
TRACE0_D04 TPIU0 Trace Data 4 B PB_11
TRACE0_D05 TPIU0 Trace Data 5 A PA_02
TRACE0_D06 TPIU0 Trace Data 6 A PA_01
TRACE0_D07 TPIU0 Trace Data 7 A PA_00
TWI0_SCL TWI0 Serial Clock Not Muxed TWI0_SCL
TWI0_SDA TWI0 Serial Data Not Muxed TWI0_SDA
UART0_CTS UART0 Clear to Send C PC_03
UART0_RTS UART0 Request to Send C PC_02
UART0_RX UART0 Receive B PB_09
UART0_TX UART0 Transmit B PB_08
UART1_CTS UART1 Clear to Send B PB_14
UART1_RTS UART1 Request to Send B PB_13
UART1_RX UART1 Receive C PC_01
UART1_TX UART1 Transmit C PC_00
USB0_CLKIN USB0 Clock/Crystal Input Not Muxed USB0_CLKIN
USB0_DM USB0 Data – Not Muxed USB0_DM
USB0_DP USB0 Data + Not Muxed USB0_DP
USB0_ID USB0 OTG ID Not Muxed USB0_ID
USB0_VBC USB0 VBUS Control Not Muxed USB0_VBC
USB0_VBUS USB0 Bus Voltage Not Muxed USB0_VBUS
USB0_XTAL USB0 Crystal Not Muxed USB0_XTAL
VDD_EXT External VDD Not Muxed VDD_EXT
VDD_INT Internal VDD Not Muxed VDD_INT
VDD_OTP VDD for OTP Not Muxed VDD_OTP
VDD_RTC VDD for RTC Not Muxed VDD_RTC
VDD_USB VDD for USB Not Muxed VDD_USB
Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued)
Signal Name Description Port Pin Name
Rev. D | Page 35 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
GPIO MULTIPLEXING FOR 12 mm × 12 mm 88-LEAD LFCSP (QFN)
Table 12 through Table 14 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the
12 mm 12 mm 88-Lead LFCSP (QFN) package.
Table 12. Signal Multiplexing for Port A
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PA_00 SPI1_CLK TRACE0_D07 SMC0_ABE0
PA_01 SPI1_MISO TRACE0_D06 SMC0_ABE1
PA_02 SPI1_MOSI TRACE0_D05 SMC0_AMS1
PA_03 SPI1_SEL2 SPI1_RDY SMC0_ARDY
PA_04 SPI1_SEL1 TM0_TMR7 SPI2_RDY SMC0_A08 SPI1_SS
PA_05 TM0_TMR0 SPI0_SEL1 SMC0_A07 SPI0_SS
PA_06 TM0_TMR1 SPI0_SEL2 SPI0_RDY SMC0_A06
PA_07 TM0_TMR2 SPT1_BTDV SPT1_ATDV SMC0_A05 CNT0_DG
PA_08 PPI0_D11 MSI0_CD SPT1_ACLK SMC0_A01
PA_09 PPI0_D10 TM0_TMR4 SPT1_AFS SMC0_A02
PA_10 PPI0_D09 TM0_TMR5 SPT1_AD0 SMC0_A03
PA_11 PPI0_D08 TM0_TMR6 SPT1_AD1 SMC0_A04
PA_12 PPI0_FS1 CAN1_RX SPT0_AFS SMC0_AOE TM0_ACI6/SYS_WAKE4
PA_13 PPI0_FS2 CAN1_TX SPT0_ACLK SMC0_ARE CNT0_ZM
PA_14 PPI0_CLK SPI1_SEL4 SPT0_AD0 SMC0_AWE TM0_ACLK5
PA_15 PPI0_FS3 SPT0_ATDV SPT0_BTDV SMC0_AMS0 CNT0_UD
Table 13. Signal Multiplexing for Port B
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PB_00 PPI0_D07 SPT1_BCLK SPI0_CLK SMC0_D07 TM0_ACLK3
PB_01 PPI0_D06 SPT1_BFS SPI0_MISO SMC0_D06 TM0_ACI1
PB_02 PPI0_D05 SPT1_BD0 SPI0_MOSI SMC0_D05
PB_03 PPI0_D04 SPT1_BD1 SPI0_D2 SMC0_D04
PB_04 PPI0_D03 SPT0_BCLK SPI0_SEL4 SMC0_D03 TM0_ACLK6
PB_05 PPI0_D02 SPT0_BD0 SPI0_SEL5 SMC0_D02
PB_06 PPI0_D01 SPT0_BFS SPI0_SEL6 SMC0_D01 TM0_CLK
PB_07 PPI0_D00 SPT0_BD1 SPI0_D3 SMC0_D00 SYS_WAKE0
PB_08 UART0_TX PPI0_D16 SPI2_SEL2 SMC0_D08 SYS_WAKE1
PB_09 UART0_RX PPI0_D17 SPI2_SEL3 SMC0_D09 TM0_ACI3
PB_10 SPI2_CLK TRACE0_CLK SMC0_D10 TM0_ACLK4
PB_11 SPI2_MISO TRACE0_D04 SMC0_D11
PB_12 SPI2_MOSI TRACE0_D03 SMC0_D12 SYS_WAKE2
PB_13 SPI2_D2 UART1_RTS TRACE0_D02 SMC0_D13
PB_14 SPI2_D3 UART1_CTS TRACE0_D01 SMC0_D14
PB_15 SPI2_SEL1 TRACE0_D00 SMC0_D15 SPI2_SS
Rev. D | Page 36 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 14. Signal Multiplexing for Port C
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed Function
Input Tap
PC_00 UART1_TX SPT0_AD1 PPI0_D15
PC_01 UART1_RX SPT0_BD1 PPI0_D14 SMC0_A09 TM0_ACI4
PC_02 UART0_RTS CAN0_RX PPI0_D13 SMC0_A10 TM0_ACI5/SYS_WAKE3
PC_03 UART0_CTS CAN0_TX PPI0_D12 SMC0_A11 TM0_ACI0
PC_04 SPT0_BCLK SPI0_CLK MSI0_D1 SMC0_A12 TM0_ACLK0
PC_05 SPT0_AFS TM0_TMR3 MSI0_CMD
PC_06 SPT0_BD0 SPI0_MISO MSI0_D3
PC_07 SPT0_BFS SPI0_MOSI MSI0_D2 TM0_ACI2
PC_08 SPT0_AD0 SPI0_D2 MSI0_D0
PC_09 SPT0_ACLK SPI0_D3 MSI0_CLK TM0_ACLK2
PC_10 SPT1_BCLK MSI0_D4 SPI1_SEL3 TM0_ACLK1
Rev. D | Page 37 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF70x DESIGNER QUICK REFERENCE
Table 15 provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• Signal Name: The Signal Name column in the table
includes the signal name for every pin and (where applica-
ble) the GPIO multiplexed pin function for every pin.
• Pin Type: The Type column in the table identifies the I/O
type or supply type of the pin. The abbreviations used in
this column are na (none), I/O (input/output), a (analog), s
(supply), and g (ground).
• Driver Type: The Driver Type column in the table identi-
fies the driver type used by the pin. The driver types are
defined in the output drive currents section of this data
sheet.
• Internal Termination: The Int Term column in the table
specifies the termination present when the processor is not
in the reset or hibernate state. The abbreviations used in
this column are wk (weak keeper, weakly retains previous
value driven on the pin), pu (pull-up), or pd (pull-down).
• Reset Termination: The Reset Term column in the table
specifies the termination present when the processor is in
the reset state. The abbreviations used in this column are
wk (weak keeper, weakly retains previous value driven on
the pin), pu (pull-up), or pd (pull-down).
• Reset Drive: The Reset Drive column in the table specifies
the active drive on the signal when the processor is in the
reset state.
• Hibernate Termination: The Hiber Term column in the
table specifies the termination present when the processor
is in the hibernate state. The abbreviations used in this col-
umn are wk (weak keeper, weakly retains previous value
driven on the pin), pu (pull-up), or pd (pull-down).
• Hibernate Drive: The Hiber Drive column in the table
specifies the active drive on the signal when the processor is
in the hibernate state.
• Power Domain: The Power Domain column in the table
specifies the power supply domain in which the signal
resides.
• Description and Notes: The Description and Notes column
in the table identifies any special requirements or charac-
teristics for the signal. If no special requirements are listed
the signal may be left unconnected if it is not used. Also, for
multiplexed general-purpose I/O pins, this column identi-
fies the functions available on the pin.
If an external pull-up or pull-down resistor is required for any
signal, 100 kΩ is the maximum value that can be used unless
otherwise noted.
Note that for Port A, Port B, and Port C (PA_00 to PC_14),
when SYS_HWRST is low, these pads are three-state. After
SYS_HWRST is released, but before code execution begins,
these pins are internally pulled up. Subsequently, the state
depends on the input enable and output enable which are
controlled by software.
Software control of internal pull-ups works according to the
following settings in the PADS_PCFG0 register. When
PADS_PCFG0 = 0: For PA_15:PA_00, PB_15:PB_00, and
PC_14:PC_00, the internal pull-up is enabled when both the
input enable and output enable of a particular pin are
deasserted. When PADS_PCFG0 = 1: For PA_15:PA_00,
PB_15:PB_00, and PC_14:PC_00, the internal pull-up is
enabled as long as the output enable of a particular pin is
deasserted.
There are some exceptions to this scheme:
• Internal pull-ups are always disabled if MSI mode is
selected for that signal.
• The following signals enabled the internal pull-down when
the output enable is de-asserted: SMC0_AMS[1:0],
SMC0_ARE, SMC0_AWE, SMC0_AOE, SMC0_ARDY,
SPI0_SEL[6:1], SPI1_SEL[4:1], and SPI2_SEL[3:1].
Table 15. ADSP-BF70x Designer Quick Reference
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
DMC0_A00 I/O B none none none none none VDD_DMC Desc: DMC0 Address 0
Notes: No notes.
DMC0_A01 I/O B none none none none none VDD_DMC Desc: DMC0 Address 1
Notes: No notes.
DMC0_A02 I/O B none none none none none VDD_DMC Desc: DMC0 Address 2
Notes: No notes.
DMC0_A03 I/O B none none none none none VDD_DMC Desc: DMC0 Address 3
Notes: No notes.
DMC0_A04 I/O B none none none none none VDD_DMC Desc: DMC0 Address 4
Notes: No notes.
DMC0_A05 I/O B none none none none none VDD_DMC Desc: DMC0 Address 5
Notes: No notes.
Rev. D | Page 38 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
DMC0_A06 I/O B none none none none none VDD_DMC Desc: DMC0 Address 6
Notes: No notes.
DMC0_A07 I/O B none none none none none VDD_DMC Desc: DMC0 Address 7
Notes: No notes.
DMC0_A08 I/O B none none none none none VDD_DMC Desc: DMC0 Address 8
Notes: No notes.
DMC0_A09 I/O B none none none none none VDD_DMC Desc: DMC0 Address 9
Notes: No notes.
DMC0_A10 I/O B none none none none none VDD_DMC Desc: DMC0 Address 10
Notes: No notes.
DMC0_A11 I/O B none none none none none VDD_DMC Desc: DMC0 Address 11
Notes: No notes.
DMC0_A12 I/O B none none none none none VDD_DMC Desc: DMC0 Address 12
Notes: No notes.
DMC0_A13 I/O B none none none none none VDD_DMC Desc: DMC0 Address 13
Notes: No notes.
DMC0_BA0 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 0
Notes: No notes.
DMC0_BA1 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 1
Notes: No notes.
DMC0_BA2 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 2
Notes: For LPDDR, leave unconnected.
DMC0_CAS I/O B none none none none none VDD_DMC Desc: DMC0 Column Address Strobe
Notes: No notes.
DMC0_CK I/O C none none L none L VDD_DMC Desc: DMC0 Clock
Notes: No notes.
DMC0_CK I/O C none none L none L VDD_DMC Desc: DMC0 Clock (complement)
Notes: No notes.
DMC0_CKE I/O B none none L none L VDD_DMC Desc: DMC0 Clock enable
Notes: No notes.
DMC0_CS0 I/O B none none none none none VDD_DMC Desc: DMC0 Chip Select 0
Notes: No notes.
DMC0_DQ00 I/O B none none none none none VDD_DMC Desc: DMC0 Data 0
Notes: No notes.
DMC0_DQ01 I/O B none none none none none VDD_DMC Desc: DMC0 Data 1
Notes: No notes.
DMC0_DQ02 I/O B none none none none none VDD_DMC Desc: DMC0 Data 2
Notes: No notes.
DMC0_DQ03 I/O B none none none none none VDD_DMC Desc: DMC0 Data 3
Notes: No notes.
DMC0_DQ04 I/O B none none none none none VDD_DMC Desc: DMC0 Data 4
Notes: No notes.
DMC0_DQ05 I/O B none none none none none VDD_DMC Desc: DMC0 Data 5
Notes: No notes.
DMC0_DQ06 I/O B none none none none none VDD_DMC Desc: DMC0 Data 6
Notes: No notes.
DMC0_DQ07 I/O B none none none none none VDD_DMC Desc: DMC0 Data 7
Notes: No notes.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 39 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
DMC0_DQ08 I/O B none none none none none VDD_DMC Desc: DMC0 Data 8
Notes: No notes.
DMC0_DQ09 I/O B none none none none none VDD_DMC Desc: DMC0 Data 9
Notes: No notes.
DMC0_DQ10 I/O B none none none none none VDD_DMC Desc: DMC0 Data 10
Notes: No notes.
DMC0_DQ11 I/O B none none none none none VDD_DMC Desc: DMC0 Data 11
Notes: No notes.
DMC0_DQ12 I/O B none none none none none VDD_DMC Desc: DMC0 Data 12
Notes: No notes.
DMC0_DQ13 I/O B none none none none none VDD_DMC Desc: DMC0 Data 13
Notes: No notes.
DMC0_DQ14 I/O B none none none none none VDD_DMC Desc: DMC0 Data 14
Notes: No notes.
DMC0_DQ15 I/O B none none none none none VDD_DMC Desc: DMC0 Data 15
Notes: No notes.
DMC0_LDM I/O B none none none none none VDD_DMC Desc: DMC0 Data Mask for Lower Byte
Notes: No notes.
DMC0_LDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
Notes: For LPDDR, a pull-down is
required.
DMC0_LDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
(complement)
Notes: For single ended DDR2, connect
to DMC0_VREF. For LPDDR, leave
unconnected.
DMC0_ODT I/O B none none none none none VDD_DMC Desc: DMC0 On-die termination
Notes: For LPDDR, leave unconnected.
DMC0_RAS I/O B none none none none none VDD_DMC Desc: DMC0 Row Address Strobe
Notes: No notes.
DMC0_UDM I/O B none none none none none VDD_DMC Desc: DMC0 Data Mask for Upper Byte
Notes: No notes.
DMC0_UDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
Notes: For LPDDR, a pull-down is
required.
DMC0_UDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
(complement)
Notes: For single ended DDR2, connect
to DMC0_VREF. For LPDDR, leave
unconnected.
DMC0_VREF a na none none none none none VDD_DMC Desc: DMC0 Voltage Reference
Notes: For LPDDR, leave unconnected.
If the DMC is not used, connect to
ground.
DMC0_WE I/O B none none none none none VDD_DMC Desc: DMC0 Write Enable
Notes: No notes.
GND g na none none none none none na Desc: Ground
Notes: No notes.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 40 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
GND_HADC g na none none none none none na Desc: Ground HADC
Notes: If HADC is not used, connect to
ground.
HADC0_VIN0 a na none none none none none VDD_HADC Desc: HADC0 Analog Input at channel 0
Notes: If HADC is not used, connect to
ground.
HADC0_VIN1 a na none none none none none VDD_HADC Desc: HADC0 Analog Input at channel 1
Notes: If HADC is not used, connect to
ground.
HADC0_VIN2 a na none none none none none VDD_HADC Desc: HADC0 Analog Input at channel 2
Notes: If HADC is not used, connect to
ground.
HADC0_VIN3 a na none none none none none VDD_HADC Desc: HADC0 Analog Input at channel 3
Notes: If HADC is not used, connect to
ground.
HADC0_VREFN a na none none none none none VDD_HADC Desc: HADC0 Ground Reference for
ADC
Notes: If HADC is not used, connect to
ground.
HADC0_VREFP a na none none none none none VDD_HADC Desc: HADC0 External Reference for
ADC
Notes: If HADC is not used, connect to
ground.
JTG_TCK_
SWCLK
I/O na pd none none none none VDD_EXT Desc: JTAG Clock | Serial Wire Clock
Notes: Functional during reset.
JTG_TDI I/O na pu none none none none VDD_EXT Desc: JTAG Serial Data In
Notes: Functional during reset.
JTG_TDO_SWO I/O A none none none none none VDD_EXT Desc: JTAG Serial Data Out | Serial Wire
Out
Notes: Functional during reset, three-
state when JTG_TRST is asserted.
JTG_TMS_
SWDIO
I/O A pu none none none none VDD_EXT Desc: JTAG Mode Select | Serial Wire DIO
Notes: Functional during reset.
JTG_TRST I/O na pd none none none none VDD_EXT Desc: JTAG Reset
Notes: Functional during reset, a 10k
external pull-down may be used to
shorten the t
VDDEXT_RST
timing
requirement.
PA_00 I/O A none none none none none VDD_EXT Desc: SPI1 Clock | TRACE0 Trace Data 7 |
SMC0 Byte Enable 0
Notes: SPI clock requires a pull-down
when controlling most SPI flash
devices.
PA_01 I/O A none none none none none VDD_EXT Desc: SPI1 Master In, Slave Out | TRACE0
Trace Data 6 | SMC0 Byte Enable 1
Notes: Pull-up required for SPI_MISO if
SPI master boot is used.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 41 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PA_02 I/O A none none none none none VDD_EXT Desc: SPI1 Master Out, Slave In | TRACE0
Trace Data 5 | SMC0 Memory Select 1
Notes: May require a pull-up if used as
an SMC memory select. Check the data
sheet requirements of the IC it connects
to.
PA_03 I/O A none none none none none VDD_EXT Desc: SPI1 Slave Select Output 2 | SPI1
Ready | SMC0 Asynchronous Ready
Notes: May require a pull-up or pull-
down if used as an SMC asynchronous
ready. Check the data sheet require-
ments of the IC it connects to and the
programmed polarity.
PA_04 I/O A none none none none none VDD_EXT Desc: SPI1 Slave Select Output 1 | TM0
Timer 7 | SPI2 Ready | SMC0 Address 8 |
SPI1 Slave Select Input
Notes: SPI slave select outputs require a
pull-up when used.
PA_05 I/O A none none none none none VDD_EXT Desc: TM0 Timer 0 | SPI0 Slave Select
Output 1 | SMC0 Address 7 | SPI0 Slave
Select Input
Notes: SPI slave select outputs require a
pull-up when used.
PA_06 I/O A none none none none none VDD_EXT Desc: TM0 Timer 1 | SPI0 Slave Select
Output 2 | SPI0 Ready | SMC0 Address 6
Notes: SPI slave select outputs require a
pull-up when used.
PA_07 I/O A none none none none none VDD_EXT Desc: TM0 Timer 2 | SPT1 Channel B
Transmit Data Valid | SPT1 Channel A
Transmit Data Valid | SMC0 Address 5 |
CNT0 Count Down and Gate
Notes: No notes.
PA_08 I/O A none none none none none VDD_EXT Desc: PPI0 Data 11 | MSI0 Card Detect |
SPT1 Channel A Clock | SMC0 Address 1
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PA_09 I/O A none none none none none VDD_EXT Desc: PPI0 Data 10 | TM0 Timer 4 | SPT1
Channel A Frame Sync | SMC0 Address 2
Notes: No notes.
PA_10 I/O A none none none none none VDD_EXT Desc: PPI0 Data 9 | TM0 Timer 5 | SPT1
Channel A Data 0 | SMC0 Address 3
Notes: No notes.
PA_11 I/O A none none none none none VDD_EXT Desc: PPI0 Data 8 | TM0 Timer 6 | SPT1
Channel A Data 1 | SMC0 Address 4
Notes: No notes.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 42 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PA_12 I/O A none none none none none VDD_EXT Desc: PPI0 Frame Sync 1 (HSYNC) | CAN1
Receive | SPORT0 Channel A Frame Sync
|SMC0 Output Enable |SYS Power
Saving Mode Wakeup 4 | TM0 Alternate
Capture Input 6
Notes: If hibernate mode is used one of
the following must be true during
hibernate. Either this pin must be
actively driven by another IC, or it must
have a pull-up or pull-down.
PA_13 I/O A none none none none none VDD_EXT Desc: PPI0 Frame Sync 2 (VSYNC) | CAN1
Transmit | SPORT0 Channel A Clock |
SMC0 Read Enable | CNT0 Count Zero
Marker
Notes: No notes.
PA_14 I/O A none none none none none VDD_EXT Desc: PPI0 Clock | SPI1 Slave Select
Output 4 | SPORT0 Channel A Data 0 |
SMC0 Write Enable | TM0 Alternate
Clock 5
Notes: SPI slave select outputs require a
pull-up when used.
PA_15 I/O A none none none none none VDD_EXT Desc: PPI0 Frame Sync 3 (FIELD) | SPT0
Channel A Transmit Data Valid | SPT0
Channel B Transmit Data Valid | SMC0
Memory Select 0 | CNT0 Count Up and
Direction
Notes: May require a pull-up if used as
an SMC memory select. Check the data
sheet requirements of the IC it connects
to.
PB_00 I/O A none none none none none VDD_EXT Desc: PPI0 Data 7 | SPT1 Channel B Clock
| SPI0 Clock | SMC0 Data 7 | TM0
Alternate Clock 3
Notes: SPI clock requires a pull-down
when controlling most SPI flash
devices.
PB_01 I/O A none none none none none VDD_EXT Desc: PPI0 Data 6 | SPT1 Channel B
Frame Sync | SPI0 Master In, Slave Out |
SMC0 Data 6 | TM0 Alternate Capture
Input 1
Notes: Pull-up required for SPI_MISO if
SPI master boot is used.
PB_02 I/O A none none none none none VDD_EXT Desc: PPI0 Data 5 | SPT1 Channel B Data
0 | SPI0 Master Out, Slave In | SMC0 Data
5
Notes: No notes.
PB_03 I/O A none none none none none VDD_EXT Desc: PPI0 Data 4 | SPT1 Channel B Data
1 | SPI0 Data 2 | SMC0 Data 4
Notes: No notes.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 43 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PB_04 I/O A none none none none none VDD_EXT Desc: PPI0 Data 3 | SPT0 Channel B Clock
| SPI0 Slave Select Output 4 | SMC0 Data
3 | TM0 Alternate Clock 6
Notes: SPI slave select outputs require a
pull-up when used.
PB_05 I/O A none none none none none VDD_EXT Desc: PPI0 Data 2 | SPT0 Channel B Data
0 | SPI0 Slave Select Output 5 | SMC0
Data 2
Notes: SPI slave select outputs require a
pull-up when used.
PB_06 I/O A none none none none none VDD_EXT Desc: PPI0 Data 1 | SPT0 Channel B
Frame Sync | SPI0 Slave Select Output 6
| SMC0 Data 1 | TM0 Clock
Notes: SPI slave select outputs require a
pull-up when used.
PB_07 I/O A none none none none none VDD_EXT Desc: PPI0 Data 0 | SPT0 Channel B Data
1 | SPI0 Data 3 | SMC0 Data 0 | SYS Power
Saving Mode Wakeup 0
Notes: If hibernate mode is used, one of
the following must be true during
hibernate. Either this pin must be
actively driven by another IC, or it must
have a pull-up or pull-down.
PB_08 I/O A none none none none none VDD_EXT Desc: UART0 Transmit | PPI0 Data 16 |
SPI2 Slave Select Output 2 | SMC0 Data
8 | SYS Power Saving Mode Wakeup 1
Notes: SPI slave select outputs require a
pull-up when used. If hibernate mode is
used, one of the following must be true
during hibernate. Either this pin must
be actively driven by another IC, or it
must have a pull-up or pull-down.
PB_09 I/O A none none none none none VDD_EXT Desc: UART0 Receive | PPI0 Data 17 |
SPI2 Slave Select Output 3 | SMC0 Data
9 | TM0 Alternate Capture Input 3
Notes: SPI slave select outputs require a
pull-up when used.
PB_10 I/O A none none none none none VDD_EXT Desc: SPI2 Clock | TRACE0 Trace Clock |
SMC0 Data 10 | TM0 Alternate Clock 4
Notes: SPI clock requires a pull-down
when controlling most SPI flash
devices.
PB_11 I/O A none none none none none VDD_EXT Desc: SPI2 Master In, Slave Out | TRACE0
Trace Data 4 | SMC0 Data 11
Notes: Pull-up required for SPI_MISO if
SPI master boot is used.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 44 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PB_12 I/O A none none none none none VDD_EXT Desc: SPI2 Master Out, Slave In | TRACE0
Trace Data 3 | SMC0 Data 12 | SYS Power
Saving Mode Wakeup 2
Notes: If hibernate mode is used, one of
the following must be true during
hibernate. Either this pin must be
actively driven by another IC, or it must
have a pull-up or pull-down.
PB_13 I/O A none none none none none VDD_EXT Desc: SPI2 Data 2 | UART1 Request to
Send | TRACE0 Trace Data 2 | SMC0 Data
13
Notes: No notes.
PB_14 I/O A none none none none none VDD_EXT Desc: SPI2 Data 3 | UART1 Clear to Send
| TRACE0 Trace Data 1 | SMC0 Data 14
Notes: No notes.
PB_15 I/O A none none none none none VDD_EXT Desc: SPI2 Slave Select Output 1 |
TRACE0 Trace Data 0 | SMC0 Data 15 |
SPI2 Slave Select Input
Notes: SPI slave select outputs require a
pull-up when used.
PC_00 I/O A none none none none none VDD_EXT Desc: UART1 Transmit | SPT0 Channel A
Data 1 | PPI0 Data 15
Notes: No notes.
PC_01 I/O A none none none none none VDD_EXT Desc: UART1 Receive | SPT0 Channel B
Data 1 | PPI0 Data 14 | SMC0 Address 9 |
TM0 Alternate Capture Input 4
Notes: No notes.
PC_02 I/O A none none none none none VDD_EXT Desc: UART0 Request to Send | CAN0
Receive | PPI0 Data 13 | SMC0 Address
10 | SYS Power Saving Mode Wakeup 3 |
TM0 Alternate Capture Input 5
Notes: If hibernate mode is used, one of
the following must be true during
hibernate. Either this pin must be
actively driven by another IC, or it must
have a pull-up or pull-down.
PC_03 I/O A none none none none none VDD_EXT Desc: UART0 Clear to Send | CAN0
Transmit | PPI0 Data 12 | SMC0 Address
11 | TM0 Alternate Capture Input 0
Notes: No notes.
PC_04 I/O A none none none none none VDD_EXT Desc: SPT0 Channel B Clock | SPI0 Clock
| MSI0 Data 1 | SMC0 Address 12 | TM0
Alternate Clock 0
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 45 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PC_05 I/O A none none none none none VDD_EXT Desc: SPT0 Channel A Frame Sync | TM0
Timer 3 | MSI0 Command
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PC_06 I/O A none none none none none VDD_EXT Desc: SPT0 Channel B Data 0 | SPI0
Master In, Slave Out | MSI0 Data 3
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PC_07 I/O A none none none none none VDD_EXT Desc: SPT0 Channel B Frame Sync | SPI0
Master Out, Slave In | MSI0 Data 2 | TM0
Alternate Capture Input 2
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PC_08 I/O A none none none none none VDD_EXT Desc: SPT0 Channel A Data 0 | SPI0 Data
2 | MSI0 Data 0
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PC_09 I/O A none none none none none VDD_EXT Desc: SPT0 Channel A Clock | SPI0 Data
3 | MSI0 Clock | TM0 Alternate Clock 2
Notes: No notes.
PC_10 I/O A none none none none none VDD_EXT Desc: SPT1 Channel B Clock | MSI0 Data
4 | SPI1 Slave Select Output 3 | TM0
Alternate Clock 1
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details. SPI slave select outputs require
a pull-up when used.
PC_11 I/O A none none none none none VDD_EXT Desc: SPT1 Channel B Frame Sync | MSI0
Data 5 | SPI0 Slave Select Output 3
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details. SPI slave select outputs require
a pull-up when used.
PC_12 I/O A none none none none none VDD_EXT Desc: SPT1 Channel B Data 0 | MSI0 Data
6
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 46 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
PC_13 I/O A none none none none none VDD_EXT Desc: SPT1 Channel B Data 1 | MSI0 Data
7
Notes: An external pull-up may be
required for MSI modes, see the MSI
chapter in the hardware reference for
details.
PC_14 I/O A none none none none none VDD_EXT Desc: SPT1 Channel B Transmit Data
Valid | MSI0 eSDIO Interrupt Input
Notes: No notes.
RTC0_CLKIN a na none none none none none VDD_RTC Desc: RTC0 Crystal input / external oscil-
lator connection
Notes: If RTC is not used, connect to
ground.
RTC0_XTAL a na none none none none none VDD_RTC Desc: RTC0 Crystal output
Notes: No notes.
SYS_BMODE0 I/O na none none none none none VDD_EXT Desc: SYS Boot Mode Control 0
Notes: A pull-down is required for
setting to 0 and a pull-up is required for
setting to 1.
SYS_BMODE1 I/O na none none none none none VDD_EXT Desc: SYS Boot Mode Control 1
Notes: A pull-down is required for
setting to 0 and a pull-up is required for
setting to 1.
SYS_CLKIN a na none none none none none VDD_EXT Desc: SYS Clock/Crystal Input
Notes: No notes.
SYS_CLKOUT I/O A none none L none none VDD_EXT Desc: SYS Processor Clock Output
Notes: During reset, SYS_CLKOUT
drives out SYS_CLKIN Frequency.
SYS_EXTWAKE I/O A none none H none L VDD_EXT Desc: SYS External Wake Control
Notes: Drives low during hibernate and
high all other times including reset.
SYS_FAULT I/O A none none none none none VDD_EXT Desc: SYS Complementary Fault Output
Notes: Open drain, requires an external
pull-up resistor.
SYS_HWRST I/O na none none none none none VDD_EXT Desc: SYS Processor Hardware Reset
Control
Notes: Active during reset, must be
externally driven.
SYS_NMI I/O na none none none none none VDD_EXT Desc: SYS Non-maskable Interrupt
Notes: Requires an external pull-up
resistor.
SYS_RESOUT I/O A none none L none none VDD_EXT Desc: SYS Reset Output
Notes: Active during reset.
SYS_XTAL a na none none none none none VDD_EXT Desc: SYS Crystal Output
Notes: Leave unconnected if an oscil-
lator is used to provide SYS_CLKIN.
Active during reset. State during
hibernate is controlled by DPM_HIB_
DIS.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 47 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
TWI0_SCL I/O D none none none none none VDD_EXT Desc: TWI0 Serial Clock
Notes: Open drain, requires external
pull up. Consult version 2.1 of the I2C
specification for the proper resistor
value. If TWI is not used, connect to
ground.
TWI0_SDA I/O D none none none none none VDD_EXT Desc: TWI0 Serial Data
Notes: Open drain, requires external
pull up. Consult version 2.1 of the I2C
specification for the proper resistor
value. If TWI is not used, connect to
ground.
USB0_CLKIN a na none none none none none VDD_USB Desc: USB0 Clock/Crystal Input
Notes: If USB is not used, connect to
ground. Active during reset
USB0_DM I/O F none none none none none VDD_USB Desc: USB0 Data –
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the HRM.
USB0_DP I/O F none none none none none VDD_USB Desc: USB0 Data +
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the HRM.
USB0_ID I/O na none none none none none VDD_USB Desc: USB0 OTG ID
Notes: If USB is not used connect to
ground. When USB is being used, the
internal pull-up that is present during
hibernate is programmable. See the
USB chapter in the HRM. Active during
reset.
USB0_VBC I/O E none none none none none VDD_USB Desc: USB0 VBUS Control
Notes: If USB is not, used pull low.
USB0_VBUS I/O G none none none none none VDD_USB Desc: USB0 Bus Voltage
Notes: If USB is not used, connect to
ground.
USB0_XTAL a na none none none none none VDD_USB Desc: USB0 Crystal
Notes: No notes.
VDD_DMC s na none none none none none na Desc: VDD for DMC
Notes: If the DMC is not used, connect
to VDD_INT.
VDD_EXT s na none none none none none na Desc: External VDD
Notes: Must be powered.
VDD_HADC s na none none none none none na Desc: VDD for HADC
Notes: If HADC is not used, connect to
ground.
VDD_INT s na none none none none none na Desc: Internal VDD
Notes: Must be powered.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 48 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
VDD_OTP s na none none none none none na Desc: VDD for OTP
Notes: Must be powered.
VDD_RTC s na none none none none none na Desc: VDD for RTC
Notes: If RTC is not used, connect to
ground.
VDD_USB s na none none none none none na Desc: VDD for USB
Notes: If USB is not used, connect to
VDD_EXT.
Table 15. ADSP-BF70x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Rev. D | Page 49 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SPECIFICATIONS
For information about product specifications, contact your Analog Devices, Inc. representative.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit
V
DD_INT
Internal Supply Voltage CCLK ≤ 400 MHz 1.045 1.100 1.155 V
V
DD_EXT1
1
Must remain powered (even if the associated function is not used).
External Supply Voltage 1.7 1.8 1.9 V
V
DD_EXT1
External Supply Voltage 3.13 3.30 3.47 V
V
DD_DMC
DDR2/LPDDR Supply Voltage 1.7 1.8 1.9 V
V
DD_USB2
2
If not used, connect to 1.8 V or 3.3 V.
USB Supply Voltage 3.13 3.30 3.47 V
V
DD_RTC
Real-Time Clock Supply Voltage 2.00 3.30 3.47 V
V
DD_HADC
HADC Supply Voltage 3.13 3.30 3.47 V
V
DD_OTP1
OTP Supply Voltage
For Reads 2.25 3.30 3.47 V
For Writes 3.13 3.30 3.47 V
V
DDR_VREF
DDR2 Reference Voltage
Applies to the DMC0_VREF pin.
0.49 × V
DD_DMC
0.50 × V
DD_DMC
0.51 × V
DD_DMC
V
V
HADC_REF3
3
V
HADC_VREF
must always be less than V
DD_HADC
.
HADC Reference Voltage 2.5 3.30 V
DD_HADC
V
V
HADC0_VINx
HADC Input Voltage 0 V
HADC_REF
+ 0.2 V
V
IH4
4
Parameter value applies to all input and bidirectional signals except RTC signals, TWI signals, DMC0 signals, and USB0 signals.
High Level Input Voltage V
DD_EXT
= 3.47 V 2.0 V
V
IH4
High Level Input Voltage V
DD_EXT
= 1.9 V 0.7 × V
DD_EXT
V
V
IHTWI5,
6
5
Parameter applies to TWI signals.
6
TWI signals are pulled up to V
BUSTWI
. See Table 16.
High Level Input Voltage V
DD_EXT
= maximum 0.7 × V
BUSTWI
V
BUSTWI
V
V
IH_DDR27
7
Parameter applies to DMC0 signals in DDR2 mode.
High Level Input Voltage V
DD_DMC
= 1.9 V V
DDR_VREF
+ 0.25 V
V
IH_LPDDR8
8
Parameter applies to DMC0 signals in LPDDR mode.
High Level Input Voltage V
DD_DMC
= 1.9 V 0.8 × V
DD_DMC
V
V
ID_DDR29
9
Parameter applies to signals DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.
Differential Input Voltage V
IX
= 1.075 V 0.50 V
V
ID_DDR29
Differential Input Voltage V
IX
= 0.725 V 0.55 V
V
IL4
Low Level Input Voltage V
DD_EXT
= 3.13 V 0.8 V
V
IL4
Low Level Input Voltage V
DD_EXT
= 1.7 V 0.3 × V
DD_EXT
V
V
ILTWI5,
6
Low Level Input Voltage V
DD_EXT
= minimum 0.3 × V
BUSTWI
V
V
IL_DDR27
Low Level Input Voltage V
DD_DMC
= 1.7 V V
DDR_VREF
– 0.25 V
V
IL_LPDDR8
Low Level Input Voltage V
DD_DMC
= 1.7 V 0.2 × V
DD_DMC
V
T
J
Junction Temperature T
AMBIENT
= 0°C to +70°C 0 105 °C
T
J
Junction Temperature T
AMBIENT
= –40°C to +85°C –40 +105 °C
AUTOMOTIVE USE ONLY
T
J
Junction Temperature
(Automotive Grade)
T
AMBIENT
= –40°C to +105°C –40 +125
10
10
Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.
°C
Rev. D | Page 50 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Clock Related Operating Conditions
Table 17 and Table 18 describe the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables
applies to all speed grades (found in the Ordering Guide) except where expressly noted. Figure 6 provides a graphical representation of the
various clocks and their available divider values.
Table 16. TWI0VSEL
1
Settings and V
DD_EXT
/V
BUSTWI
TWI0VSEL V
DD_EXT
Nominal V
BUSTWI
Min V
BUSTWI
Nominal V
BUSTWI
Max Unit
TWI000
2
3.30 3.13 3.30 3.47 V
TWI001 1.80 1.70 1.80 1.90 V
TWI011 1.80 3.13 3.30 3.47 V
TWI100 3.30 4.75 5.00 5.25 V
1
TWI0VSEL is the TWI voltage select field in the PADS_PCFG0 register. See the hardware reference manual.
2
Designs must comply with the V
DD_EXT
and V
BUSTWI
voltages specified for the default TWI0VSEL setting for correct JTAG boundary scan operation during reset.
Table 17. Core and System Clock Operating Conditions
Parameter Ratio Restriction PLLCLK Restriction Min Max Unit
f
CCLK
Core Clock Frequency f
CCLK
≥ f
SYSCLK
PLLCLK = 800 400 MHz
f
CCLK
Core Clock Frequency f
CCLK
≥ f
SYSCLK
600 ≤ PLLCLK < 800 390 MHz
f
CCLK
Core Clock Frequency f
CCLK
≥ f
SYSCLK
380 ≤ PLLCLK < 600 380 MHz
f
CCLK
Core Clock Frequency f
CCLK
≥ f
SYSCLK
230.2 ≤ PLLCLK < 380 PLLCLK MHz
f
SYSCLK
SYSCLK Frequency
1
1
The minimum frequency for SYSCLK and SCLK0 applies only when the USB is used.
PLLCLK = 800 60 200 MHz
f
SYSCLK
SYSCLK Frequency
1
600 ≤ PLLCLK < 800 60 195 MHz
f
SYSCLK
SYSCLK Frequency
1
380 ≤ PLLCLK < 600 60 190 MHz
f
SYSCLK
SYSCLK Frequency
1
230.2 ≤ PLLCLK < 380 60 PLLCLK ÷ 2 MHz
f
SCLK0
SCLK0 Frequency
1
f
SYSCLK
≥ f
SCLK0
30 100 MHz
f
SCLK1
SCLK1 Frequency f
SYSCLK
≥ f
SCLK1
200 MHz
f
DCLK
DDR2 Clock Frequency f
SYSCLK
≥ f
DCLK
125 200 MHz
f
DCLK
LPDDR Clock Frequency f
SYSCLK
≥ f
DCLK
10 200 MHz
Rev. D | Page 51 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 18. Peripheral Clock Operating Conditions
Parameter Restriction Min Typ Max Unit
f
OCLK
Output Clock Frequency 50 MHz
f
SYS_CLKOUTJ
SYS_CLKOUT Period Jitter
1,
2
±2 %
f
PCLKPROG
Programmed PPI Clock When Transmitting Data and Frame Sync 50 MHz
f
PCLKPROG
Programmed PPI Clock When Receiving Data or Frame Sync 50 MHz
f
PCLKEXT
External PPI Clock When Receiving Data and Frame Sync
3,
4
f
PCLKEXT
≤ f
SCLK0
50 MHz
f
PCLKEXT
External PPI Clock Transmitting Data or Frame Sync
3,
4
f
PCLKEXT
≤ f
SCLK0
50 MHz
f
SPTCLKPROG
Programmed SPT Clock When Transmitting Data and Frame Sync 50 MHz
f
SPTCLKPROG
Programmed SPT Clock When Receiving Data or Frame Sync 50 MHz
f
SPTCLKEXT
External SPT Clock When Receiving Data and Frame Sync
3,
4
f
SPTCLKEXT
≤ f
SCLK0
50 MHz
f
SPTCLKEXT
External SPT Clock Transmitting Data or Frame Sync
3,
4
f
SPTCLKEXT
≤ f
SCLK0
50 MHz
f
SPICLKPROG
Programmed SPI Clock When Transmitting Data 50 MHz
f
SPICLKPROG
Programmed SPI Clock When Receiving Data 50 MHz
f
SPICLKEXT
External SPI Clock When Receiving Data
3,
4
f
SPICLKEXT
≤ f
SCLK0
50 MHz
f
SPICLKEXT
External SPI Clock When Transmitting Data
3,
4
f
SPICLKEXT
≤ f
SCLK0
50 MHz
f
MSICLKPROG
Programmed MSI Clock 50 MHz
1
SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due
to the dependency on these factors the measured jitter may be higher or lower than this typical specification for each end application.
2
The value in the Typ field is the percentage of the SYS_CLKOUT period.
3
The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications
section for that peripheral. Pay particular attention to setup and hold times for VDD_EXT = 1.8 V which may preclude the maximum frequency listed here.
4
The peripheral external clock frequency must also be less than or equal to the f
SCLK
that clocks the peripheral.
Figure 6. Clock Relationships and Divider Values
Table 19. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
PLLCLK
PLL Clock Frequency 230.2 800 MHz
CGU_CTL.MSEL
1
PLL Multiplier 8 41
1
The CGU_CTL.MSEL setting must also be chosen to ensure that the f
PLLCLK
specification is not violated.
SYS_CLKIN PLL
DCLK
SYSCLK
CCLK
SCLK1
(MDMA1, MDMA2, CRYPTOGRAPHIC ACCELERATORS)
SCLK0
(ALL OTHER PERIPHERALS)
CSEL
(1
-
32)
SYSSEL
(1
-
32)
S0SEL
(1
-
8)
S1SEL
(1
-
8)
DSEL
(1
-
32)
OCLK
OSEL
(1
-
128)
PLLCLK
Rev. D | Page 52 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ELECTRICAL CHARACTERISTICS
Parameter Conditions Min Typ Max Unit
V
OH1
High Level Output Voltage V
DD_EXT
= 1. 7 V, I
OH
= –1.0 mA 0.8 × V
DD_EXT
V
V
OH1
High Level Output Voltage V
DD_EXT
= 3 .1 3 V , I
OH
= –2.0 mA 0.9 × V
DD_EXT
V
V
OH_DDR22
High Level Output Voltage, DDR2,
Programmed Impedance = 34 Ω
V
DD_DMC
= 1.70 V, I
OH
= –7.1 mA V
DD_DMC
– 0.320 V
V
OH_DDR22
High Level Output Voltage, DDR2,
Programmed Impedance = 40 Ω
V
DD_DMC
= 1.70 V, I
OH
= –5.8 mA V
DD_DMC
– 0.320 V
V
OH_DDR22
High Level Output Voltage, DDR2,
Programmed Impedance = 50 Ω
V
DD_DMC
= 1.70 V, I
OH
= –4.1 mA V
DD_DMC
– 0.320 V
V
OH_DDR22
High Level Output Voltage, DDR2,
Programmed Impedance = 60 Ω
V
DD_DMC
= 1.70 V, I
OH
= –3.4 mA V
DD_DMC
– 0.320 V
V
OH_LPDDR2
High Level Output Voltage, LPDDR V
DD_DMC
= 1.70 V, I
OH
= –2.0 mA V
DD_DMC
– 0.320 V
V
OL3
Low Level Output Voltage V
DD_EXT
= 1. 7 V, I
OL
= 1.0 mA 0.400 V
V
OL3
Low Level Output Voltage V
DD_EXT
= 3.13 V, I
OL
= 2.0 mA 0.400 V
V
OL_DDR22
Low Level Output Voltage, DDR2,
Programmed Impedance = 34 Ω
V
DD_DMC
= 1.70 V, I
OL
= 7.1 mA 0.320 V
V
OL_DDR22
Low Level Output Voltage, DDR2,
Programmed Impedance = 40 Ω
V
DD_DMC
= 1.70 V, I
OL
= 5.8 mA 0.320 V
V
OL_DDR22
Low Level Output Voltage, DDR2,
Programmed Impedance = 50 Ω
V
DD_DMC
= 1.70 V, I
OL
= 4.1 mA 0.320 V
V
OL_DDR22
Low Level Output Voltage, DDR2,
Programmed Impedance = 60 Ω
V
DD_DMC
= 1.70 V, I
OL
= 3.4 mA 0.320 V
V
OL_LPDDR2
Low Level Output Voltage, LPDDR V
DD_DMC
= 1.70 V, I
OL
= 2.0 mA 0.320 V
I
IH4
High Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
10 µA
I
IH_DMC0_VREF5
High Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
1µA
I
IH_PD6
High Level Input Current with Pull-
down Resistor
V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
100 µA
R
PD6
Internal Pull-down Resistance V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
57 130 k
I
IL7
Low Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
10 µA
I
IL_DMC0_VREF5
Low Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
1µA
I
IL_PU8
Low Level Input Current with Pull-up
Resistor
V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
100 µA
R
PU8
Internal Pull-up Resistance V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
53 129 k
I
IH_USB09
High Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
10 µA
I
IL_USB09
Low Level Input Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
10 µA
I
OZH10
Three-State Leakage Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
10 µA
I
OZH11
Three-State Leakage Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 1.9 V
10 µA
I
OZL12
Three-State Leakage Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 0 V
10 µA
I
OZH_PD13
Three-State Leakage Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 3.47 V
100 µA
Rev. D | Page 53 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
I
OZH_TWI14
Three-State Leakage Current V
DD_EXT
= 3.47 V, V
DD_DMC
= 1.9 V,
V
DD_USB
= 3.47 V, V
IN
= 5.5 V
10 µA
ADSP-BF701/703/705/707 Input Capacitance
C
IN
(GPIO)
15
Input Capacitance T
AMBIENT
= 25°C 5.2 6.0 pF
C
IN_TWI14
Input Capacitance T
AMBIENT
= 25°C 6.9 7.4 pF
C
IN_DDR
16
Input Capacitance T
AMBIENT
= 25°C 6.1 6.9 pF
ADSP-BF700/702/704/706 Input Capacitance
C
IN
(GPIO)
15
Input Capacitance T
AMBIENT
= 25°C 5.0 5.3 pF
C
IN_TWI14
Input Capacitance T
AMBIENT
= 25°C 6.8 7.4 pF
I
DD_DEEPSLEEP17,
18
V
DD_INT
Current in Deep Sleep Mode Clocks disabled
T
J
= 25°C
1.4 mA
I
DD_IDLE18
V
DD_INT
Current in Idle f
PLLCLK
= 300 MHz
f
CCLK
= 100 MHz
ASF = 0.05 (idle)
f
SYSCLK
= f
SCLK0
= 25 MHz
USBCLK = DCLK = OUTCLK =
SCLK1 = DISABLED
Peripherals disabled
T
J
= 25°C
13 mA
I
DD_TYP18
V
DD_INT
Current f
PLLCLK
= 800 MHz
f
CCLK
= 400 MHz
ASF = 1.0 (full-on typical)
f
SYSCLK
= f
SCLK0
= 25 MHz
USBCLK = DCLK = OUTCLK =
SCLK1 = DISABLED
Peripherals disabled
T
J
= 25°C
90 mA
I
DD_TYP18
V
DD_INT
Current f
PLLCLK
= 300 MHz
f
CCLK
= 300 MHz
ASF = 1.0 (full-on typical)
f
SYSCLK
= f
SCLK0
= 25 MHz
USBCLK = DCLK = OUTCLK =
SCLK1 = DISABLED
Peripherals disabled
T
J
= 25°C
66 mA
I
DD_TYP18
V
DD_INT
Current f
PLLCLK
= 400 MHz
f
CCLK
= 200 MHz
ASF = 1.0 (full-on typical)
f
SYSCLK
= f
SCLK0
= 25 MHz
USBCLK = DCLK = OUTCLK =
SCLK1 = DISABLED
Peripherals disabled
T
J
= 25°C
49 mA
I
DD_TYP18
V
DD_INT
Current f
PLLCLK
= 300 MHz
f
CCLK
= 100 MHz
ASF = 1.0 (full-on typical)
f
SYSCLK
= f
SCLK0
= 25 MHz
USBCLK = DCLK = OUTCLK =
SCLK1 = DISABLED
Peripherals disabled
T
J
= 25°C
30 mA
Parameter Conditions Min Typ Max Unit
Rev. D | Page 54 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
I
DD_HIBERNATE17,
19
Hibernate State Current V
DD_INT
= 0 V,
V
DD_DMC
= 1.8 V,
V
DD_EXT
= V
DD_HADC
= V
DD_OTP
=
V
DD_RTC
= V
DD_USB
= 3.3 V,
T
J
= 25°C,
f
CLKIN
= 0
33 A
I
DD_HIBERNATE17,
19
Hibernate State Current
Without USB
V
DD_INT
= 0 V,
V
DD_DMC
= 1.8 V,
V
DD_EXT
= V
DD_HADC
= V
DD_OTP
=
V
DD_RTC
= V
DD_USB
= 3.3 V,
T
J
= 25°C,
f
CLKIN
= 0,
USB protection disabled
(USB_PHY_CTLDIS = 1)
15 A
I
DD_INT18
V
DD_INT
Current V
DD_INT
within operating conditions
table specifications
See I
DDINT_TOT
equation on
on Page 55
mA
I
DD_RTC
I
DD_RTC
Current V
DD_RTC
= 3.3 V, T
J
= 125°C 10 A
1
Applies to all output and bidirectional signals except DMC0 signals, TWI signals, and USB0 signals.
2
Applies to DMC0_Axx, DMC0_CAS, DMC0_CKE, DMC0_CK, DMC0_CK, DMC0_CS, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,
DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, and DMC0_WE signals.
3
Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.
4
Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TDI, and JTG_TMS_SWDIO signals.
5
Applies to DMC0_VREF signal.
6
Applies to JTG_TCK_SWCLK and JTG_TRST signals.
7
Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TCK, and JTG_TRST signals.
8
Applies to JTG_TDI, JTG_TMS_SWDIO, PA_xx, PB_xx, and PC_xx signals when internal GPIO pull-ups are enabled. For information on when internal pull-ups are enabled
for GPIOs. See ADSP-BF70x Designer Quick Reference.
9
Applies to USB0_CLKIN signal.
10
Applies to PA_xx, PB_xx, PC_xx, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP,
USB0_ID, and USB0_VBC signals.
11
Applies to DMC0_Axx, DMC0_BAxx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_
UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE signals.
12
Applies to PA_xx, PB_xx, PC_xx, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS,
DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,
DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.
13
Applies to USB0_VBUS signals.
14
Applies to all TWI signals.
15
Applies to all signals, except DMC0 and TWI signals.
16
Applies to all DMC0 signals.
17
See the ADSP-BF70x Blackfin+ Processor Hardware Reference for definition of deep sleep and hibernate operating modes.
18
Additional information can be found at Total Internal Power Dissipation.
19
Applies to VDD_EXT, VDD_DMC, and VDD_USB supply signals only. Clock inputs are tied high or low.
Parameter Conditions Min Typ Max Unit
Rev. D | Page 55 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Total Internal Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current (deep sleep)
2. Dynamic, due to transistor switching characteristics for
each clock domain
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. The following equation describes the internal
current consumption.
I
DDINT_TOT
= I
DDINT_DEEPSLEEP
+ I
DDINT_CCLK_DYN
+
I
DDINT_PLLCLK_DYN
+ I
DDINT_SYSCLK_DYN
+
I
DDINT_SCLK0_DYN
+ I
DDINT_SCLK1_DYN
+
I
DDINT_DCLK_DYN
+ I
DDINT_DMA_DR_DYN
+
I
DDINT_USBCLK_DYN
I
DDINT_DEEPSLEEP
is the only item present that is part of the static
power dissipation component. I
DDINT_DEEPSLEEP
is specified as a
function of voltage (V
DD_INT
) and temperature (see Table 21).
There are eight different items that contribute to the dynamic
power dissipation. These components fall into three broad cate-
gories: application-dependent currents, clock currents, and data
transmission currents.
Application-Dependent Current
The application-dependent currents include the dynamic cur-
rent in the core clock domain.
Core clock (CCLK) use is subject to an activity scaling factor
(ASF) that represents application code running on the processor
cores and L1/L2 memories (Table 22). The ASF is combined
with the CCLK frequency and V
DD_INT
dependent data in
Table 23 to calculate this portion.
I
DDINT_CCLK_DYN
(mA) = Table 23 × ASF
Clock Current
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissi-
pated by each clock domain is dependent on voltage (V
DD_INT
),
operating frequency and a unique scaling factor.
I
DDINT_PLLCLK_DYN
(mA) = 0.012 × f
PLLCLK
(MHz) × V
DD_INT
(V)
I
DDINT_SYSCLK_DYN
(mA) = 0.120 × f
SYSCLK
(MHz) × V
DD_INT
(V)
I
DDINT_SCLK0_DYN
(mA) = 0.110 × f
SCLK0
(MHz) × V
DD_INT
(V)
I
DDINT_SCLK1_DYN
(mA) = 0.068 × f
SCLK1
(MHz) × V
DD_INT
(V)
I
DDINT_DCLK_DYN
(mA) = 0.055 × f
DCLK
(MHz) × V
DD_INT
(V)
The dynamic component of the USB clock is a unique case. The
USB clock contributes a near constant current value when used.
Data Transmission Current
The data transmission current represents the power dissipated
when transmitting data. This current is expressed in terms of
data rate. The calculation is performed by adding the data rate
(MB/s) of each DMA-driven access to peripherals, L1, L2, and
external memory. This number is then multiplied by a weighted
data-rate coefficient and V
DD_INT
:
I
DDINT_DMADR_DYN
(mA) = Weighted DRC × Total Data Rate
(MB/s) × V
DD_INT
(V)
A weighted data-rate coefficient is used because different coeffi-
cients exist depending on the source and destination of the
transfer. For details on using this equation and calculating the
weighted DRC, see the related Engineer Zone material. For a
quick maximum calculation, the weighted DRC can be assumed
to be 0.0497, which is the coefficient for L1 to L1 transfers.
Table 20. I
DDINT_USBCLK_DYN
Current
Is USB Enabled? I
DDINT_USBCLK_DYN
(mA)
Yes – High-Speed Mode 13.94
Yes – Full-Speed Mode 10.83
Yes – Suspend Mode 5.2
No 0.34
Rev. D | Page 56 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 21. Static Current—I
DD_DEEPSLEEP
(mA)
T
J
(°C)
Voltage (V
DD_INT
)
1.045 1.050 1.060 1.070 1.080 1.090 1.100 1.110 1.120 1.130 1.140 1.150 1.155
–40 0.6 0.6 0.7 0.7 0.7 0.8 0.8 0.8 0.9 0.9 0.9 1.0 1.0
–20 1.1 1.1 1.2 1.2 1.2 1.3 1.4 1.4 1.5 1.5 1.6 1.7 1.7
0 2.0 2.0 2.1 2.2 2.3 2.4 2.5 2.5 2.6 2.7 2.8 3.0 3.0
25 4.3 4.3 4.5 4.7 4.8 5.0 5.2 5.3 5.5 5.7 5.9 6.1 6.2
40 6.7 6.8 7.0 7.3 7.5 7.8 8.0 8.3 8.6 8.8 9.1 9.4 9.6
55 10.3 10.5 10.8 11.2 11.5 11.9 12.3 12.6 13.0 13.4 13.9 14.3 14.5
70 15.7 15.9 16.4 16.8 17.4 17.9 18.4 18.9 19.5 20.1 20.7 21.3 21.6
85 23.3 23.6 24.3 25.0 25.7 26.4 27.2 27.9 28.7 29.5 30.4 31.2 31.7
100 34.2 34.6 35.5 36.5 37.5 38.5 39.5 40.6 41.7 42.8 43.9 45.1 45.7
105 38.7 39.2 40.2 41.3 42.4 43.5 44.6 45.8 47.0 48.2 49.5 50.8 51.5
115 48.9 49.5 50.7 52.0 53.4 54.7 56.0 57.5 59.0 60.5 62.0 63.6 64.4
125 61.5 62.1 63.6 65.1 66.7 68.3 69.9 71.7 73.4 75.2 77.0 79.0 79.9
Table 22. Activity Scaling Factors (ASF)
I
DDINT
Power Vector ASF
I
DD-IDLE1
0.05
I
DD-IDLE2
0.05
I
DD-NOP1
0.56
I
DD-NOP2
0.59
I
DD-APP3
0.78
I
DD-APP1
0.79
I
DD-APP2
0.83
I
DD-TYP1
1.00
I
DD-TYP3
1.01
I
DD-TYP2
1.03
I
DD-HIGH1
1.39
I
DD-HIGH3
1.39
I
DD-HIGH2
1.54
Table 23. CCLK Dynamic Current per core (mA, with ASF = 1)
f
CCLK
(MHz)
Voltage (V
DD_INT
)
1.045 1.050 1.060 1.070 1.080 1.090 1.100 1.110 1.120 1.130 1.140 1.150 1.155
400 66.7 67.2 67.9 68.7 69.4 70.2 71.1 71.8 72.6 73.4 74.2 74.9 75.4
350 58.6 59.0 59.6 60.3 61.0 61.7 62.4 63.0 63.7 64.4 65.1 65.8 66.1
300 50.2 50.5 51.1 51.7 52.3 52.9 53.5 54.1 54.7 55.3 55.9 56.4 56.8
250 42.1 42.3 42.8 43.3 43.8 44.3 44.7 45.3 45.8 46.3 46.8 47.4 47.6
200 33.7 33.9 34.3 34.7 35.1 35.5 35.9 36.3 36.7 37.1 37.5 37.9 38.0
150 25.4 25.5 25.8 26.1 26.4 26.7 27.0 27.3 27.6 27.9 28.2 28.5 28.8
100 17.0 17.1 17.3 17.5 17.7 17.9 18.1 18.3 18.5 18.6 18.8 19.0 19.1
Rev. D | Page 57 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
HADC
HADC Electrical Characteristics
HADC DC Accuracy
HADC Timing Specifications
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 27 may cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
ESD SENSITIVITY
Table 24. HADC Electrical Characteristics
Parameter Conditions Typ Unit
I
DD_HADC_IDLE
Current Consumption on V
DD_HADC
.
HADC is powered on, but not
converting.
2.0 mA
I
DD_HADC_ACTIVE
Current Consumption on V
DD_HADC
during a conversion.
2.5 mA
I
DD_HADC_
POWERDOWN
Current Consumption on V
DD_HADC
.
Analog circuitry of the HADC is
powered down
10 µA
Table 25. HADC DC Accuracy
1
1
See the Operating Conditions section for the HADC0_VINx specification.
Parameter Typ Unit
2
2
LSB = HADC0_VREFP ÷ 4096
Resolution 12 Bits
No Missing Codes (NMC) 10 Bits
Integral Nonlinearity (INL) ±2 LSB
Differential Nonlinearity (DNL) ±2 LSB
Offset Error ±8 LSB
Offset Error Matching ±10 LSB
Gain Error ±4 LSB
Gain Error Matching ±4 LSB
Table 26. HADC Timing Specifications
Parameter Typ Max Unit
Conversion Time 20 × T
SAMPLE
µs
Throughput Range 1 MSPS
T
WAKEUP
100 µs
Table 27. Absolute Maximum Ratings
Parameter Rating
Internal Supply Voltage (V
DD_INT
) –0.33 V to +1.26 V
External (I/O) Supply Voltage (V
DD_EXT
) –0.33 V to +3.60 V
DDR2/LPDDR Controller Supply
Voltage (V
DD_DMC
)
–0.33 V to +1.90 V
USB PHY Supply Voltage (V
DD_USB
) –0.33 V to +3.60 V
Real-Time Clock Supply Voltage
(V
DD_RTC
)
–0.33 V to +3.60 V
One-Time Programmable Memory
Supply Voltage (V
DD_OTP
)
–0.33 V to +3.60 V
HADC Supply Voltage (V
DD_HADC
) –0.33 V to +3.60 V
HADC Reference Voltage (V
HADC_REF
) –0.33 V to +3.60 V
DDR2 Reference Voltage (V
DDR_VREF
) –0.33 V to +1.90 V
Input Voltage
1, 2,
3
1
Applies to 100% transient duty cycle.
2
Applies only when the related power supply (V
DD_DMC
, V
DD_EXT
, or V
DD_USB
) is
within specification. When the power supply is below specification, the range is
the voltage being applied to that power domain ± 0.2 V.
3
Applies when nominal V
DD_EXT
is 3.3 V.
–0.33 V to +3.63 V
Input Voltage
1, 2,
4
4
Applies when nominal V
DD_EXT
is 1.8 V.
–0.33 V to +2.10 V
TWI Input Voltage
2, 5
5
Applies to TWI_SCL and TWI_SDA.
–0.33 V to +5.50 V
USB0_Dx Input Voltage
2,
6
6
If the USB is not used, connect these pins according to Table 15.
–0.33 V to +5.25 V
USB0_VBUS Input Voltage
2,
6
–0.33 V to +6.00 V
DDR2/LPDDR Input Voltage
2
–0.33 V to +2.10 V
Output Voltage Swing –0.33 V to V
DD_EXT
+ 0.5 V
Analog Input Voltage
7
7
Applies only when V
DD_HADC
is within specifications and ≤ 3.4 V. When V
DD_HADC
is within specifications and > 3.4 V, the maximum rating is 3.6 V. When V
DD_
HADC
is below specifications, the range is V
DD_HADC
± 0.2 V.
–0.2 V to V
DD_HADC
+ 0.2 V
I
OH
/I
OL
Current per Signal
1
4 mA (maximum)
Storage Temperature Range –65°C to +150°C
Junction Temperature While Biased +125°C
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
Rev. D | Page 58 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 28 and Figure 7 describe clock and reset operations related to the clock generation unit (CGU). Per the CCLK, SYSCLK, SCLK0,
SCLK1, DCLK, and OCLK timing specifications in Table 17 and Table 18, combinations of SYS_CLKIN and clock multipliers must not
select clock rates in excess of the processor’s maximum instruction rate.
Table 28. Clock and Reset Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
f
CKIN
SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 0)
1,
2,
3
1
Applies to PLL bypass mode and PLL nonbypass mode.
2
The t
CKIN
period (see Figure 7) equals 1/f
CKIN
.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
PLLCLK
setting discussed in Table 19.
19.2 35 19.2 50 MHz
f
CKIN
SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 1)
1,
2,
3
N/A N/A 38.4 50 MHz
f
CKIN
SYS_CLKIN External Source Frequency (CGU_CTL.DF = 0)
1,
2,
3
19.2 60 19.2 60 MHz
f
CKIN
SYS_CLKIN External Source Frequency (CGU_CTL.DF = 1)
1,
2,
3
38.4 60 38.4 60 MHz
t
CKINL
SYS_CLKIN Low Pulse
1
8.33 8.33 ns
t
CKINH
SYS_CLKIN High Pulse
1
8.33 8.33 ns
t
WRST
SYS_HWRST Asserted Pulse Width Low
4
4
Applies after power-up sequence is complete. See Table 29 and Figure 8 for power-up reset timing.
11 × t
CKIN
11 × t
CKIN
ns
Figure 7. Clock and Reset Timing
SYS_CLKIN
tWRST
tCKIN
tCKINL tCKINH
SYS_HWRST
Rev. D | Page 59 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Power-Up Reset Timing
A power-up reset is required to place the processor in a known state after power-up. A power-up reset is initiated by asserting
SYS_HWRST and JTG_TRST. During power-up reset, all pins are high impedance except for those noted in the ADSP-BF70x Designer
Quick Reference.
Both JTG_TRST and SYS_HWRST need to be asserted upon power-up, but only SYS_HWRST needs to be released for the device to boot
properly. JTG_TRST may be asserted indefinitely for normal operation. JTG_TRST only needs to be released when using an emulator to
connect to the DAP for debug or boundary scan. There is an internal pull-down on JTG_TRST to ensure internal emulation logic will
always be properly initialized during power-up reset.
Table 29 and Figure 8 show the relationship between power supply startup and processor reset timing, related to the clock generation unit
(CGU) and reset control unit (RCU). In Figure 8, V
DD_SUPPLIES
are V
DD_INT
, V
DD_EXT
, V
DD_DMC
, V
DD_USB
, V
DD_RTC
, V
DD_OTP
, and V
DD_HADC
.
There is no power supply sequencing requirement for the ADSP-BF70x processor. However, if saving power during power-on is import-
ant, bringing up V
DD_INT
last is recommended. This avoids a small current drain in the V
DD_INT
domain during the transition period of I/O
voltages from 0 V to within the voltage specification.
Table 29. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirement
t
RST_IN_PWR
SYS_HWRST and JTG_TRST Deasserted After V
DD_INT
, V
DD_DMC
, V
DD_USB
,
V
DD_RTC
, V
DD_OTP
, V
DD_HADC
, and SYS_CLKIN are Stable and Within Specification
11 × t
CKIN
ns
t
VDDEXT_RST
SYS_HWRST Deasserted After V
DD_EXT
is Stable and Within Specifications
(No External Pull-Down on JTG_TRST)
10 µs
t
VDDEXT_RST
SYS_HWRST Deasserted After V
DD_EXT
is Stable and Within Specifications (10k
External Pull-Down on JTG_TRST)
1µs
Figure 8. Power-Up Reset Timing
tRST_IN_PWR
SYS_HWRST
AND
JTG_TRST
CLKIN
V
DD_SUPPLIES
(EXCEPT VDD_EXT)
VDD_EXT
tVDDEXT_RST
Rev. D | Page 60 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Asynchronous Read
Table 30 and Figure 9 show asynchronous memory read timing, related to the static memory controller (SMC).
Table 30. Asynchronous Memory Read (BxMODE = b#00)
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SDATARE
DATA in Setup Before
SMC0_ARE High
11.8 10.8 ns
t
HDATARE
DATA in Hold After
SMC0_ARE High
00ns
t
DARDYARE
SMC0_ARDY Valid After
SMC0_ARE Low
1,
2
1
SMC0_BxCTL.ARDYEN bit = 1.
2
RAT value set using the SMC_BxTIM.RAT bits.
(RAT – 2.5) ×
t
SCLK0
– 17.5
(RAT – 2.5) ×
t
SCLK0
– 17.5
ns
Switching Characteristics
t
AMSARE
SMC0_Ax/SMC0_AMSx
Assertion Before
SMC0_ARE Low
3
3
PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
(PREST + RST + PREAT)
× t
SCLK0
– 2
(PREST + RST + PREAT)
× t
SCLK0
– 2
ns
t
DADVARE
SMC0_ARE Low Delay
From ADV High
PREAT × t
SCLK0
– 2 PREAT × t
SCLK0
– 2 ns
t
AOEARE
SMC0_AOE Assertion
Before SMC0_ARE Low
(RST + PREAT) ×
t
SCLK0
– 2
(RST + PREAT) ×
t
SCLK0
– 2
ns
t
HARE
Output
4
Hold After
SMC0_ARE High
5
4
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx.
5
RHT value set using the SMC_BxTIM.RHT bits.
RHT × t
SCLK0
– 2 RHT × t
SCLK0
– 2 ns
t
WARE
SMC0_ARE Active Low
Width
6
6
SMC0_BxCTL.ARDYEN bit = 0.
RAT × t
SCLK0
– 2 RAT × t
SCLK0
– 2 ns
t
DAREARDY
SMC0_ARE High Delay
After SMC0_ARDY
Assertion
1
3.5 × t
SCLK0
+ 17.5 3.5 × t
SCLK0
+ 17.5 ns
Rev. D | Page 62 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SMC Read Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to
programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum f
OCLK
specification.
For this example, RST = 0x2, RAT = 0x4, and RHT = 0x1.
Table 31. SMC Read Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SDAT
SMC0_Dx Setup Before SYS_CLKOUT 5.3 4.3 ns
t
HDAT
SMC0_Dx Hold After SYS_CLKOUT 1.5 1.5 ns
t
SARDY
SMC0_ARDY Setup Before SYS_CLKOUT 16.6 14.4 ns
t
HARDY
SMC0_ARDY Hold After SYS_CLKOUT 0.7 0.7 ns
Switching Characteristics
t
DO
Output Delay After SYS_CLKOUT
1
1
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx.
77ns
t
HO
Output Hold After SYS_CLKOUT
1
–2.5 –2.5 ns
Figure 10. Asynchronous Memory Read Cycle Timing
tHARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
tDO tHO
tDO
tHARDY
tSARDY
tSDAT
tHDAT
tSARDY
SYS_CLKOUT
SMC0_AMSx
SMC0_ABEx
SMC0_AOE
SMC0_ARE
SMC0_ARDY
DATA 15–0
tHO
SMC0_Ax
Rev. D | Page 63 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Asynchronous Flash Read
Table 32 and Figure 11 show asynchronous flash memory read timing, related to the static memory controller (SMC).
Table 32. Asynchronous Flash Read
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
AMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV
Low
1
1
PREST value set using the SMC_BxETIM.PREST bits.
PREST × t
SCLK0
– 2 ns
t
WADV
SMC0_NORDV Active Low Width
2
2
RST value set using the SMC_BxTIM.RST bits.
RST × t
SCLK0
– 2 ns
t
DADVARE
SMC0_ARE Low Delay From SMC0_NORDV High
3
3
PREAT value set using the SMC_BxETIM.PREAT bits.
PREAT × t
SCLK0
– 2 ns
t
HARE
Output
4
Hold After SMC0_ARE High
5
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5
RHT value set using the SMC_BxTIM.RHT bits.
RHT × t
SCLK0
– 2 ns
t
WARE6
6
SMC0_BxCTL.ARDYEN bit = 0.
SMC0_ARE Active Low Width
7
7
RAT value set using the SMC_BxTIM.RAT bits.
RAT × t
SCLK0
– 2 ns
Figure 11. Asynchronous Flash Read
SMC0_Ax
tAMSADV
tDADVARE
tWADV
tWARE tHARE
READ LATCHED
DATA
SMC0_AMSx
(NOR_CE)
SMC0_NORDV
SMC0_ARE
(NOR_OE)
SMC0_Dx
(DATA)
Rev. D | Page 64 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Asynchronous Page Mode Read
Table 33 and Figure 12 show asynchronous memory page mode read timing, related to the static memory controller (SMC).
Table 33. Asynchronous Page Mode Read
V
DD_EXT
1.8 V /3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
AV
SMC0_Ax (Address) Valid for First Address Min Width
1
1
PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
(PREST + RST + PREAT + RAT) × t
SCLK0
– 2 ns
t
AV1
SMC0_Ax (Address) Valid for Subsequent SMC0_Ax
(Address) Min Width
PGWS × t
SCLK0
– 2 ns
t
WADV
SMC0_NORDV Active Low Width
2
2
RST value set using the SMC_BxTIM.RST bits.
RST × t
SCLK0
– 2 ns
t
HARE
Output
3
Hold After SMC0_ARE High
4
3
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4
RHT value set using the SMC_BxTIM.RHT bits.
RHT × t
SCLK0
– 2 ns
t
WARE5
5
SMC_BxCTL.ARDYEN bit = 0.
SMC0_ARE Active Low Width
6
6
RAT value set using the SMC_BxTIM.RAT bits.
(RAT + (Nw – 1) × PGWS) × t
SCLK0
– 2 ns
Figure 12. Asynchronous Page Mode Read
SMC0_AMSx
(NOR_CE)
SMC0_ARE
(NOR_OE)
SMC0_AOE
NOR_ADV
SMC0_Dx
(DATA)
A0
tWADV
tWARE tHARE
D0 D1 D2 D3
A0 + 1 A0 + 2 A0 + 3
tAV tAV1 tAV1 tAV1
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
SMC0_Ax
(ADDRESS)
Rev. D | Page 65 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Asynchronous Write
Table 34 and Figure 13 show asynchronous memory write timing, related to the static memory controller (SMC).
Table 34. Asynchronous Memory Write (BxMODE = b#00)
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
t
DARDYAWE1
1
SMC_BxCTL.ARDYEN bit = 1.
SMC0_ARDY Valid After
SMC0_AWE Low
2
2
WAT value set using the SMC_BxTIM.WAT bits.
(WAT – 2.5) ×
t
SCLK0
– 17.5
(WAT – 2.5) ×
t
SCLK0
– 17.5
ns
Switching Characteristics
t
ENDAT
DATA Enable After SMC0_AMSx
Assertion
–3 –2 ns
t
DDAT
DATA Disable After SMC0_AMSx
Deassertion
4.5 4 ns
t
AMSAWE
SMC0_Ax/SMC0_AMSx Assertion
Before SMC0_AWE Low
3
3
PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
(PREST + WST +
PREAT) × t
SCLK0
– 2
(PREST + WST +
PREAT) × t
SCLK0
– 4
ns
t
HAWE
Output
4
Hold After SMC0_AWE High
5
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
WHT × t
SCLK0
WHT × t
SCLK0
ns
t
WAWE6
6
SMC_BxCTL.ARDYEN bit = 0.
SMC0_AWE Active Low Width
6
WAT × t
SCLK0
– 2 WAT × t
SCLK0
– 2 ns
t
DAWEARDY1
SMC0_AWE High Delay After
SMC0_ARDY Assertion
3.5 × t
SCLK0
+ 17.5 3.5 × t
SCLK0
+ 17.5 ns
Figure 13. Asynchronous Write
SMC0_AWE
SMC0_ABEx
SMC0_Ax
tDARDYAWE
tAMSAWE
tDAWEARDY
tENDAT tDDAT
tHAWE
tWAWE
SMC0_AMSx
SMC0_Dx (DATA)
SMC0_ARDY
Rev. D | Page 66 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
SMC Write Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to
programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum f
OCLK
specification.
For this example WST = 0x2, WAT = 0x2, and WHT = 0x1.
Table 35. SMC Write Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SARDY
SMC0_ARDY Setup Before SYS_CLKOUT 14.4 ns
t
HARDY
SMC0_ARDY Hold After SYS_CLKOUT 0.7 ns
Switching Characteristics
t
DDAT
SMC0_Dx Disable After SYS_CLKOUT 7 ns
t
ENDAT
SMC0_Dx Enable After SYS_CLKOUT –2.5 ns
t
DO
Output Delay After SYS_CLKOUT
1
1
Output pins/balls include SMC0_AMSx, SMC0_ABEx, SMC0_Ax, SMC0_Dx, SMC0_AOE, and SMC0_AWE.
7ns
t
HO
Output Hold After SYS_CLKOUT
1
–2.5 ns
Figure 14. SMC Write Cycle Timing With Reference to SYS_CLKOUT Timing
SETUP
2 CYCLES
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
tDO tHO
SYS_CLKOUT
SMC0_ABEx
SMC0_AWE
SMC0_ARDY
SMC0_Dx
tSARDY
tSARDY
tDDAT
tENDAT tHARDY
tHO
tDO
tHARDY
SMC0_Ax
SMC0_AMSx
Rev. D | Page 67 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Asynchronous Flash Write
Table 36 and Figure 15 show asynchronous flash memory write timing, related to the static memory controller (SMC).
All Accesses
Table 37 describes timing that applies to all memory accesses, related to the static memory controller (SMC).
Table 36. Asynchronous Flash Write
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
AMSADV
SMC0_Ax/SMC0_AMSx Assertion Before ADV Low
1
1
PREST value set using the SMC_BxETIM.PREST bits.
PREST × t
SCLK0
– 2 ns
t
DADVAWE
SMC0_AWE Low Delay From ADV High
2
2
PREAT value set using the SMC_BxETIM.PREAT bits.
PREAT × t
SCLK0
– 4 ns
t
WADV
NR_ADV Active Low Width
3
3
WST value set using the SMC_BxTIM.WST bits.
WST × t
SCLK0
– 2 ns
t
HAWE
Output
4
Hold After SMC0_AWE High
5
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
WHT × t
SCLK0
ns
t
WAWE6
6
SMC_BxCTL.ARDYEN bit = 0.
SMC0_AWE Active Low Width
7
7
WAT value set using the SMC_BxTIM.WAT bits.
WAT × t
SCLK0
– 2 ns
Figure 15. Asynchronous Flash Write
Table 37. All Accesses
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Switching Characteristic
t
TURN
SMC0_AMSx Inactive Width (IT + TT) × t
SCLK0
– 2 (IT + TT) × t
SCLK0
– 2 ns
NR_CE
(SMC0_AMSx)
NR_WE
(SMC0_AWE)
NOR_A x
-
1
(SMC0_Ax)
NR_ADV
(SMC0_AOE)
tAMSADV
tDADVAWE
NR_DQ 15
-
0
(SMC0_Dx)
tWADV
tWAWE tHAWE
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DDR2 SDRAM Clock and Control Cycle Timing
Table 38 and Figure 16 show DDR2 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC).
Table 38. DDR2 SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Switching Characteristics
t
CK
Clock Cycle Time (CL = 2 Not Supported) 5 ns
t
CH
High Clock Pulse Width 0.45 0.55 t
CK
t
CL
Low Clock Pulse Width 0.45 0.55 t
CK
t
IS
Control/Address Setup Relative to DMC0_CK Rise 350 ps
t
IH
Control/Address Hold Relative to DMC0_CK Rise 475 ps
Figure 16. DDR2 SDRAM Clock and Control Cycle Timing
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
-
13, AND DMC0_BA0
-
2.
DMC0_CK
ADDRESS
CONTROL
tIS tIH
tCK tCH tCL
DMC0_CK
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DDR2 SDRAM Read Cycle Timing
Table 39 and Figure 17 show DDR2 SDRAM read cycle timing, related to the dynamic memory controller (DMC).
Table 39. DDR2 SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
1
1
To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
Parameter Min Max Unit
Timing Requirements
t
DQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_
DQ Signals
0.35 ns
t
QH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS 1.8 ns
t
RPRE
Read Preamble 0.9 t
CK
t
RPST
Read Postamble 0.4 t
CK
Figure 17. DDR2 SDRAM Controller Input AC Timing
DMC0_CKx
DMC0_DQSn
tRPRE
tDQSQ
tDQSQ
tQH
tRPST
DMC0_DQx
DMC0_CKx
DMC0_DQSn
tQH
DMC0_Ax
DMC0 CONTROL
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DDR2 SDRAM Write Cycle Timing
Table 40 and Figure 18 show DDR2 SDRAM write cycle timing, related to the dynamic memory controller (DMC).
Table 40. DDR2 SDRAM Write Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
1
1
To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
Parameter Min Max Unit
Switching Characteristics
t
DQSS2
2
Write command to first DMC0_DQS delay = WL × t
CK
+ t
DQSS
.
DMC0_DQS Latching Rising Transitions to Associated Clock Edges –0.25 +0.25 t
CK
t
DS
Last Data Valid to DMC0_DQS Delay 0.15 ns
t
DH
DMC0_DQS to First Data Invalid Delay 0.275 ns
t
DSS
DMC0_DQS Falling Edge to Clock Setup Time 0.2 t
CK
t
DSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 t
CK
t
DQSH
DMC0_DQS Output High Pulse Width 0.35 t
CK
t
DQSL
DMC0_DQS Output Low Pulse Width 0.35 t
CK
t
WPRE
Write Preamble 0.35 t
CK
t
WPST
Write Postamble 0.4 t
CK
t
IPW
Address and Control Output Pulse Width 0.6 t
CK
t
DIPW
DMC0_DQ and DMC0_DM Output Pulse Width 0.35 t
CK
Figure 18. DDR2 SDRAM Controller Output AC Timing
tDS tDH
tDQSS
tDSH tDSS
tWPRE tDQSL tDQSH tWPST
DMC0_LDM
DMC0_CK
tIPW
tDIPW
DMC0_UDM
DMC0_LDQS
DMC0_UDQS
DMC0_CK
DMC0_Ax
DMC0 CONTROL
DMC0_DQx
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Mobile DDR SDRAM Clock and Control Cycle Timing
Table 41 and Figure 19 show mobile DDR SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC).
Table 41. Mobile DDR SDRAM Clock and Control Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Switching Characteristics
t
CK
Clock Cycle Time (CL = 2 Not Supported) 5 ns
t
CH
Minimum Clock Pulse Width 0.45 0.55 t
CK
t
CL
Maximum Clock Pulse Width 0.45 0.55 t
CK
t
IS
Control/Address Setup Relative to DMC0_CK Rise 1.5 ns
t
IH
Control/Address Hold Relative to DMC0_CK Rise 1.5 ns
Figure 19. Mobile DDR SDRAM Clock and Control Cycle Timing
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
-
13, AND DMC0_BA0
-
2.
DMC0_CK
ADDRESS
CONTROL
tIS tIH
tCK tCH tCL
DMC0_CK
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Mobile DDR SDRAM Read Cycle Timing
Table 42 and Figure 20 show mobile DDR SDRAM read cycle timing, related to the dynamic memory controller (DMC).
Table 42. Mobile DDR SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Timing Requirements
t
QH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS 1.5 ns
t
DQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated
DMC0_DQ Signals
0.7 ns
t
RPRE
Read Preamble 0.9 1.1 t
CK
t
RPST
Read Postamble 0.4 0.6 t
CK
Figure 20. Mobile DDR SDRAM Controller Input AC Timing
DMC0_CK
DMC0_DQS
tDQSQ
DMC0_DQS
(DATA)
Dn Dn+1 Dn+2 Dn+3
tRPRE tRPST
tQH
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Mobile DDR SDRAM Write Cycle Timing
Table 43 and Figure 21 show mobile DDR SDRAM write cycle timing, related to the dynamic memory controller (DMC).
Table 43. Mobile DDR SDRAM Write Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Switching Characteristics
t
DQSS1
1
Write command to first DMC0_DQS delay = WL × t
CK
+ t
DQSS
.
DMC0_DQS Latching Rising Transitions to Associated Clock Edges 0.75 1.25 t
CK
t
DS
Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns) 0.48 ns
t
DH
DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.48 ns
t
DSS
DMC0_DQS Falling Edge to Clock Setup Time 0.2 t
CK
t
DSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 t
CK
t
DQSH
DMC0_DQS Input High Pulse Width 0.4 t
CK
t
DQSL
DMC0_DQS Input Low Pulse Width 0.4 t
CK
t
WPRE
Write Preamble 0.25 t
CK
t
WPST
Write Postamble 0.4 t
CK
t
IPW
Address and Control Output Pulse Width 2.3 ns
t
DIPW
DMC0_DQ and DMC0_DM Output Pulse Width 1.8 ns
Figure 21. Mobile DDR SDRAM Controller Output AC Timing
DMC0_CK
DMC0_DQS0
-
1
DMC0_DQ0
-
15/
DMC0_DQM0
-
1
tDQSS
tDSH tDSS
tDQSL tDQSH tWPST
tWPRE
tDS tDH
tDIPW
CONTROL Write CMD
Dn Dn+1 Dn+2 Dn+3
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
-
13, AND DMC0_BA0
-
1.
tDIPW
tIPW
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General-Purpose I/O Port Timing (GPIO)
Table 44 and Figure 22 describe I/O timing, related to the general-purpose ports (PORT).
Timer Cycle Timing
Table 45 and Figure 23 describe timer expired operations, related to the general-purpose timer (TIMER). The input signal is asynchro-
nous in width capture mode and external clock mode and has an ideal maximum input frequency of (f
SCLK0
/4) MHz. The Period Value
(VALUE) is the timer period assigned in the TMx_TMRn_PER register and can range from 2 to 2
32
– 1.
Table 44. General-Purpose I/O Port Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirement
t
WFI
General-Purpose Port Pin Input Pulse Width 2 × t
SCLK0
– 1.5 ns
Figure 22. General-Purpose I/O Port Timing
Table 45. Timer Cycle Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
WL
Timer Pulse Width Input Low
1
1
This specification indicates the minimum instantaneous width that can be tolerated due to duty cycle variation or jitter for TMx signals in width capture and external clock
modes. The ideal maximum frequency for TMx signals is listed in Timer Cycle Timing on this page.
2 × t
SCLK0
– 1.5 2 × t
SCLK0
– 1.5 ns
t
WH
Timer Pulse Width Input High
1
2 × t
SCLK0
– 1.5 2 × t
SCLK0
– 1.5 ns
Switching Characteristic
t
HTO
Timer Pulse Width Output t
SCLK0
× VALUE – 1 t
SCLK0
× VALUE – 1 ns
Figure 23. Timer Cycle Timing
GPIO INPUT
tWFI
TMR OUTPUT
TMR INPUT
tWH, tWL
tHTO
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Up/Down Counter/Rotary Encoder Timing
Table 46 and Figure 24 describe timing, related to the general-purpose counter (CNT).
Table 46. Up/Down Counter/Rotary Encoder Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width 2 × t
SCLK0
2 × t
SCLK0
ns
Figure 24. Up/Down Counter/Rotary Encoder Timing
CNT_UD
CNT_DG
CNT_ZM
tWCOUNT
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Debug Interface (JTAG Emulation Port) Timing
Table 47 and Figure 25 provide I/O timing, related to the debug interface (JTAG emulator port).
Table 47. JTAG Port Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
TCK
JTG_TCK Period 20 20 ns
t
STAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High 5 4 ns
t
HTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High 4 4 ns
t
SSYS
System Inputs Setup Before JTG_TCK High
1
1
System inputs = DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_xx, PB_xx, PC_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT,
SYS_NMI, TWI0_SCL, TWI0_SDA, and SYS_EXTWAKE.
44ns
t
HSYS
System Inputs Hold After JTG_TCK High
1
4 4 ns
t
TRSTW
JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)
2
2
50 MHz maximum.
44t
TCK
Switching Characteristics
t
DTDO
JTG_TDO Delay From JTG_TCK Low 16.5 14.5 ns
t
DSYS
System Outputs Delay After JTG_TCK Low
3
3
System outputs = DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,
DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, PA_xx, PB_xx, PC_xx, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT, and SYS_NMI.
18 16.5 ns
t
DTMS
TMS Delay After TCK High in SWD Mode 3.5 16.5 3.5 14.5 ns
Figure 25. JTAG Port Timing
JTG_TCK
JTG_TMS
JTG_TDI
JTG_TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP tHTAP
tDTDO
tSSYS tHSYS
tDSYS
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Serial Ports
To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications
must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock
(SPT_CLK) width. In Figure 26 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active
sampling edge.
When externally generated the SPORT clock is called f
SPTCLKEXT
:
When internally generated, the programmed SPORT clock (f
SPTCLKPROG
) frequency in MHz is set by the following equation where CLKDIV
is a field in the SPORT_DIV register that can be set from 0 to 65,535:
Table 48. Serial Ports—External Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in Either
Transmit or Receive Mode)
1
1
Referenced to sample edge.
1.5 1 ns
t
HFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in Either
Transmit or Receive Mode)
1
33 ns
t
SDRE
Receive Data Setup Before Receive SPT_CLK
1
1.5 1 ns
t
HDRE
Receive Data Hold After SPT_CLK
1
33 ns
t
SCLKW
SPT_CLK Width
2
2
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external
SPT_CLK ideal maximum frequency, see the f
SPTCLKEXT
specification in Table 18 in Clock Related Operating Conditions.
(0.5 × t
SPTCLKEXT
) – 1 (0.5 × t
SPTCLKEXT
) – 1 ns
t
SPTCLKE
SPT_CLK Period
2
t
SPTCLKEXT
– 1 t
SPTCLKEXT
– 1 ns
Switching Characteristics
t
DFSE
Frame Sync Delay After SPT_CLK
(Internally Generated Frame Sync in Either
Transmit or Receive Mode)
3
3
Referenced to drive edge.
18 15 ns
t
HOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in Either
Transmit or Receive Mode)
3
2.5 2.5 ns
t
DDTE
Transmit Data Delay After Transmit SPT_CLK
3
18 15 ns
t
HDTE
Transmit Data Hold After Transmit SPT_CLK
3
2.5 2.5 ns
tSPTCLKEXT
1
fSPTCLKEXT
-------------------------------=
fSPTCLKPROG
fSCLK0
CLKDIV 1+
-----------------------------=
tSPTCLKPROG
1
fSPTCLKPROG
-----------------------------------=
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Table 49. Serial Ports—Internal Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in Either
Transmit or Receive Mode)
1
17 14.5 ns
t
HFSI
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in Either
Transmit or Receive Mode)
1
–0.5 –0.5 ns
t
SDRI
Receive Data Setup Before SPT_CLK
1
6.5 5 ns
t
HDRI
Receive Data Hold After SPT_CLK
1
1.5 1 ns
Switching Characteristics
t
DFSI
Frame Sync Delay After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)
2
22ns
t
HOFSI
Frame Sync Hold After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)
2
–4.5 –3.5 ns
t
DDTI
Transmit Data Delay After SPT_CLK
2
22ns
t
HDTI
Transmit Data Hold After SPT_CLK
2
–5 –3.5 ns
t
SCLKIW
SPT_CLK Width
3
0.5 × t
SPTCLKPROG
– 1.5 0.5 × t
SPTCLKPROG
– 1.5 ns
t
SPTCLKI
SPT_CLK Period
3
t
SPTCLKPROG
– 1.5 t
SPTCLKPROG
– 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t
SPTCLKPROG
.
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Figure 26. Serial Ports
DRIVE EDGE SAMPLE EDGE
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
tHOFSI tHFSI
tHDRI
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tHFSI
tDDTI
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tHOFSE
tHOFSI
tHDTI
tHFSE
tHDTE
tDDTE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tHOFSE tHFSE
tHDRE
DATA RECEIVE—EXTERNAL CLOCK
tSCLKIW
tDFSI
tSFSI
tSDRI
tSCLKW
tDFSE
tSFSE
tSDRE
tDFSE
tSFSE
tSFSI
tDFSI
tSCLKIW tSCLKW
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
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Table 50. Serial Ports—Enable and Three-State
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTEN
Data Enable from External Transmit SPT_CLK
1
11ns
t
DDTTE
Data Disable from External Transmit SPT_CLK
1
14 14 ns
t
DDTIN
Data Enable from Internal Transmit SPT_CLK
1
–1.12 –1 ns
t
DDTTI
Data Disable from Internal Transmit SPT_CLK
1
2.8 2.8 ns
1
Referenced to drive edge.
Figure 27. Serial Ports—Enable and Three-State
DRIVE EDGE DRIVE EDGE
tDDTIN
tDDTEN tDDTTE
SPT_CLK
(SPORT CLOCK
INTERNAL)
SPT_A/BDx
(DATA
CHANNEL A/B)
SPT_CLK
(SPORT CLOCK
EXTERNAL)
SPT_A/BDx
(DATA
CHANNEL A/B)
DRIVE EDGE DRIVE EDGE
tDDTTI
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The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection
registers) the SPT_TDV is asserted for communication with external devices.
Table 51. Serial Ports—Transmit Data Valid (TDV)
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
t
DRDVEN
Data-Valid Enable Delay from Drive Edge of External Clock
1
1
Referenced to drive edge.
2.5 2.5 ns
t
DFDVEN
Data-Valid Disable Delay from Drive Edge of External Clock
1
17.5 14.5 ns
t
DRDVIN
Data-Valid Enable Delay from Drive Edge of Internal Clock
1
–4.5 –3.5 ns
t
DFDVIN
Data-Valid Disable Delay from Drive Edge of Internal Clock
1
22ns
Figure 28. Serial Ports—Transmit Data Valid Internal and External Clock
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
tDRDVEN tDFDVEN
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
tDRDVIN tDFDVIN
SPT_A/BTDV
SPT_A/BTDV
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Table 52. Serial Ports—External Late Frame Sync
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External Transmit Frame Sync or External
Receive Frame Sync with MCE = 1, MFD = 0
1
19 15.5 ns
t
DDTENFS
Data Enable for MCE = 1, MFD = 0
1
0.5 0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.
Figure 29. External Late Frame Sync
DRIVE SAMPLE
2ND BIT1ST BIT
DRIVE
tDDTE/I
tHDTE/I
tDDTLFSE
tDDTENFS
tSFSE/I
tHFSE/I
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BFS
(FRAME SYNC)
SPT_A/BCLK
(SPORT CLOCK)
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Serial Peripheral Interface (SPI) Port—Master Timing
Table 53 and Figure 30 describe serial peripheral interface (SPI) port master operations.
When internally generated, the programmed SPI clock (f
SPICLKPROG
) frequency in MHz is set by the following equation where BAUD is a
field in the SPI_CLK register that can be set from 0 to 65,535:
Note that:
• In dual mode data transmit, the SPI_MISO signal is also an output.
• In quad mode data transmit, the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs.
• In dual mode data receive, the SPI_MOSI signal is also an input.
• In quad mode data receive, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs.
• To add additional frame delays, see the documentation for the SPI_DLY register in the hardware reference manual.
Table 53. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SPI_CLK Edge (Data Input
Setup)
6.5 5.5 ns
t
HSPIDM
SPI_CLK Sampling E dg e to Da ta Inp ut I nvalid 1 1 ns
Switching Characteristics
t
SDSCIM
SPI_SEL low to First SPI_CLK Edge 0.5 × t
SCLK0
– 2.5 0.5 × t
SCLK0
– 1.5 ns
t
SPICHM
SPI_CLK High Period
1
1
See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t
SPICLKPROG
.
0.5 × t
SPICLKPROG
– 1.5 0.5 × t
SPICLKPROG
– 1.5 ns
t
SPICLM
SPI_CLK Low Period
1
0.5 × t
SPICLKPROG
– 1.5 0.5 × t
SPICLKPROG
– 1.5 ns
t
SPICLK
SPI_CLK Period
1
t
SPICLKPROG
– 1.5 t
SPICLKPROG
– 1.5 ns
t
HDSM
Last SPI_CLK Edge to SPI_SEL High (0.5 × t
SCLK0
) – 2.5 (0.5 × t
SCLK0
) – 1.5 ns
t
SPITDM
Sequential Transfer Delay
2
2
STOP value set using the SPI_DLY.STOP bits.
(STOP × t
SPICLK
) – 1.5 (STOP × t
SPICLK
) – 1.5 ns
t
DDSPIDM
SPI_CLK Edge to Data Out Valid (Data Out
Delay)
2.5 2 ns
t
HDSPIDM
SPI_CLK Edge to Data Out Invalid (Data Out
Hold)
–4.5 –3.5 ns
fSPICLKPROG
fSCLK0
BAUD 1+
-------------------------=
tSPICLKPROG
1
fSPICLKPROG
---------------------------------=
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Figure 30. Serial Peripheral Interface (SPI) Port—Master Timing
tSDSCIM tSPICLK tHDSM tSPITDM
tSPICLM tSPICHM
tHDSPIDM
tHSPIDM
tSSPIDM
SPI_SEL
(OUTPUT)
SPI_CLK
(OUTPUT)
DATA OUTPUTS
(SPI_MOSI)
CPHA = 1
CPHA = 0
tDDSPIDM
tHSPIDM
tSSPIDM
tHDSPIDM
tDDSPIDM
DATA INPUTS
(SPI_MISO)
DATA OUTPUTS
(SPI_MOSI)
DATA INPUTS
(SPI_MISO)
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Serial Peripheral Interface (SPI) Port—Slave Timing
Table 54 and Figure 31 describe serial peripheral interface (SPI) port slave operations. Note that:
• In dual mode data transmit, the SPI_MOSI signal is also an output.
• In quad mode data transmit, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs.
• In dual mode data receive, the SPI_MISO signal is also an input.
• In quad mode data receive, the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called f
SPICLKEXT
:
Table 54. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
MinMaxMinMaxUnit
Timing Requirements
t
SPICHS
SPI_CLK High Period
1
1
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external
SPI_CLK ideal maximum frequency see the f
SPICLKTEXT
specification in Table 18 of Clock Related Operating Conditions.
(0.5 × t
SPICLKEXT
) – 1.5 (0.5 × t
SPICLKEXT
) – 1.5 ns
t
SPICLS
SPI_CLK Low Period
1
(0.5 × t
SPICLKEXT
) – 1.5 (0.5 × t
SPICLKEXT
) – 1.5 ns
t
SPICLK
SPI_CLK Period
1
t
SPICLKEXT
– 1.5 t
SPICLKEXT
– 1.5 ns
t
HDS
Last SPI_CLK Edge to SPI_SS Not Asserted
(NonSPIHP)
55ns
t
HDS
Last SPI_CLK Edge to SPI_SS Not Asserted
(Using SPIHP)
1.5 × t
SCLK0
1.5 × t
SCLK0
ns
t
SPITDS
Sequential Transfer Delay (NonSPIHP) 0.5 × t
SPICLK
– 1.5 0.5 × t
SPICLK
– 1.5 ns
t
SPITDS
Sequential Transfer Delay (Using SPIHP) 3 × t
SCLK0
3 × t
SCLK0
ns
t
SDSCI
SPI_SS Assertion to First SPI_CLK Edge 11.5 11.5 ns
t
SSPID
Data Input Valid to SPI_CLK Edge (Data Input
Setup)
1.5 1 ns
t
HSPID
SPI_CLK Sampling Edge to Data Input Invalid 3.3 3 ns
Switching Characteristics
t
DSOE
SPI_SS Assertion to Data Out Active 0 17.5 0 14.5 ns
t
DSDHI
SPI_SS Deassertion to Data High Impedance 0 13 0 11.5 ns
t
DDSPID
SPI_CLK Edge to Data Out Valid (Data Out Delay) 17.5 14.5 ns
t
HDSPID
SPI_CLK Edge to Data Out Invalid (Data Out Hold) 2.5 2.5 ns
tSPICLKEXT
1
fSPICLKEXT
-----------------------------=
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Figure 31. Serial Peripheral Interface (SPI) Port—Slave Timing
tSPICLK tHDS tSPITDS
tSDSCI tSPICLS tSPICHS
tDSOE tDDSPID
tDDSPID tDSDHI
tHDSPID
tSSPID
tDSDHI
tHDSPID
tDSOE
tHSPID
tSSPID
tDDSPID
SPI_SS
(INPUT)
SPI_CLK
(INPUT)
tHSPID
DATA OUTPUTS
(SPI_MISO)
CPHA = 1
CPHA = 0
DATA INPUTS
(SPI_MOSI)
DATA OUTPUTS
(SPI_MISO)
DATA INPUTS
(SPI_MOSI)
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Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
Table 55. SPI Port—SPI_RDY Slave Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
DSPISCKRDYSR
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × t
SCLK0
+ t
HDSPID
3.5 × t
SCLK0
+ t
DDSPID
ns
t
DSPISCKRDYST
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × t
SCLK0
+ t
HDSPID
4.5 × t
SCLK0
+ t
DDSPID
ns
Figure 32. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0)
Figure 33. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1)
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
tDSPISCKRDYSR
SPI_RDY (O)
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
CPHA = 1
CPHA = 0
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
tDSPISCKRDYST
SPI_RDY (O)
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
CPHA = 1
CPHA = 0
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Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing
In Figure 34 and Figure 35, the outputs can be SPI_MOSI SPI_MISO, SPI_D2, and/or SPI_D3 depending on the mode of operation.
Table 56. SPI Port ODM Master Mode Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Switching Characteristics
t
HDSPIODMM
SPI_CLK Edge to High Impedance from Data Out Valid –4.5 –3.5 ns
t
DDSPIODMM
SPI_CLK Edge to Data Out Valid from High Impedance 2.5 2 ns
Figure 34. ODM Master
SPI_CLK
(CPOL = 0)
tHDSPIODMM
SPI_CLK
(CPOL = 1)
tDDSPIODMM tDDSPIODMM
tHDSPIODMM
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
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Table 57. SPI Port—ODM Slave Mode
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Switching Characteristics
t
HDSPIODMS
SPI_CLK Edge to High Impedance from Data Out Valid 2.5 2.5 ns
t
DDSPIODMS
SPI_CLK Edge to Data Out Valid from High Impedance 17.5 14.5 ns
Figure 35. ODM Slave
tHDSPIODMS
tDDSPIODMS tDDSPIODMS
tHDSPIODMS
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
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Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
SPI_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in
SPI_DLY.
Table 58. SPI Port—SPI_RDY Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SRDYSCKM0
Minimum Setup Time for SPI_RDY De-assertion in
Master Mode Before Last SPI_CLK Edge of Valid
Data Transfer to Block Subsequent Transfer with
CPHA = 0
(2.5 + 1.5 × BAUD
1
) × t
SCLK0
+ 14.5
1
BAUD value set using the SPI_CLK.BAUD bits.
ns
t
SRDYSCKM1
Minimum Setup Time for SPI_RDY De-assertion in
Master Mode Before Last SPI_CLK Edge of Valid
Data Transfer to Block Subsequent Transfer with
CPHA = 1
(2.5 + BAUD
1
) × t
SCLK0
+ 14.5 ns
Switching Characteristic
t
SRDYSCKM
Time Between Assertion of SPI_RDY by Slave and
First Edge of SPI_CLK for New SPI Transfer with
CPHA = 0 and BAUD = 0 (STOP, LEADX, LAGX = 0)
3 × t
SCLK0
4 × t
SCLK0
+ 17.5 ns
Time Between Assertion of SPI_RDY by Slave and
First Edge of SPI_CLK for New SPI Transfer with
CPHA = 0 and BAUD ≥ 1 (STOP, LEADX, LAGX = 0)
(4 + 1.5 × BAUD
1
) × t
SCLK0
(5 + 1.5 × BAUD
1
) × t
SCLK0
+ 17.5 ns
Time Between Assertion of SPI_RDY by Slave and
First Edge of SPI_CLK for New SPI Transfer with
CPHA = 1 (STOP, LEADX, LAGX = 0)
(3 + 0.5 × BAUD
1
) × t
SCLK0
(4 + 0.5 × BAUD
1
) × t
SCLK0
+ 17.5 ns
Figure 36. SPI_RDY Setup Before SPI_CLK with CPHA = 0
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
tSRDYSCKM0
SPI_RDY
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Figure 37. SPI_RDY Setup Before SPI_CLK with CPHA = 1
Figure 38. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
tSRDYSCKM1
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM
SPI_RDY
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Enhanced Parallel Peripheral Interface Timing
The following tables and figures describe enhanced parallel peripheral interface timing operations. The POLC bits in the EPPI_CTL
register may be used to set the sampling/driving edges of the EPPI clock.
When internally generated, the programmed PPI clock (f
PCLKPROG
) frequency in MHz is set by the following equation where VALUE is a
field in the EPPI_CLKDIV register that can be set from 0 to 65,535:
When externally generated the EPPI_CLK is called f
PCLKEXT
:
Table 59. Enhanced Parallel Peripheral Interface—Internal Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSPI
External FS Setup Before EPPI_CLK 6.5 5 ns
t
HFSPI
External FS Hold After EPPI_CLK 1.5 1 ns
t
SDRPI
Receive Data Setup Before EPPI_CLK 6.4 5 ns
t
HDRPI
Receive Data Hold After EPPI_CLK 1 1 ns
t
SFS3GI
External FS3 Input Setup Before EPPI_CLK
Fall Edge in Clock Gating Mode
16.5 14 ns
t
HFS3GI
External FS3 Input Hold Before EPPI_CLK
Fall Edge in Clock Gating Mode
1.5 0 ns
Switching Characteristics
t
PCLKW
EPPI_CLK Width
1
1
See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t
PCLKPROG
.
0.5 × t
PCLKPROG
– 2 0.5 × t
PCLKPROG
– 2 ns
t
PCLK
EPPI_CLK Period
1
t
PCLKPROG
– 2 t
PCLKPROG
– 2 ns
t
DFSPI
Internal FS Delay After EPPI_CLK 2 2 ns
t
HOFSPI
Internal FS Hold After EPPI_CLK –4 –3 ns
t
DDTPI
Transmit Data Delay After EPPI_CLK 2 2 ns
t
HDTPI
Transmit Data Hold After EPPI_CLK –4 –3 ns
fPCLKPROG
fSCLK0
VALUE 1+
--------------------------=
tPCLKPROG
1
fPCLKPROG
-------------------------=
tPCLKEXT
1
fPCLKEXT
---------------------=
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Figure 39. PPI Internal Clock GP Receive Mode with Internal Frame Sync Timing
Figure 40. PPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing
Figure 41. PPI Internal Clock GP Receive Mode with External Frame Sync Timing
tHDRPI
tSDRPI
tHOFSPI
FRAME SYNC
DRIVEN
DATA
SAMPLED
tDFSPI
tPCLK
tPCLKW
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 10
POLC[1:0] = 01
tHOFSPI
FRAME SYNC
DRIVEN
DATA
DRIVEN
tDFSPI
tDDTPI tHDTPI
tPCLK
tPCLKW
DATA
DRIVEN
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
tPCLK
tSFSPI
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
EPPI_Dx
EPPI_FS1/2
tHFSPI
tHDRPI
tSDRPI
tPCLKW
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
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Figure 42. PPI Internal Clock GP Transmit Mode with External Frame Sync Timing
Figure 43. Clock Gating Mode with Internal Clock and External Frame Sync Timing
tHDTPI
tSFSPI
DATA DRIVEN /
FRAME SYNC SAMPLED
tHFSPI
tDDTPI
tPCLK
tPCLKW
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
EPPI_CLK
tSFS3GI
EPPI_FS3
tHFS3GI
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Table 60. Enhanced Parallel Peripheral Interface—External Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
PCLKW
EPPI_CLK Width
1
(0.5 × t
PCLKEXT
) – 1 (0.5 × t
PCLKEXT
) – 1 ns
t
PCLK
EPPI_CLK Period
1
t
PCLKEXT
– 1 t
PCLKEXT
– 1 ns
t
SFSPE
External FS Setup Before EPPI_CLK 1.5 1 ns
t
HFSPE
External FS Hold After EPPI_CLK 3.3 3 ns
t
SDRPE
Receive Data Setup Before EPPI_CLK 1 1 ns
t
HDRPE
Receive Data Hold After EPPI_CLK 3 3 ns
Switching Characteristics
t
DFSPE
Internal FS Delay After EPPI_CLK 17.5 14.5 ns
t
HOFSPE
Internal FS Hold After EPPI_CLK 2.5 2.5 ns
t
DDTPE
Transmit Data Delay After EPPI_CLK 17.5 14.5 ns
t
HDTPE
Transmit Data Hold After EPPI_CLK 2.5 2.5 ns
1
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency, see the f
PCLKEXT
specification in Table 18 in Clock Related Operating Conditions.
Figure 44. PPI External Clock GP Receive Mode with Internal Frame Sync Timing
Figure 45. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
tDFSPE
tPCLK
tPCLKW
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 10
POLC[1:0] = 01
tHOFSPE
FRAME SYNC
DRIVEN
DATA
DRIVEN
tDFSPE
tDDTPE tHDTPE
tPCLK
tPCLKW
DATA
DRIVEN
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
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Figure 46. PPI External Clock GP Receive Mode with External Frame Sync Timing
Figure 47. PPI External Clock GP Transmit Mode with External Frame Sync Timing
tPCLK
tSFSPE
DATA SAMPLED/
FRAME SYNC SAMPLED
DATA SAMPLED/
FRAME SYNC SAMPLED
EPPI_Dx
EPPI_FS1/2
tHFSPE
tHDRPE
tSDRPE
tPCLKW
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
tHDTPE
tSFSPE
DATA DRIVEN/
FRAME SYNC SAMPLED
tHFSPE
tDDTPE
tPCLK
tPCLKW
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00
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Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The universal asynchronous receiver-transmitter (UART) ports receive and transmit operations are described in the ADSP-BF70x
Blackfin+ Processor Hardware Reference.
Controller Area Network (CAN) Interface
The controller area network (CAN) interface timing is described in the ADSP-BF70x Blackfin+ Processor Hardware Reference.
Universal Serial Bus (USB)
Table 61 describes the universal serial bus (USB) clock timing. Refer to the USB 2.0 Specification for timing and dc specifications for USB
pins (including output characteristics for driver types E, F, and G listed in the ADSP-BF70x Designer Quick Reference).
Table 61. USB Clock Timing
Parameter
V
DD_EXT
3.3 V Nominal
Min Max Unit
Timing Requirements
f
USBS
USB_CLKIN Frequency 24 24 MHz
fs
USB
USB_CLKIN Clock Frequency Stability –50 +50 ppm
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Mobile Storage Interface (MSI) Controller Timing
Table 63 and Figure 48 show I/O timing, related to the mobile storage interface (MSI).
The MSI timing depends on the period of the input clock that has been routed to the MSI peripheral (t
MSICLKIN
) by setting the
MSI0_UHS_EXT register. See Table 62 for this information.
(f
MSICLKPROG
) frequency in MHz is set by the following equation where DIV0 is a field in the MSI_CLKDIV register that can be set from 0 to
255. When DIV0 is set between 1 and 255, the following equation is used to determine f
MSICLKPROG
:
When DIV0 = 0,
Also note the following:
Table 62. t
MSICLKIN
Settings
EXT_CLK_MUX_CTRL[31:30] t
MSICLKIN
00 t
SCLK0
× 2
01 t
SCLK0
10 t
SCLK1
× 3
Table 63. MSI Controller Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
ISU
Input Setup Time 5.5 4.7 ns
t
IH
Input Hold Time 2 0.5 ns
Switching Characteristics
t
MSICLK
Clock Period Data Transfer Mode
1
1
See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for t
MSICLKPROG
.
t
MSICLKPROG
– 1.5 t
MSICLKPROG
– 1.5 ns
t
WL
Clock Low Time 7 7 ns
t
WH
Clock High Time 7 7 ns
t
TLH
Clock Rise Time 3 3 ns
t
THL
Clock Fall Time 3 3 ns
t
ODLY
Output Delay Time During Data Transfer Mode (0.5 × t
MSICLKIN
) + 3.2 (0.5 × t
MSICLKIN
) + 3 ns
t
OH
Output Hold Time (0.5 × t
MSICLKIN
) – 4 (0.5 × t
MSICLKIN
) – 3 ns
tMSICLKIN
1
fMSICLKIN
-----------------------=
fMSICLKPROG
fMSICLKIN
DIV0 2
-------------------------=
fMSICLKPROG fMSICLKIN
=
tMSICLKPROG
1
fMSICLKPROG
------------------------------=
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OUTPUT DRIVE CURRENTS
Figure 49 through Figure 60 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF70x Blackfin
processors. The curves represent the current drive capability of
the output drivers as a function of output voltage.
Figure 49. Driver Type A Current (1.8 V V
DD_EXT
)
Figure 50. Driver Type A Current (3.3 V V
DD_EXT
)
VOH
VOL
25
15
5
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
–5
–15
20
10
0
–10
–20
–30
–25
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD_EXT = 1.9V @ –40°C
VDD_EXT = 1.8V @ 25°C
VDD_EXT = 1.7V @ 125°C
VDD_EXT = 1.9V @ –40°C
VDD_EXT = 1.8V @ 25°C
VDD_EXT = 1.7V @ 125°C
VOH
VOL
60
40
20
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0
–20
–40
–60
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD_EXT = 3.47V @ –40°C
VDD_EXT = 3.30V @ 25°C
VDD_EXT = 3.13V @ 125°C
VDD_EXT = 3.47V @ –40°C
VDD_EXT = 3.30V @ 25°C
VDD_EXT = 3.13V @ 125°C
Figure 51. Driver Type D Current (1.8 V V
DD_EXT
)
Figure 52. Driver Type D Current (3.3 V V
DD_EXT
)
Figure 53. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω)
VOL
0
–4
–8
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
–12
–2
–6
–10
–14
–16
0 0.5 1.0 1.5 2.0 2.5
VDD_EXT = 1.9V @ –40°C
VDD_EXT = 1.8V @ 25°C
VDD_EXT = 1.7V @ 125°C
VOL
5
–5
–15
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
–25
–35
0
–10
–20
–30
–40
–50
–45
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD_EXT = 3.47V @ –40°C
VDD_EXT = 3.30V @ 25°C
VDD_EXT = 3.13V @ 125°C
–35
–30
–25
–20
–15
–10
–5
0
5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOL
Rev. D | Page 101 of 114 | February 2019
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Figure 54. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω)
Figure 55. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω)
Figure 56. Driver Type B and Driver Type C (DDR Drive Strength 60 Ω)
–30
–25
–20
–15
–10
–5
0
5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOL
–25
–20
–15
–10
–5
0
5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOL
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
@ –4 0°C
@ 25°C
D
V
D_DMC
= 1.7V @ 125°C
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
V
D
V
D_DMC
= 1.8
V
D
V
D_DMC
= 1.9
V
OL
Figure 57. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω)
Figure 58. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω)
Figure 59. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω)
0
5
10
15
20
25
30
35
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOH
0
5
10
15
20
25
30
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOH
0
5
10
15
20
25
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
VOH
Rev. D | Page 102 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 61
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point, V
MEAS
, is V
DD_EXT
/2
for V
DD_EXT
(nominal) = 1.8 V/3.3 V.
Output Enable Time Measurement
Output pins are considered enabled when they make a transi-
tion from a high impedance state to the point when they start
driving.
The output enable time, t
ENA
, is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving, as shown on the right side of
Figure 62. If multiple pins are enabled, the measurement value
is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, t
DIS
, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 62.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 63). V
LOAD
is equal
to V
DD_EXT
/2.
Figure 60. Driver Type B and Device Driver C (DDR Drive Strength 60 Ω)
Figure 61. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
VDD_DMC = 1.9V @ –40°C
VDD_DMC = 1.8V @ 25°C
VDD_DMC = 1.7V @ 125°C
0
2
4
6
8
10
12
14
16
18
20
VOH
INPUT
OR
OUTPUT
V
MEAS
V
MEAS
Figure 62. Output Enable/Disable
Figure 63. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
tENA
T1
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50:
0.5pF
70:
400:
45:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50:
Rev. D | Page 103 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Figure 64 through Figure 67 show how output rise time varies
with capacitance. The delay and hold specifications given must
be derated by a factor derived from these figures. The graphs in
these figures may not be linear outside the ranges shown.
Figure 64. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
DD_EXT
= 1.8 V)
Figure 65. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
DD_EXT
= 3.3 V)
40
0
5
10
15
20
25
30
35
0 50 100 150 200 250
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25°C
35
0
5
10
15
20
25
30
0 50 100 150 200
250
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
tRISE = 3.3V @ 25°C
tFALL = 3.3V @ 25°C
Figure 66. Driver Type B & C Typical Rise and Fall Times (10% to 90%)
vs. Load Capacitance (V
DD_DMC
= 1.8 V)
Figure 67. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance (V
DD_DMC
= 1.8 V) for LPDDR
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0246810
12
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 2 4 6 8 10 12
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25°C
Rev. D | Page 104 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board, use the following equation:
where:
T
J
= junction temperature (°C).
T
CASE
= case temperature (°C) measured by customer at top
center of package.
JT
= from Table 64 and Table 65.
P
D
= power dissipation (see Total Internal Power Dissipation
section for the method to calculate P
D
).
Values of
JA
are provided for package comparison and printed
circuit board design considerations.
JA
can be used for a first-
order approximation of T
J
by the following equation:
where:
T
A
= ambient temperature (°C).
Values of
JC
are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
In Table 64 and Table 65, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6. The junction-to-
case measurement complies with MIL-STD-883 (Method
1012.1). All measurements use a 2S2P JEDEC test board.
Table 64. Thermal Characteristics for CSP_BGA
Parameter Condition Typical Unit
JA
0 linear m/s air flow 28.7 °C/W
JMA
1 linear m/s air flow 26.2 °C/W
JMA
2 linear m/s air flow 25.2 °C/W
JC
10.1 °C/W
JT
0 linear m/s air flow 0.24 °C/W
JT
1 linear m/s air flow 0.40 °C/W
JT
2 linear m/s air flow 0.51 °C/W
Table 65. Thermal Characteristics for LFCSP (QFN)
Parameter Condition Typical Unit
JA
0 linear m/s air flow 22.9 °C/W
JMA
1 linear m/s air flow 17.9 °C/W
JMA
2 linear m/s air flow 16.4 °C/W
JC
2.26 °C/W
JT
0 linear m/s air flow 0.14 °C/W
JT
1 linear m/s air flow 0.27 °C/W
JT
2 linear m/s air flow 0.30 °C/W
TJTCASE JT PD
+=
TJTAJA PD
+=
Rev. D | Page 105 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF70x 184-BALL CSP_BGA BALL ASSIGNMENTS
(NUMERICAL BY BALL NUMBER)
Figure 68 shows an overview of signal placement on the
184-ball CSP_BGA.
Table 66 lists the 184-ball CSP_BGA package by ball number for
the ADSP-BF70x. Table 67 lists the 184-ball CSP_BGA package
by signal.
Figure 68. 184-Ball CSP_BGA Configuration
BOTTOM VIEW
TOP VIEW
GND
VDD_INT
VDD_EXT
I/O SIGNALS
DVDD_DMC
OVDD_OTP
HVDD_HADC
RVDD_RTC
UVDD_USB
GND_HADC
H
A1 BALL
CORNER
3
4
5
6
7
8
9
10
11
12
13
14
1
2
A
M
B
D
F
H
K
P
C
E
G
J
L
N
U
DDDD
DDDD
DD
D
D
H
OR
H
U
DDDD
DDDD
DD
D
D
H
O
R
A
M
B
D
F
H
K
P
C
E
G
J
L
N
8
3
4
5
6
79
10
11
12
13
14
1
2
A1 BALL
CORNER
H
Rev. D | Page 106 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 66. 184-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
A01 GND D08 VDD_DMC H03 SYS_CLKOUT L14 GND
A02 DMC0_A09 D09 VDD_DMC H04 VDD_INT M01 PC_00
A03 DMC0_BA0 D12 PA_08 H05 GND M02 RTC0_CLKIN
A04 DMC0_BA1 D13 DMC0_DQ06 H06 GND M03 PB_15
A05 DMC0_BA2 D14 DMC0_DQ05 H07 GND M04 PB_12
A06 DMC0_CAS E01 DMC0_A06 H08 GND M05 PC_12
A07 DMC0_RAS E02 DMC0_A05 H09 GND M06 USB0_VBUS
A08 DMC0_A13 E03 JTG_TDI H10 GND M07 USB0_VBC
A09 PA_03 E05 VDD_INT H11 VDD_DMC M08 PB_09
A10 DMC0_CK E06 VDD_DMC H12 PA_10 M09 PB_05
A11 DMC0_CK E07 VDD_DMC H13 PA_11 M10 PB_04
A12 DMC0_LDQS E08 VDD_DMC H14 DMC0_UDQS M11 PB_01
A13 DMC0_LDQS E09 VDD_DMC J01 PC_05 M12 PB_03
A14 GND E10 DMC0_VREF J02 PC_06 M13 DMC0_LDM
B01 DMC0_A07 E12 SYS_BMODE0 J03 SYS_RESOUT M14 SYS_CLKIN
B02 DMC0_A08 E13 DMC0_DQ08 J04 VDD_INT N01 RTC0_XTAL
B03 DMC0_A11 E14 DMC0_DQ07 J05 VDD_RTC N02 PB_14
B04 DMC0_A10 F01 DMC0_A01 J06 GND N03 PB_11
B05 DMC0_A12 F02 DMC0_A02 J07 GND N04 PC_14
B06 DMC0_WE F03 PC_09 J08 GND N05 PC_11
B07 DMC0_CS0 F04 VDD_INT J09 GND N06 USB0_ID
B08 DMC0_ODT F05 VDD_INT J10 GND_HADC N07 USB0_DP
B09 DMC0_CKE F06 GND J11 VDD_OTP N08 PB_08
B10 DMC0_DQ00 F07 GND J12 PA_13 N09 PB_06
B11 DMC0_DQ02 F08 GND J13 DMC0_DQ13 N10 PB_00
B12 DMC0_DQ01 F09 GND J14 DMC0_UDQS N11 HADC0_VIN2
B13 DMC0_DQ04 F10 VDD_DMC K01 PC_04 N12 HADC0_VIN1
B14 DMC0_DQ03 F11 VDD_DMC K02 PC_01 N13 PA_15
C01 JTG_TDO_SWO F12 SYS_FAULT K03 PC_02 N14 SYS_XTAL
C02 JTG_TMS_SWDIO F13 DMC0_DQ10 K05 VDD_EXT P01 GND
C03 JTG_TCK_SWCLK F14 DMC0_DQ09 K06 VDD_EXT P02 PB_13
C04 PA_01 G01 DMC0_A03 K07 VDD_EXT P03 PB_10
C05 SYS_EXTWAKE G02 PA_00 K08 VDD_EXT P04 PC_13
C06 PA_02 G03 PC_08 K09 VDD_EXT P05 USB0_XTAL
C07 SYS_NMI G04 VDD_INT K10 VDD_HADC P06 USB0_CLKIN
C08 GND G05 GND K12 PA_12 P07 USB0_DM
C09 PA_04 G06 GND K13 DMC0_DQ15 P08 PB_07
C10 PA_05 G07 GND K14 DMC0_DQ14 P09 HADC0_VREFN
C11 PA_06 G08 GND L01 PC_03 P10 HADC0_VREFP
C12 PA_07 G09 GND L02 TWI0_SDA P11 HADC0_VIN3
C13 SYS_HWRST G10 GND L03 TWI0_SCL P12 HADC0_VIN0
C14 SYS_BMODE1 G11 VDD_DMC L06 VDD_USB P13 PA_14
D01 DMC0_A00 G12 PA_09 L07 VDD_EXT P14 GND
D02 DMC0_A04 G13 DMC0_DQ11 L08 VDD_EXT
D03 JTG_TRST G14 DMC0_DQ12 L09 VDD_EXT
D06 VDD_DMC H01 PC_07 L12 PB_02
D07 VDD_DMC H02 PC_10 L13 DMC0_UDM
Rev. D | Page 107 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 67. ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Alphabetical by Signal Name)
Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
DMC0_A00 D01 DMC0_WE B06 PA_08 D12 SYS_HWRST C13
DMC0_A01 F01 GND C08 PA_09 G12 SYS_NMI C07
DMC0_A02 F02 GND A01 PA_10 H12 SYS_RESOUT J03
DMC0_A03 G01 GND A14 PA_11 H13 SYS_XTAL N14
DMC0_A04 D02 GND F06 PA_12 K12 TWI0_SCL L03
DMC0_A05 E02 GND F07 PA_13 J12 TWI0_SDA L02
DMC0_A06 E01 GND F08 PA_14 P13 USB0_CLKIN P06
DMC0_A07 B01 GND F09 PA_15 N13 USB0_DM P07
DMC0_A08 B02 GND G05 PB_00 N10 USB0_DP N07
DMC0_A09 A02 GND G06 PB_01 M11 USB0_ID N06
DMC0_A10 B04 GND G07 PB_02 L12 USB0_VBC M07
DMC0_A11 B03 GND G08 PB_03 M12 USB0_VBUS M06
DMC0_A12 B05 GND G09 PB_04 M10 USB0_XTAL P05
DMC0_A13 A08 GND G10 PB_05 M09 VDD_DMC D06
DMC0_BA0 A03 GND H05 PB_06 N09 VDD_DMC D07
DMC0_BA1 A04 GND H06 PB_07 P08 VDD_DMC D08
DMC0_BA2 A05 GND H07 PB_08 N08 VDD_DMC D09
DMC0_CAS A06 GND H08 PB_09 M08 VDD_DMC E06
DMC0_CK A10 GND H09 PB_10 P03 VDD_DMC E07
DMC0_CKE B09 GND H10 PB_11 N03 VDD_DMC E08
DMC0_CK A11 GND J06 PB_12 M04 VDD_DMC E09
DMC0_CS0 B07 GND J07 PB_13 P02 VDD_DMC F10
DMC0_DQ00 B10 GND J08 PB_14 N02 VDD_DMC F11
DMC0_DQ01 B12 GND J09 PB_15 M03 VDD_DMC G11
DMC0_DQ02 B11 GND L14 PC_00 M01 VDD_DMC H11
DMC0_DQ03 B14 GND P01 PC_01 K02 VDD_EXT K05
DMC0_DQ04 B13 GND P14 PC_02 K03 VDD_EXT K06
DMC0_DQ05 D14 GND_HADC J10 PC_03 L01 VDD_EXT K07
DMC0_DQ06 D13 HADC0_VIN0 P12 PC_04 K01 VDD_EXT K08
DMC0_DQ07 E14 HADC0_VIN1 N12 PC_05 J01 VDD_EXT K09
DMC0_DQ08 E13 HADC0_VIN2 N11 PC_06 J02 VDD_EXT L07
DMC0_DQ09 F14 HADC0_VIN3 P11 PC_07 H01 VDD_EXT L08
DMC0_DQ10 F13 HADC0_VREFN P09 PC_08 G03 VDD_EXT L09
DMC0_DQ11 G13 HADC0_VREFP P10 PC_09 F03 VDD_HADC K10
DMC0_DQ12 G14 JTG_TCK_SWCLK C03 PC_10 H02 VDD_INT E05
DMC0_DQ13 J13 JTG_TDI E03 PC_11 N05 VDD_INT F04
DMC0_DQ14 K14 JTG_TDO_SWO C01 PC_12 M05 VDD_INT F05
DMC0_DQ15 K13 JTG_TMS_SWDIO C02 PC_13 P04 VDD_INT G04
DMC0_LDM M13 JTG_TRST D03 PC_14 N04 VDD_INT H04
DMC0_LDQS A12 PA_00 G02 RTC0_CLKIN M02 VDD_INT J04
DMC0_LDQS A13 PA_01 C04 RTC0_XTAL N01 VDD_OTP J11
DMC0_ODT B08 PA_02 C06 SYS_BMODE0 E12 VDD_RTC J05
DMC0_RAS A07 PA_03 A09 SYS_BMODE1 C14 VDD_USB L06
DMC0_UDM L13 PA_04 C09 SYS_CLKIN M14
DMC0_UDQS J14 PA_05 C10 SYS_CLKOUT H03
DMC0_UDQS H14 PA_06 C11 SYS_EXTWAKE C05
DMC0_VREF E10 PA_07 C12 SYS_FAULT F12
Rev. D | Page 108 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
ADSP-BF70x 12 mm × 12 mm 88-LEAD LFCSP (QFN) LEAD ASSIGNMENTS
(NUMERICAL BY LEAD NUMBER)
Figure 69 shows an overview of signal placement on the12 mm
× 12 mm 88-lead LFCSP (QFN).
Figure 69. 12 mm × 12 mm 88-Lead LFCSP (QFN) Configuration
PIN 1
INDICATOR
PIN 1
PIN 22
PIN 66
PIN 45
PIN 23
PIN 44
PIN 88
PIN 67
GND PAD
(PIN 89)
PIN 1
INDICATOR
PIN 1
PIN 22
PIN 23 PIN 44
PIN 45
PIN 66
PIN 67
PIN 88
ADSP-BF70x
88-LEAD LFCSP (QFN)
TOP VIEW
BOTTOM VIEW
Rev. D | Page 109 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 68 lists the 12 mm × 12 mm 88-Lead LFCSP (QFN) pack-
age by lead number for the ADSP-BF70x. Table 69 lists the
12 mm ×12 mm 88-Lead LFCSP (QFN) package by signal.
Table 68. 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignment (Numerical by Lead Number)
Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name
1 PC_10 24 PB_14 47 PB_02 70 PA_07
2 PC_09 25 PB_13 48 PB_01 71 PA_06
3 PC_08 26 VDD_EXT 49 VDD_OTP 72 VDD_EXT
4 VDD_EXT 27 PB_12 50 VDD_EXT 73 PA_05
5 PC_07 28 PB_11 51 VDD_INT 74 PA_04
6 PC_06 29 PB_10 52 PB_00 75 PA_03
7 PC_05 30 VDD_INT 53 PA_15 76 GND
8 PC_04 31 USB0_XTAL 54 PA_14 77 SYS_NMI
9 PC_03 32 USB0_CLKIN 55 VDD_EXT 78 PA_02
10 PC_02 33 USB0_ID 56 SYS_XTAL 79 SYS_EXTWAKE
11 VDD_EXT 34 USB0_VBUS 57 SYS_CLKIN 80 PA_01
12 SYS_CLKOUT 35 USB0_DP 58 PA_13 81 VDD_INT
13 PC_01 36 VDD_USB 59 PA_12 82 VDD_EXT
14 VDD_INT 37 USB0_DM 60 PA_11 83 JTG_TDO_SWO
15 SYS_RESOUT 38 USB0_VBC 61 VDD_INT84JTG_TMS_SWDIO
16 PC_00 39 PB_09 62 VDD_EXT 85 JTG_TCK_SWCLK
17 VDD_EXT 40 PB_08 63 PA_10 86 JTG_TDI
18 TWI0_SDA 41 VDD_EXT 64 PA_09 87 JTG_TRST
19 TWI0_SCL 42 PB_07 65 SYS_FAULT 88 PA_00
20 RTC0_XTAL 43 PB_06 66 SYS_BMODE0 89* GND
21 RTC0_CLKIN 44 PB_05 67 SYS_BMODE1
22 VDD_RTC 45 PB_04 68 SYS_HWRST
23 PB_15 46 PB_03 69 PA_08
*Pin no. 89 is the GND supply (see Figure 69) for the processor; this pad must connect to GND.
Rev. D | Page 110 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Table 69. ADSP-BF70x 12 mm × 12 mm 88 -Lead LFCSP (QFN) Lead Assignments (Alphabetical by Signal Name)
Signal Name Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name Lead No.
GND 76 PB_00 52 PC_07 5 USB0_VBUS 34
GND 89 PB_01 48 PC_08 3 USB0_XTAL 31
JTG_TCK_SWCLK 85 PB_02 47 PC_09 2 VDD_EXT 4
JTG_TDI 86 PB_03 46 PC_10 1 VDD_EXT 11
JTG_TDO_SWO 83 PB_04 45 RTC0_CLKIN 21 VDD_EXT 17
JTG_TMS_SWDIO 84 PB_05 44 RTC0_XTAL 20 VDD_EXT 26
JTG_TRST 87 PB_06 43 SYS_BMODE0 66 VDD_EXT 41
PA_00 88 PB_07 42 SYS_BMODE1 67 VDD_EXT 50
PA_01 80 PB_08 40 SYS_CLKIN 57 VDD_EXT 55
PA_02 78 PB_09 39 SYS_CLKOUT 12 VDD_EXT 62
PA_03 75 PB_10 29 SYS_EXTWAKE 79 VDD_EXT 72
PA_04 74 PB_11 28 SYS_FAULT 65 VDD_EXT 82
PA_05 73 PB_12 27 SYS_HWRST 68 VDD_INT 14
PA_06 71 PB_13 25 SYS_NMI 77 VDD_INT 30
PA_07 70 PB_14 24 SYS_RESOUT 15 VDD_INT 51
PA_08 69 PB_15 23 SYS_XTAL 56 VDD_INT 61
PA_09 64 PC_00 16 TWI0_SCL 19 VDD_INT 81
PA_10 63 PC_01 13 TWI0_SDA 18 VDD_OTP 49
PA_11 60 PC_02 10 USB0_CLKIN 32 VDD_RTC 22
PA_12 59 PC_03 9 USB0_DM 37 VDD_USB 36
PA_13 58 PC_04 8 USB0_DP 35
PA_14 54 PC_05 7 USB0_ID 33
PA_15 53 PC_06 6 USB0_VBC 38
Rev. D | Page 111 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
OUTLINE DIMENSIONS
Dimensions for the 12 mm × 12 mm CSP_BGA package in
Figure 70 are shown in millimeters.
Figure 70. 184-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-184-1)
Dimensions shown in millimeters
0.80
BSC
10.40
REF SQ
12.10
12.00 SQ
11.90
COMPLIANT TO JEDEC STANDARDS MO-275-GGAA-1
0.80
REF
A
B
C
D
E
F
G
9
10 8
11
12
13
14 75
642
31
BOTTOM VIEW
H
J
K
L
M
N
P
DETAIL A
TOP VIEW
DETAIL A
COPLANARITY
0.12
0.50
0.45
0.40
BALL DIAMETER
SEATING
PLANE
A1 BALL
CORNER
A1 BALL
CORNER
1.29
1.19
1.09
1.70
1.54
1.39
0.39
0.35
0.30
Rev. D | Page 112 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
Dimensions for the 12 mm × 12 mm LFCSP_VQ package in Figure 71 are shown in millimeters.
SURFACE-MOUNT DESIGN
Table 70 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for
Surface-Mount Design and Land Pattern Standard.
Figure 71. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
(CP-88-8)
Dimensions shown in millimeters
Table 70. CSP_BGA Data for Use with Surface-Mount Design
Package
Package
Ball Attach Type
Package
Solder Mask Opening
Package
Ball Pad Size
BC-184-1 Solder Mask Defined 0.4 mm Diameter 0.5 mm Diameter
COMPLIANT TO JEDEC STANDARDS MO-220
1
22
66
45
23
44
88
67
0.50
0.40
0.30
0.28
0.23
0.18
10.50
REF
0.60 MAX
0.60
MAX
6.00
5.90 SQ
5.80
0.50
BSC
0.190~0.245 REF
12° MAX
SEATING
PLANE
PIN 1
INDICATOR
0.70
0.65
0.60 0.045
0.025
0.005
PIN 1
INDICATOR
TOP VIEW
0.90
0.85
0.80
EXPOSED
PAD
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
12.10
12.00 SQ
11.90
11.85
11.75 SQ
11.65
Rev. D | Page 113 of 114 | February 2019
ADSP-BF700/701/702/703/704/705/706/707
AUTOMOTIVE PRODUCTS
The following models are available with controlled manufactur-
ing to support the quality and reliability requirements of
automotive applications. Note that these automotive models
may have specifications that differ from the nonautomotive
models; therefore designers should review the Specifications
section of this data sheet carefully. Only the automotive grade
products shown in Table 71 are available for use in automotive
applications. Contact your local Analog Devices account repre-
sentative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these
models.
Table 71. Automotive Products
Model
1,
2,
3
Processor Instruction
Rate (Max) L2 SRAM
Temperature
Grade
4
Package Description
Package
Option
ADBF700WCCPZ2xx 200 MHz 128K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF701WCBCZ2xx 200 MHz 128K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF702WCCPZ3xx 300 MHz 256K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF702WCCPZ4xx 400 MHz 256K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF703WCBCZ3xx 300 MHz 256K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF703WCBCZ4xx 400 MHz 256K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF704WCCPZ3xx 300 MHz 512K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF704WCCPZ4xx 400 MHz 512K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF705WCBCZ3xx 300 MHz 512K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF705WCBCZ4xx 400 MHz 512K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF706WCCPZ3xx 300 MHz 1024K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF706WCCPZ4xx 400 MHz 1024K bytes –40°C to +105°C 88-Lead LFCSP_VQ CP-88-8
ADBF707WCBCZ3xx 300 MHz 1024K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
ADBF707WCBCZ4xx 400 MHz 1024K bytes –40°C to +105°C 184-Ball CSP_BGA BC-184-1
1
Select Automotive grade products, supporting –40°C to +105°C T
AMBIENT
condition, will be available when they appear in the Automotive Products table.
2
Z = RoHS Compliant Part.
3
xx denotes the current die revision.
4
Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions for the junction temperature (T
J
) specification
which is the only temperature specification.
Rev. D | Page 114 of 114 | February 2019
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12396-0-2/19(D)
ADSP-BF700/701/702/703/704/705/706/707
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ORDERING GUIDE
Model
1
1
Z = RoHS Compliant Part.
Processor Instruction
Rate (Max) L2 SRAM
Temperature
Grade
2
2
Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions for the junction temperature (T
J
) specification
which is the only temperature specification.
Package Description
Package
Option
ADSP-BF700KCPZ-1 100 MHz 128K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF700KCPZ-2 200 MHz 128K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF700BCPZ-2 200 MHz 128K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF701KBCZ-1 100 MHz 128K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF701KBCZ-2 200 MHz 128K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF701BBCZ-2 200 MHz 128K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF702KCPZ-3 300 MHz 256K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF702BCPZ-3 300 MHz 256K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF702KCPZ-4 400 MHz 256K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF702BCPZ-4 400 MHz 256K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF703KBCZ-3 300 MHz 256K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF703BBCZ-3 300 MHz 256K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF703KBCZ-4 400 MHz 256K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF703BBCZ-4 400 MHz 256K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF704KCPZ-3 300 MHz 512K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF704BCPZ-3 300 MHz 512K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF704KCPZ-4 400 MHz 512K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF704BCPZ-4 400 MHz 512K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF705KBCZ-3 300 MHz 512K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF705BBCZ-3 300 MHz 512K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF705KBCZ-4 400 MHz 512K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF705BBCZ-4 400 MHz 512K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF706KCPZ-3 300 MHz 1024K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF706BCPZ-3 300 MHz 1024K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF706KCPZ-4 400 MHz 1024K bytes 0°C to +70°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF706BCPZ-4 400 MHz 1024K bytes –40°C to +85°C 88-Lead LFCSP_VQ CP-88-8
ADSP-BF707KBCZ-3 300 MHz 1024K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF707BBCZ-3 300 MHz 1024K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
ADSP-BF707KBCZ-4 400 MHz 1024K bytes 0°C to +70°C 184-Ball CSP_BGA BC-184-1
ADSP-BF707BBCZ-4 400 MHz 1024K bytes –40°C to +85°C 184-Ball CSP_BGA BC-184-1
