LTC2874 Quad IO-Link Master Hot Swap Controller and PHY Description Features n n n n n n n n n n n n n n IO-Link(R) Compatible (COM1/COM2/COM3) 8V to 34V Operation Hot SwapTM Controller Protected Supply Outputs Discrete Power MOSFETs for Ruggedness and Flexibility Configurable 100mA (4-Port), 200mA (2-Port), or 400mA (1-Port) CQ Drive Capability Automatic Wake-Up Pulse Generation Automatic Cable Sensing CQ Pins Protected to 50V Configurable L+ Current Limit with Foldback Short Circuit, Input UV/OV and Thermal Protection Optional Interrupt and Auto-Retry after Faults 2.9V to 5.5V Logic Supply for Flexible Digital Interface No Damage or Latchup to 8kV HBM ESD 38-Lead (5mm x 7mm) QFN and TSSOP Packages Applications n n n IO-Link Masters Intelligent Sensors and Actuators Factory Automation Networks The LTC(R)2874 provides a rugged, 4-port IO-Link power and communications interface to remote devices connected by cables up to 20m in length. Output supply voltage and inrush current are ramped up in a controlled manner using external N-channel MOSFETs, providing improved robustness compared to fully integrated solutions. Wake-up pulse generation, line noise suppression, connection sensing and automatic restart after fault conditions are supported, along with signaling at 4.8kb/s, 38.4kb/s, and 230.4kb/s. Configuration and fault reporting are exchanged using a SPI-compatible 4-wire interface that operates at clock rates up to 20MHz. The LTC2874 implements an IO-Link master PHY. For IO-Link device designs, see the LT(R)3669. L, LT, LTC, LTM, Linear Technology, the Linear logo, Module are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. IO-Link is a registered trademark of PROFIBUS User Organization (PNO). All other trademarks are the property of their respective owners. Typical Application Quad-Port 200mA Power Source and Signaling Interface Operating Waveforms 8V TO 34V 100F VDD 1F VL 2.9V TO 5.5V VCC IRQ 4 1F 4 CQ2 20V/DIV SENSE-3 SENSE-4 4 0.2 SENSE-1 SENSE-2 4.7k IRQ CQ1 SENSE+ LTC2874 TXENn GATE1 TXDn GATE2 RXDn GATE3 CQ3 10 CQ4 4s/DIV LOAD: 4nF CQ1, CQ3: SLEW = 0 CQ2, CQ4: SLEW = 1 GATE4 C CS L+1 SCK CQ1 SDI L+2 SDO CQ2 L+3 CQ3 L+4 GND GND CQ4 2874 TA01b 1 4 2 3 1 4 2 3 1 4 3 2 1 4 3 2 2874 TA01a 2874fb For more information www.linear.com/LTC2874 1 LTC2874 Absolute Maximum Ratings (Notes 1, 2, 3) Input Supplies VDD......................................................... -0.3V to 40V VL............................................................. -0.3V to 6V Input Voltages CS, SCK, SDI, TXD ................................... -0.3V to 6V TXEN............................................. -0.3V to VL + 0.3V CQ.................................................... VDD - 50V to 50V GATE - L+ (Note 4)................................. -0.3V to 10V L+.............................................................. -6V to 50V SENSE+, SENSE-....................... VDD - 2V to VDD + 2V Output Voltages GATE........................................... -0.3V to (VL+) + 15V IRQ........................................................... -0.3V to 6V RXD, SDO...................................... -0.3V to VL + 0.3V Operating Temperature Range LTC2874I...............................................-40C to 85C Maximum Junction Temperature........................... 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) FE Package........................................................ 300C Pin Configuration TOP VIEW 36 TXEN3 L+4 4 35 TXD3 CQ4 5 34 RXD3 CQ3 6 33 CS GATE3 7 32 SCK SENSE-3 8 31 SDI L+3 9 30 GND SENSE+ 10 VDD 11 GATE2 12 39 GND 38 37 36 35 34 33 32 CQ4 1 31 TXD3 CQ3 2 30 RXD3 GATE3 3 29 CS SENSE-3 4 28 SCK L+3 5 27 SDI SENSE+ 6 29 GND 28 VL 26 GND 39 GND VDD 7 25 GND GATE2 8 27 TXEN2 24 VL SENSE-2 9 23 TXEN2 SENSE-2 13 26 TXD2 L+2 10 22 TXD2 L+2 14 25 RXD2 CQ2 11 21 RXD2 CQ2 15 24 SDO CQ1 12 IRQ TXEN1 20 RXD1 TXD1 21 TXD1 L+1 19 L+1 22 TXEN1 RXD1 GATE1 23 IRQ SENSE-1 18 20 SDO 13 14 15 16 17 18 19 SENSE-1 CQ1 16 GATE1 17 UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN FE PACKAGE 38-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 25C/W (NOTE 5) EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB 2 TXEN3 37 RXD4 3 RXD4 2 TXD4 GATE4 SENSE-4 TXEN4 TOP VIEW GATE4 38 TXD4 SENSE-4 1 L+4 TXEN4 TJMAX = 150C, JA = 34C/W (NOTE 5) EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB 2874fb For more information www.linear.com/LTC2874 LTC2874 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2874IFE#PBF LTC2874IFE#TRPBF LTC2874FE 38-Lead Plastic TSSOP -40C to 85C LTC2874IUHF#PBF LTC2874IUHF#TRPBF 2874 38-Lead (5mm x 7mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset to their default states. (Note 2) SYMBOL PARAMETER CONDITIONS MIN VDD Input Supply Operating Range 24VMODE = 0 24VMODE = 1 l l IDD VDD Input Supply Current, All Ports Enabled DRVEN = 0xF, ENL+ = 0xF, ILLM = 0x0 l VDD(UVL) UV Lockout VDD Rising l TYP MAX UNITS Input Supply 8 20 5.5 UV Lockout Hysteresis VDD(UVTH) UV Bit Threshold OV Bit Threshold V V 5 8 mA 6 6.5 0.13 VDD Rising 24VMODE = 1 24VMODE = 0 l l 16.2 6.8 UV Bit Threshold Hysteresis VDD(OVTH) 34 34 16.8 7.1 V 17.4 7.4 0.2 VDD Rising, OV_TH = 0x1 l 31 OV Bit Threshold Hysteresis 32 V V V V 33 0.4 V V Logic Supply VL Logic Supply Range IL VL Logic Supply Current l Digital Inputs at 0V or VL l VL+(PGTH) = VDD - V(L+) l 2.9 5.5 0.1 1 1.5 1.9 V mA L+ Power Supply Output VL+(PGTH) L+ Power Good Threshold 1.2 L+ Power Good Hysteresis VCB(TH) VACL Circuit Breaker Threshold Analog Current Limit Voltage VCB(TH) = V(SENSE+) - V(SENSE-) (Note 7) = V(SENSE+) - V(SENSE-) VACL V(L+) = 0V, FLDBK_MODE = 1 V(L+) = VDD - 1V Start-Up, 2XPTC Enabled, V(L+) > 18V (Note 7) tOC(L+) L+ Pin OC Fault Filter V(SENSE+) - V(SENSE-) = 250mV, LPTC = 0x03 (Figure 1) tD(ACL) VSENSE to GATE Low V(SENSE+) - V(SENSE-) = 250mV, LPTC = 0x03 (Figure 1) CG = 0nF CG = 10nF V 100 mV VACL - 0.8 mV l l 9.2 42 16.7 50 100 24.2 58 mV mV mV l 110 122.5 135 s 19 24 25 s s l Start-Up Current Pulse Duration 2XPTC = 0x0 l 52 62 72 ms SENSE- Pin Input Current V(SENSE-) = 24V l 0 10 25 A 2874fb For more information www.linear.com/LTC2874 3 LTC2874 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset to their default states. (Note 2) SYMBOL PARAMETER CONDITIONS External N-Channel Gate Drive (VGATE - VL+) I(GATE) = -1A VDD = 17V to 30V VDD = 8V IGATE(UP) GATE Pin Output Current, Sourcing V(SENSE+) - V(SENSE-) = 0V, V(GATE) = 1V IGATE(DN) GATE Pin Output Current, Sinking ENL+ = 0, V(GATE) = 10V MIN TYP MAX UNITS l l 10 4.5 13 15 15 V V l -10 -14 -20 A Gate Drive VGATE 1.2 mA 90 mA Pull-Down Current from GATE to SOURCE During UVLO or L+ OC Timeout Event V(SENSE+) - V(SENSE-) = 0.2V, VGATE = 10V (VGATE - VL+) for Power Good V(L+) = 8V to 30V l Output High, I(CQ) = -100mA Output Low, I(CQ) = 100mA l l IQPKH, IQPKL Wake-Up Request (WURQ) Current (Figure 2) l 500 700 IQH, IQL Current Limit (Figure 3) l 110 160 tOC(CQ) Overcurrent Timeout CL = 100pF, VDD - CQ or CQ = 5V (Figure 3) SLEW = 0, SIO_MODE = 0 SLEW = 1, SIO_MODE = 0 l l 13 13 IGATE(LIM) 3.0 3.8 4.5 V 1.2 1.1 1.6 1.5 V V CQ Line Driver VRQH, VRQL Residual Voltage (Note 6) mA 230 mA 24 24 s s CQ Line Receiver VTHH Input High Threshold Voltage 24VMODE = 1 24VMODE = 0 l l 10.5 0.5 * VDD 11.9 13 0.7 * VDD V V VTHL Input Low Threshold Voltage 24VMODE = 1 24VMODE = 0 l l 8 0.3 * VDD 9.4 11 0.5 * VDD V V VHYS Input Hysteresis 24VMODE = 1 24VMODE = 0 l l 2.0 0.05 * VDD 2.5 2.9 0.2 * VDD V V Input Resistance V(CQ) = VDD - 1V, ILLM = 0x0 l 390 510 630 VOH Output High Voltage I(RXD) = -100A l VL - 0.4 VOL Output Low Voltage I(RXD) = 100A l Input Threshold Voltage 2.9V VL 5.5V l Input Leakage Current 0V VIN VL CS, TXD SCK, SDI, TXEN l l Input Capacitance (Note 7) l VOH(SDO) SDO Output High Voltage I(SDO) = -1mA l VOL(SDO) SDO Output Low Voltage I(SDO) = 1mA l 0.4 V VOL(IRQ) IRQ Open Drain Output Low Voltage I(IRQ) = 3mA I(IRQ) = 5mA l l 0.4 0.7 V V Receive-Mode Load/Discharge Current ILLM = 0x3, 0V V(CQ) 5V ILLM = 0x3, 5V < V(CQ) 30V ILLM = 0x2, 5V < V(CQ) 30V ILLM = 0x1, 5V < V(CQ) 30V l l l l 6.2 6.2 3.7 2.5 6.8 6.8 4.2 2.8 mA mA mA mA Input to GATE Off Propagation Delay ENL+ UVLO_VDD (Note 7) or OV_VDD Event l l 2 10 4 15 s s k V 0.4 V 0.33 * VL 0.67 * VL V -10 -1 1 10 A A 2.5 pF Digital I/O VL - 0.4 V Other Pin Functions ILL 4 0 5 3.2 2.2 2874fb For more information www.linear.com/LTC2874 LTC2874 Switching Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset to their default states. SYMBOL PARAMETER CONDITIONS GATE Turn-On Delay tRETRY MIN l Auto-Retry Delay RETRYTC = 0x5 ESD Protection CQ and L+ Pins All Other Pins Human Body Model (Note 7) TYP MAX 10 20 UNITS s 3.9 s 8 6 kV kV Driver and Receiver fDTR Maximum Data Transfer Rate CL = 4nF SLEW = 0 SLEW = 1 l l TBIT Bit Time SLEW = 0 SLEW = 1 CCQ CQ Pin Input Capacitance (Note 7) Rise or Fall Time SLEW = 0 (Figure 4) CL = 100pF CL = 4nF l l SLEW = 1 (Figure 4) CL = 100pF CL = 4nF CL = 100pF (Figure 5) SLEW = 0 SLEW = 1 38.4 230.4 kb/s kb/s 26.04 4.34 s s 100 pF 3 3 5.2 5.2 s s l l 0.5 0.5 0.869 0.869 s s l l 4 1.3 8 3 s s Driver tDR, tDF tPHLD, tPLHD Propagation Delay tSKEWD Skew CL = 100pF (Figure 5) SLEW = 0 SLEW = 1 tZHD, tZLD Enable Time RL = 10k, CL = 100pF, ILLM = 0x0 (Figure 6) SLEW = 0 SLEW = 1 l l 12 3 s s 3 s 7.5 20 s 80 85 s 8.3 10 ms 0.5 0.5 tHZD, tLZD Disable Time RL = 10k, CL = 100pF, ILLM = 0x0 (Figure 6) l tWUDLY Wake-Up Request (WURQ) Delay (Figure 2) l tWU WURQ Pulse Duration (Figure 2) l WURQ Cooldown Timer 75 l s s Receiver tH, tL (Figure 7) TBIT = 208.3s (COM1), NSF = 0x1 TBIT = 26.0s (COM2), NSF = 0x2 TBIT = 4.34s (COM3), NSF = 0x3 l l l (Figure 8, Note 9) TBIT = 208.3s (COM1), NSF = 0x1 TBIT = 26.0s (COM2), NSF = 0x2 TBIT = 4.34s (COM3), NSF = 0x3 l l l tPHLR, tPLHR Receiver Propagation Delay NSF = 0x0, CL = 100pF (Figure 7) l Receiver Skew NSF = 0x0, CL = 100pF (Figure 7) tND tSKEWR Detection Time Noise Suppression Time 1/16 1/16 1/16 1/10 1/9 1/7 TBIT TBIT TBIT 1/10 1/9 1/7 1/16 1/16 1/16 TBIT TBIT TBIT 200 600 ns 100 ns 2874fb For more information www.linear.com/LTC2874 5 LTC2874 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 24V, VL = 2.9V to 5.5V unless otherwise noted. (See Figure 9) (Note 7) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Interface tSU CS to SCK Set-Up Time l 7 ns tHD SCK Falling to CS Hold Time tCH SCK High Time l 7 ns l 19 ns tCL SCK Low Time l 19 ns tDS SDI Set-Up Time l 4 ns tDH SDI Hold Time l 4 ns tDO SCK Falling to SDO Valid SCK Frequency C(SDO) = 10pF 4.5V VL 5.5V 2.9V VL < 4.5V l l 20 40 ns ns 50% Duty Cycle (Note 8) l 20 MHz Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltages are with respect to GND. All currents into device pins are positive; all currents out of device pins are negative. Note 3. Numerical subscripts corresponding to port number are sometimes omitted from pin names for brevity. Note 4. An internal clamp limits each GATE pin to a minimum of 10V above its respective L+ pin. Externally driving these pins to voltages beyond the clamp may damage the device. Note 5. This IC includes current limiting and overtemperature protection that are intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Overtemperature protection will become active at a junction temperature greater than the rated maximum operating temperature. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6. Residual voltages are defined as follows: VRQH = VDD - V(CQ), and VRQL = V(CQ) - V(GND). Note 7. Guaranteed by design and not production tested. Note 8. SCK frequency is limited by SDO propagation delay as follows: tSCK 2 * (tDO + ts), where ts is the setup time of the receiving device. Note 9. Guaranteed by production testing of tH and tL. Typical Performance Characteristics otherwise noted. Operation at 230.4kb/s (COM3) and 38.4kb/s (COM2) TA = 25C, VDD = 24V, VL = 3.3V, unless Driver Eye Diagram (COM3) CQ Residual Voltage vs VDD 1.4 ICQ = 100mA CQ1 20V/DIV NO CABLE CQ4 20m CABLE (FAR END) VRQH 10V/DIV CQ3 CQ4 10s/DIV LOAD: 4nF CQ1, CQ3: SLEW = 0 CQ2, CQ4: SLEW = 1 CQ1 RESIDUAL VOLTAGE (V) CQ2 2874 G01 1s/DIV PRBS = 28 - 1 CQ1: LOAD = 4nF CQ4: 20m CABLE + 1nF + 300 CQ2, CQ3: ASYNCHRONOUS COM3 SWITCHING L+1 TO L+4: ENABLED AND BYPASSED AT FAR END 85C 25C -40C 1.3 1.2 1.1 2874 G02 VRQL 1.0 5 10 20 25 30 15 VDD SUPPLY VOLTAGE (V) 35 2874 G03 6 2874fb For more information www.linear.com/LTC2874 LTC2874 Typical Performance Characteristics TA = 25C, VDD = 24V, VL = 3.3V, unless otherwise noted. Driver Current Limit vs Temperature 1000 -IQH IQL 800 CURRENT (mA) CQ Short Circuit Protection Driver Enable/Disable SHORT TO GND CQ 10V/DIV TXEN 2V/DIV FOUR CONNECTED CQ PINS 600 IRQ 5V/DIV 400 TWO CONNECTED CQ PINS -I(CQ) 500mA/DIV 200 EACH CQ PIN 0 -50 -25 25 50 0 TEMPERATURE (C) 75 TXD = GND SIO_MODE = 0 LOAD: 50pF 100 CQ (TXD LOW) CIRCUIT BREAKER 4s/DIV 10V/DIV CQ (TXD HIGH) 2874 G05 2874 G06 2s/DIV SLEW = 1, ILLM = 0x0 LOAD: 100pF (GND) + 10k (VDD OR GND) 2874 G04 6 CQ (NEAR END) DELAY (s) NSF = 0x2 SLEW = 0 SIO_MODE = 1 SLEW = 0 3 2 RXD (NEAR END) ABSMAX 40 0 -40 OUTPUT HIGH -160 0 -50 -25 25 50 0 TEMPERATURE (C) OUTPUT LOW -120 1 2874 G07 80 -80 SLEW = 1 100s/DIV VDD = 30V VDD = 8V 160 120 4 10V/DIV 200 tPLHD tPHLD 5 CQ (FAR END) 5V/DIV LOAD = 100pF CURRENT (mA) 10V/DIV CQ Driver Short-Circuit Current vs Short-Circuit Voltage Driver Propagation Delay vs Temperature Driving 20m Cable to 1F Load 75 -200 -60 100 BEFORE TIME-OUT -40 0 20 -20 CQ PIN VOLTAGE (V) 40 2874 G09 2874 G08 Wake-Up Pulse Width vs Temperature 140 100 85.0 85C -40C VDD = 8V 82.5 PULSE WIDTH (s) CURRENT (A) 60 VDD = 30V 20 -20 VDD - V(CQ) = 50V -60 IQPKL PULSE, VDD = 30V IQPKL PULSE, VDD = 20V IQPKH PULSE, VDD = 30V IQPKH PULSE, VDD = 20V 900 80.0 IQPKL, VDD = 30V IQPKL, VDD = 20V IQPKH, VDD = 30V IQPKH, VDD = 20V 800 700 600 77.5 -100 -140 -60 Wake-Up Current vs Temperature 1000 CURRENT (mA) CQ Pin Current 60 ILLM = 0 DRIVER OFF -40 0 20 -20 CQ PIN VOLTAGE (V) 40 60 2874 G10 500 LOAD = 26 TO GND OR VDD 75.0 -25 25 -50 50 0 TEMPERATURE (C) 75 100 2874 G11 LOAD = 26 TO GND OR VDD 400 -25 25 -50 50 0 TEMPERATURE (C) 75 100 2874 G12 2874fb For more information www.linear.com/LTC2874 7 LTC2874 Typical Performance Characteristics otherwise noted. Wake-Up Pulse: IQPKH TA = 25C, VDD = 24V, VL = 3.3V, unless Receiver Output Voltage vs Load Current Wake-Up Pulse: IQPKL 0.5 16th SCK 16th SCK 5V/DIV 0.4 10V/DIV CQ VOLTAGE (V) 5V/DIV CQ 10V/DIV 5V/DIV IRQ IRQ 5V/DIV 20s/DIV CQ LOAD: 4nF + 100 20s/DIV CQ LOAD: 4nF + 100 2874 G13 VL = 2.9V VL = 3.3V VL = 5V 0.3 VL - VOH 0.2 0.1 2874 G14 VOL 0.0 0.0 0.2 0.3 0.1 LOAD CURRENT (mA) 0.4 2874 G15 23 VDD = 30V VDD = 20V 12 11 10 VTHL 9 NSF = 0x2 NSF = 0x0 1 75 100 0 -50 -25 4 0 25 50 TEMPERATURE (C) NSF = 0x3 1 75 100 0 -50 -25 0 25 50 TEMPERATURE (C) L+1 L+1 L+2 L+2 L+3 100 2X Current Pulse at 18V L+ L+3 10V/DIV 75 2874 G18 L+ Start-Up (Set by CG) and Disable L+4 NSF = 0x2 3 2874 G17 L+ Start-Up with 100F Load 10V/DIV 20 2 NSF = 0x3 2874 G16 FLDBK_MODE = 1 VL = 2.9V TO 5.5V NSF = 0x1 21 4 3 DETECTED REJECTED 22 20 2 24VMODE = 1 8 0 25 50 -50 -25 TEMPERATURE (C) 23 NSF = 0x1 21 VTHH Receiver Pulse Rejection and Detection Delay vs Temperature LOAD = 100pF RISING RXD FALLING RXD 22 DELAY (s) THRESHOLD VOLTAGE (V) 13 Receiver Propagation or Filter Delay vs Temperature PULSE WIDTH (s) Receiver Input Threshold vs Temperature 10V/DIV L+4 -(L+) FLDBK_MODE = 0 2XPTC = 0x1 LPTC = 0xB 8 4ms/DIV 200mA/DIV 2874 G19 2XPTC = 0x1 FLDBK_MODE = 0 LOAD: 10F 40ms/DIV 2874 G20 LPTC = 0xD CG: 22nF 2XPTC = 0x0 FLDBK_MODE = 0 LOAD: 3500F 100ms/DIV 2874 G21 2874fb For more information www.linear.com/LTC2874 LTC2874 Typical Performance Characteristics TA = 25C, VDD = 24V, VL = 3.3V, unless otherwise noted. -14.4 VDD = 30V VDD = 20V VDD = 8V 14.0 FOUR PORTS ON VDD = 30V VDD = 20V VDD = 8V 13.5 VGATE (V) -14.2 CURRENT (A) External MOSFET VGS (VGATE) vs Temperature IGATE(UP) vs Temperature -14.0 L+ Overcurrent Behavior FOUR PORTS ON LOAD STEP (8) 10V/DIV L+ IRQ 5V/DIV 13.0 -13.8 12.5 -13.6 -50 -25 0 25 50 TEMPERATURE (C) 75 12.0 -50 100 -25 0 25 50 TEMPERATURE (C) 75 2874 G22 1.8 FALLING L+ VDD - L+ (V) 16.5 16.0 1.6 1.5 1.4 15.5 15.0 -50 1.3 V(L+) = 0V FLDBK_MODE = 1 -25 0 25 50 TEMPERATURE (C) 75 -25 0 25 50 TEMPERATURE (C) 75 L+ Overcurrent Circuit Breaker Delay vs VSENSE Duty Cycle 1 20 40 60 DUTY CYCLE (%) 80 INPUT LOW 1.5 8 VDD = RISING 100 2874 G27b 3.5 4.0 4.5 5.0 VL SUPPLY VOLTAGE (V) 3.0 OV_TH = 0x3 36 OV_TH = 0x2 34 30 -50 5.5 ILL Sinking Current vs CQ Voltage TA = 85C TA = 25C TA = -40C ILLM = 0x3 6 -25 0 25 50 TEMPERATURE (C) ILLM = 0x2 4 ILLM = 0x1 2 OV_TH = 0x1 32 0.1 0 INPUT HIGH 2.0 2874 G27a 38 10 TA = 85C TA = 25C TA = -40C 1.0 2.5 100 CURRENT (mA) 100 DELAY (ms) 40 SUPPLY VOLTAGE (V) 1000 Logic Input Threshold vs VL Supply Voltage 2.5 VDD Overvoltage Indicator vs Temperature LPTC = 0xF LPTC = 0x8 LPTC = 0x4 LPTC = 0x2 LPTC = 0x1 LPTC = 0x0 2874 G24 2874 G26 2874 G25 10000 100s/DIV RISING L+ 1.2 -50 100 3.0 VDD = 30V VDD = 20V VDD = 8V 1.7 17.0 VACL (mV) L+ Power Good Threshold vs Temperature VDD = 30V VDD = 20V VDD = 8V 17.5 100 THRESHOLD VOLTAGE (V) 18.0 LPTC = 0x4 IRQMASK = 0xF6 FLDBK_MODE = 0 LOAD: 50pF 2874 G23 L+ Current Limit Sense Voltage vs Temperature 0.01 CIRCUIT BREAKER -I(L+) 500mA/DIV 75 100 2874 G28 0 INPUT RESISTANCE ILLM = 0x0 0 10 20 30 40 CQ PIN VOLTAGE (V) 50 2874 G29 2874fb For more information www.linear.com/LTC2874 9 LTC2874 Typical Performance Characteristics otherwise noted. TA = 25C, VDD = 24V, VL = 3.3V, unless VDD Supply Current vs Supply Voltage 70 CQ1 TO CQ4 SWITCHING 1010, L+1 TO L+4 ENABLED 50 SIO, 0.6kb/s, 1F COM2, 0.05nF COM2. 4nF COM2, 10nF COM3, 0.05nF COM3, 1nF COM3, 4nF 40 30 20 COM2 30 0 35 4nF 1nF 20 0 15 20 25 30 VDD SUPPLY VOLTAGE (V) COM1 40 10 10 COM3 CQ1 TO CQ4 SWITCHING 1010 L+1 TO L+4 ENABLED 50 10 5 VDD = 30V VDD = 20V 60 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 60 VDD Supply Current vs Data Rate 70 0.05nF 0 50 100 150 DATE RATE (kb/s) 6 CQ Driver Edge Time vs Supply Voltage VL = 5V VL = 3.3V VL = 2.9V 5 4 3 2 0 1 2 3 4 5 6 LOAD CURRENT (mA) 7 8 2874 G32 10 RISING FALLING LOAD = 100pF CQ1 CQ2 SLEW = 0 3 10V/DIV 2 0 CQ3 CQ4 1 1 0 Driving 12V Relay Coils 4 EDGE TIME (s) VOLTAGE (V) 5 250 2874 G31 2874 G30 SDO Voltage vs Load Current 200 SLEW = 1 5 10 15 20 25 30 VDD SUPPLY VOLTAGE (V) 35 2874 G34 20ms/DIV 24VMODE = 0 SLEW = 0 SIO_MODE = 1 RELAYS: G2R-1-E-T130 DC12 + CATCH DIODE 2874 G33 2874fb For more information www.linear.com/LTC2874 LTC2874 Pin Functions (FE/UHF) TXEN4 (Pin 1/Pin 35): Port 4 CQ4 Driver Enable. See TXEN1. GATE4 (Pin 2/Pin 36): Port 4 Gate Drive. See GATE1. SENSE-4 (Pin 3/Pin 37): L+4 Supply Current Sense Negative Input. See SENSE-1. L+4 (Pin 4/Pin 38): Port 4 Power Supply Output. See L+1. CQ4 (Pin 5/Pin 1): Port 4 C/Q line. See CQ1. CQ3 (Pin 6/Pin 2): Port 3 C/Q line. See CQ1. GATE3 (Pin 7/Pin 3): Port 3 Gate Drive. See GATE1. SENSE-3 (Pin 8/Pin 4): L+3 Supply Current Sense Negative Input. See SENSE-1. L+3 (Pin 9/Pin 5): Port 3 Power Supply Output. See L+1. SENSE+ (Pin 10/Pin 6): L+ Current Sense Common Positive Input. Connect external sense resistors RS1 through RS4, normally 0.2, between this pin and each of the SENSE- pins in a star configuration. See Applications Information. Tie to VDD if unused. Do not leave open. VDD (Pin 11/Pin 7): Supply Voltage Input (8V to 34V). Bypass to GND with a 1F ceramic capacitor placed near the pin and at least 100F additional bulk capacitance. GATE2 (Pin 12/Pin 8): Port 2 Gate Drive. See GATE1. SENSE-2 (Pin 13/Pin 9): L+2 Supply Current Sense Negative Input. See SENSE-1. L+2 (Pin 14/Pin 10): Port 2 Power Supply Output. See L+1. CQ2 (Pin 15/Pin 11): Port 2 C/Q line. See CQ1. CQ1 (Pin 16/Pin 12): Port 1 Bidirectional Communication or Signaling (C/Q) Line. When the port 1 driver is enabled (either by TXEN1 or under SPI control), this pin is an output referenced to GND, inverted in polarity with respect to the TXD1 input. Otherwise, this pin is an input that a remote device may drive and an optional, programmable current sink is active. Receiver output RXD1 monitors this pin in both cases. GATE1 (Pin 17/Pin 13): Gate Drive for External N-Channel MOSFET, Port 1. When the MOSFET is turned on, a 14A current drives the gate to 13V above the L+1 output supply voltage. During a current limit condition, the voltage at GATE1 reduces to maintain constant L+ port current. If a timer expires, GATE1 pulls down, turning off the MOSFET, and a TOC_L+ event is recorded. SENSE-1 (Pin 18/Pin 14): L+1 Supply Current Sense Negative Input. An external sense resistor, RS1 (normally 0.2), connected between this pin and SENSE+ programs the load current limit (VACL/RS1). Current is controlled by an analog current limit amplifier and timed circuit breaker. See L+ PIN POWER CONTROL in the Applications Information section. Tie to VDD if unused. Do not leave open. L+1 (Pin 19/Pin 15): Port 1 Output Supply Monitor and Source Connection. Connect this pin to the source of the external MOSFET for port 1. RXD1 (Pin 20/Pin 16): Port 1 Data Output from CQ1 Receiver, Referenced to VL. Active even when the driver is on. RXD1 polarity is inverted with respect to the line data at the CQ1 pin. 2874fb For more information www.linear.com/LTC2874 11 LTC2874 Pin Functions (FE/UHF) TXD1 (Pin 21/Pin 17): Port 1 Data Input to CQ1 Driver, Referenced to VL. Tie to VL if unused. TXEN1 (Pin 22/Pin 18): Port 1 CQ1 Driver Enable, Referenced to VL. Tie to GND if unused. IRQ (Pin 23/Pin 19): Interrupt Output. Open drain output that pulls low to alert the host microcontroller when an event occurs, eliminating the need for continuous software polling. Disable individual IRQ events using the IRQMASK register. IRQ typically has a pull-up resistor to VL. GND (Pins 29, 30, Exposed Pad Pin 39/Pins 25, 26, Exposed Pad Pin 39): Device Ground. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the PCB. Solder to the board and tie directly to the ground plane using thermal vias. SDI (Pin 31/Pin 27): SPI Interface Data Input, Referenced to VL. Tie to GND if unused. SCK (Pin 32/Pin 28): SPI Interface Clock Input, Referenced to VL. Tie to GND if unused. SDO (Pin 24/Pin 20): SPI Interface Data Output, Referenced to VL. CS (Pin 33/Pin 29): SPI Interface Chip Select Input (Active Low), Referenced to VL. Tie to VL if unused. RXD2 (Pin 25/Pin 21): Port 2 Data Output from CQ2 Receiver. See RXD1. RXD3 (Pin 34/Pin 30): Port 3 Data Output from CQ3 Receiver. See RXD1. TXD2 (Pin 26/Pin 22): Port 2 Data Input to CQ2 Driver. See TXD1. TXD3 (Pin 35/Pin 31): Port 3 Data Input to CQ3 Driver. See TXD1. TXEN2 (Pin 27/Pin 23): Port 2 CQ2 Driver Enable. See TXEN1. TXEN3 (Pin 36/Pin 32): Port 3 CQ3 Driver Enable. See TXEN1. VL (Pin 28/Pin 24): Logic supply (2.9V to 5.5V) for the control logic, registers, receiver outputs, driver inputs, and SPI interface. Bypass to GND with at least a 0.1F capacitor. RXD4 (Pin 37/Pin 33): Port 4 Data Output from CQ4 Receiver. See RXD1. 12 TXD4 (Pin 38/Pin 34): Port 4 Data Input to CQ4 Driver. See TXD1. 2874fb For more information www.linear.com/LTC2874 LTC2874 Block Diagram 2.9V TO 5.5V VL SCK SPI SDI CONTROL AND MONITORING REGISTERS SDO UVLO AND SUPPLY MONITORS OV_VDD UV_VDD UVLO_VDD UVLO_VL THERMAL PROTECTION FAULT CONTROL CVDD1 1F CHARGE PUMP CVDD2 100F TO GATE DRIVERS SENSE+ IRQ PORT 1 16.7mV TO 50mV + SLEW1 DRVEN1 TXEN1 DRIVER CONTROL TXD1 FOLDBACK - 18V + - SENSE- RS1 0.2 1 2X PULSE - 4.7k CS + CVL 0.1F 8V TO 34V VDD ACL NSF1 RXD1 + RCVR PWRGD1 FILTER VDD - 1.5V DRIVER CONTROL WKUP1 WAKEUP GENERATION - CABLE SENSE + ENL+1 RXD3 RXD4 L+1 1 OF 4 CABLES ILLM1 GATE2 PORT 2 L+2 CQ2 SENSE-3 GATE3 PORT 3 L+3 CQ3 SENSE-4 TXEN4 TXD4 Q1 SENSE-2 TXEN3 TXD3 RGATE1 10 CQ1 TXEN2 RXD2 GATE DRIVER - FAULT CONTROL TXD2 GATE1 GATE4 PORT 4 L+4 CQ4 GND 2874 BD 2874fb For more information www.linear.com/LTC2874 13 LTC2874 Test Circuits / Timing Diagrams 250mV VCB(TH) VSENSE 0V tD(ACL) 13V VGATE 2V 0V tOC(L+) VL 50% IRQ VOL(IRQ) 2874 F01 Figure 1. L+ Pin Overcurrent VDD RL CS SDI SCK (16th CLOCK) VL 50% CQ 0V tWUDLY 0A SCK I(CQ) TXEN 0.5A 0.5A IQPKH RL 0V OR VL 0.5A I(CQ) IQPKL 0.5A TWU RL = 52.3 || 51.7 = 26 0A 2874 F02 Figure 2. Wake-Up Parameters GND OR VL VDD - CQ OR CQ CQ TXD 5V 50% 0V A + - TXEN VL VDD - 5V OR 5V -IQH OR IQL I(CQ) 0A tOC(CQ) VL 50% IRQ 2874 F03 VOL(IRQ) Figure 3. CQ Pin Overcurrent TXD CQ TXEN VL VL TXD tDF CL CQ 90% 10% tDR 0V 90% 10% VDD - VRQH VRQL 2874 F04 Figure 4. Driver Edge Rate 14 2874fb For more information www.linear.com/LTC2874 LTC2874 Test Circuits / Timing Diagrams TXD TXEN 50% TXD CQ tPHLD CL CQ VL 50% 0V tPLHD VDD - VRQH VTHH(MAX) VTHL(MIN) VL VRQL tSKEWD = |tPLHD - tPLHD| 2874 F05 Figure 5. Driver Timing TXEN VL OR GND RL CQ TXEN GND OR VDD CL 50% VL 50% 0V tHZD tZHD VDD - 3V VTHH(MAX) CQ VDD - VRQH 0V tZLD tLZD CQ VTHL(MIN) VDD 3V VRQL 2874 F06 Figure 6. Driver Enable/Disable Timing CQ tPHLR RXD RXD CL VDD VTHH(MAX) CQ 50% NOISE SUPPRESSION OFF tPHLR + tH * TBIT 50% RXD VTHL(MIN) NOISE SUPPRESSION ON 0V tPLHR VOH 50% VOL tPLHR + tL * TBIT 50% tSKEWR = |tPHLR - tPLHR| VOH VOL 2874 F07 Figure 7. Receiver Timing SHORT GLITCH REJECTED tND LONG GLITCH DETECTED VDD CQ VTHH VTHL 0V VOH RXD VOL TBIT TBIT 2874 F08 Figure 8. Receiver Noise Suppression 2874fb For more information www.linear.com/LTC2874 15 LTC2874 Test Circuits / Timing Diagrams tSU tDS CS 1 SCK 0 SDI 2 0 3 0 tCH tDH 4 A3 5 A2 6 A1 7 A0 tHD tSCK tCL 8 X 9 10 11 12 13 14 15 16 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 HI-Z HI-Z SDO 2874 F09 tDO Figure 9. SPI Interface Timing (Read) CS 1 SCK C2 SDI 2 C1 3 C0 4 A3 5 A2 6 A1 7 A0 8 X 9 D7 10 D6 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 HI-Z HI-Z SDO 2874 F10 Figure 10. SPI Interface Timing (Write or WrtUpd) 16 2874fb For more information www.linear.com/LTC2874 LTC2874 Operation The LTC2874 is an industrial master Hot Swap bus controller and physical interface (PHY) that provides power and communication to four independent 3-wire ports through cables up to 20m in length (see Figure 11A). The primary applications are 24V systems specified by IEC 61131-9 single-drop communication interface (SDCI) for small sensors and actuators, commonly known as IO-Link. Each port on the LTC2874 includes a Hot Swap power supply output, data transceiver, and a current sink, as shown in Figure 11B. This set of features allows a typical master controller for four ports to be built with the LTC2874, a host microcontroller, and four power MOSFETs. The basic configuration is shown on page 1. VDD L+ L+ C/Q L- C/Q DRV DEVICE ILL L+, L-: POWER SUPPLY L- C/Q: COMMUNICATION OR SWITCHING SIGNAL (A) The rugged LTC2874 line interface has been designed to tolerate abusive conditions encountered on cable interfaces. The CQ pins will tolerate 50V above L- (GND) and -50V from VDD. The L+ pins offer commensurate ruggedness for power supply outputs (see Absolute Maximum Ratings). Discrete power MOSFETs offer the best possible system ruggedness and allow design flexibility. They also ensure that ports remain fully independent in the event of extreme fault conditions. Hot Swap MASTER The LTC2874 turns each port's supply voltage on and off in a controlled manner using external N-channel MOSFETs. External sense resistors individually set the current limits for each port. Optional foldback behavior reduces maximum power dissipation in the external MOSFETs over their operating range. Each output is protected by a circuit breaker that responds to an overcurrent fault after a programmable timeout delay. A current-pulse-upon-18V feature provides additional IO-Link capability for driving heavy, nonlinear loads. (B) 2874 F11 Figure 11. (A) SDCI Class A 3-Wire Interface (B) LTC2874 Master 3-Wire Interface Port The bidirectional CQ pins are individually programmable to operate in coded switching (COM) or switching signal (standard IO, or SIO) format with reconfigurable behavior including slew rate, noise suppression filter, and sinking current. Drivers are protected against overcurrent faults by circuit breakers that respond to a fault condition after a mode-specific delay. For IO-Link compatibility, under SPI control, the LTC2874 automatically generates 80s wake-up request (WURQ) pulses with correct polarity. Normally, the LTC2874 will automatically restart after supply overvoltage or port overcurrent timeout faults. The auto-retry delay is programmable. Alternatively, latchoff behavior is available. Overcurrent circuit breaker delays for CQ pins are mode dependent; for L+ pins they are programmable. The LTC2874 provides a 4-wire SPI-compatible interface for configuration and monitoring. The host can detect faults and other events by polling four event registers or by monitoring the IRQ pin, a programmable interrupt request. Standalone Operation The LTC2874 is designed for use with a host controller. The SPI-compatible interface is the only means of operating the Hot Swap power supply outputs. The transceivers can operate standalone without the serial interface, restricted by the default register configuration settings. 2874fb For more information www.linear.com/LTC2874 17 LTC2874 Applications Information Drivers Receivers The LTC2874 line drivers convert digital levels at the TXD pins to inverted polarity line levels at the CQ pins. Drive at data rates of up to 230.4kb/s. For IO-Link operation, they support COM1, COM2, and COM3 transmission. The four drivers operate concurrently and independently. The four receivers convert 24V signals detected at the CQ line inputs to inverted-polarity logic levels at the RXD outputs. Receiver threshold behavior is selectable, as shown in Figure 12. When the 24VMODE bit is set low, the receiver thresholds for all four ports track the input VDD supply. The drivers feature a controlled programmable slew rate for optimum EMC performance. Rise and fall times are programmed using a register bit and are independent of the VDD supply voltage. Set each driver's SLEW bit high for edge times of 0.5s, or low for edge times of 3s. Each driver is enabled either by its TXEN pin or DRVEN register bit. When disabled, drivers are Hi-Z and the CQ pin impedance is dominated by the ILL current sink (unless disabled) and the receiver input resistance. While the line drivers normally operate push-pull, each can also operate in open-drain mode by driving the data signal into its TXEN pin. For operation with an external pull-up, tie its TXD pin high. For an external pull-down, disable that port's current sink (ILLM = 0) and tie its TXD pin low. SIO Mode Up to 1F of load capacitance can be driven in SIO, or standard I/O, mode. Set SIO_MODE = 1 and reduce the edge rate (SLEW = 0). In SIO mode, the overcurrent circuit breaker timeout is extended to 480s. Configuring CQ Outputs for 200mA or 400mA The LTC2874 driving capability can be increased by connecting CQ outputs and operating drivers in parallel. Figure 36 shows a 2-port configuration that guarantees a minimum CQ drive strength of 200mA, and Figure 37 shows a configuration for 400mA. Combine only CQ outputs from a single LTC2874. 18 20 RECEIVER THRESHOLDS (V) The LTC2874 line drivers are current limited to 160mA. Each is protected by an overcurrent circuit breaker with modeselectable timeout. For normal signaling (SIO_MODE = 0), the circuit breaker will trip after being in current limit for 15s. This timeout is more than sufficient to support IOlink requirements. 0.55*VDD 15 24VMODE = 1 VTHH 10 0.45*VDD 11.9V 9.4V VTHL 5 24VMODE = 0 0 0 10 20 30 VDD SUPPLY VOLTAGE (V) 40 2874 F12 Figure 12. CQ Receiver Input Threshold (Typical) Each receiver has an optional digital noise filter that rejects narrow pulses on the CQ line. Filter delays of 0.6s, 2.8s or 20.3s are selected using port-specific NSF register bits. Setting NSF = 0x0 disables the filter. When the receiver is operated at an IO-Link compatible data rate (COM3, COM2 or COM1) and the NSF bits are set accordingly, the filter rejects pulses shorter than 1/16 of the bit time. Figure 13 illustrates the rejection and detection bands for a positive noise glitch. Except when Hi-Z at start-up (see Figure 26), receivers are always active. Driver and receiver settings appropriate for SIO mode and IO-Link operation are summarized in Table 1. Table 1. Recommended Driver and Receiver Settings OPERATION SLEW NSF SIO_MODE SIO 0 0x1 1 COM1 0 0x1 0 COM2 0 0x2 0 COM3 1 0x3 0 2874fb For more information www.linear.com/LTC2874 LTC2874 Although WURQs may be generated with the driver enabled, we recommend the following procedure for best results: DETECTED REJECTED UNDEFINED 1. Disable driver. 2. Clear any driver fault by setting TOC_CQ event bit low. 0V REJECTED VTHH REJECTED GLITCH HIGH LEVEL Applications Information REJECTED NSF = 0x01, 0x10: N = 3/16 NSF = 0x11: N = 4/16 N * TBIT 1/16 TBIT GLITCH DURATION 2874 F13 Figure 13. Receiver Noise Rejection and Detection Behavior for CQ Positive Glitch Current Sinks Each CQ pin has a programmable current sink for use with sensors having high side outputs. Each port's current sink is independently set to a value of 0mA, 2.5mA, 3.7mA, or 6.2mA with port-specific ILLM register bits. The highest setting guarantees 5mA for IO-link. The second setting guarantees 2.2mA for compatibility with IEC 61131-2 digital inputs. Each current sink disables when its driver is enabled or a wake-up request is in progress on that port. Automatic Wake-Up Generation The LTC2874 generates an 80s 500mA wake-up pulse for the purpose of gaining the attention of a remote IOLink device. To initiate WURQ generation on a particular port, the respective WKUP bit must be set high. Acting as a pushbutton, the bit will self-clear once the WURQ is underway. The sequence begins by automatically determining the correct polarity for the pulse, first by disabling the driver (as needed) and sensing the CQ line for 5s. The driver switches on to generate the pulse, then returns to its state prior to the WURQ (normally off). The complete sequence is shown in Figure 14. WKUP BIT SELF-CLEARS WKUP BIT CQ SENSE 5s 80s READY AGAIN 8.3ms LOCKOUT WU EVENT BIT 3. Generate WURQ by setting WKUP bit high. Several measures prevent overheating during WURQ, when driver power dissipation can be high (for example, easily 15W at maximum operating voltage). First, if any overtemperature condition is detected when the WKUP bit is first set high, polarity sensing and pulse generation are delayed until the condition clears. Second, only one port at a time is allowed a WURQ, determined by lowest port number in the event of a simultaneous request. Third, upon completion of a WURQ, an 8.3ms cool-down interval is enforced before another WURQ can be generated. While a WURQ is underway on any port, the WKUP bits cannot be set. (Their holding latches can be set high with a write command, and even read out, but when updated by an update or WrtUpd command, they will clear and not change the register bits themselves. See the Serial Interface section for more information.) Finally, a thermal shutdown condition will cause the driver to turn off. Normal overcurrent circuit breaker timers are disabled during wake-up. Setting the 24VMODE register bit low disables wake-up generation; the WKUP bits have no effect and will not self clear. L+ PIN POWER CONTROL External MOSFET, Sense R Summary One function of the LTC2874 is to control delivery of power through cables to four remote devices. On each port it does this by controlling the gate voltage of an external power MOSFET based on the current monitored by an external sense resistor and the output voltage at the L+ pin. This circuitry couples the raw VDD input supply to each port through the MOSFET in a controlled manner that satisfies the power needs of the connected device while minimizing power dissipation in the MOSFET and disturbances on the VDD backplane. 2874 F14 Figure 14. Wake-up Sequence 2874fb For more information www.linear.com/LTC2874 19 LTC2874 Applications Information Inrush Control When the L+ supply of any port is enabled (ENL+ = 1), the LTC2874 ramps up the GATE pin of that port's external MOSFET in a controlled manner. The gate drivers use a shared charge pump that derives its power from VDD. Under normal power-up circumstances, the MOSFET gate rises until the port current reaches the current limit, at which point the GATE pin is servoed to maintain the current limit. The ramp rate of the L+ port output voltage is: dV(L+) I(L+) VACL = = dt CL+ RS * CL+ where CL+ is the capacitance on the L+ pin, including supply bypass capacitance of the connected device. During this inrush period, an integrating up/down counter times the duration that the current exceeds the circuit breaker threshold VCB(TH). When output charging is complete, the port current falls and the GATE pin resumes rising to fully enhance the MOSFET and minimize its onresistance. The final VGS is nominally 13V. If the timer expires before the inrush period completes, the port is turned off and a TOC_L+ fault is reported. The timer delay is adjustable from 17.5s to 0.25s using the LPTC register bits. Optionally, the L+ pin ramp rate can be slowed further using the RGCG network shown in Figure 22. For a sufficiently large capacitor, the ramp rate is: current to exceed VCB(TH)/RS for a limited time before powering down the port. This duration is timed by an integrating up/down counter for that port whose minimum timeout, which is common to all ports, is set in the TMRCTRL register (0xC). If the current drops below the circuit breaker current threshold before the timer expires, the timer counts back down at the same rate. This allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 50%; longer duty cycle overloads will turn the port off. L+ Current Limit Foldback Protection During port start-up (inrush) or when a cable is connected (hot-plugged) to an enabled port, most of the supply voltage is dropped across the MOSFET as it begins to supply charging current to the remote device. To protect the MOSFET from overheating, the LTC2874 has a current limit foldback circuit that limits the maximum power dissipated by the external MOSFET, thereby increasing its robustness. Figure 15 shows how VACL is linearly reduced (folded back) according to the voltage on the L+ pin. The circuit breaker voltage VCB(TH) is also folded back and remains no higher than VACL. Figure 16 shows typical power-on behavior with foldback. Foldback mode may interfere with start-up into some resistive loads. Setting the FLDBK_MODE bit low disables foldback behavior. 50 FLDBK_MODE = 0 VACL (mV) The current limit of each LTC2874 L+ port is set with a resistor of value VACL/ILIMIT. Specified variation in VACL (10%) and tolerance of the resistor must be taken into account. For IO-Link applications (which require a guaranteed minimum of 0.2A), 0.2 sense resistors (RS1 to RS4) will set the typical limit 25% above the required minimum. dV(L+) dV(GATE) I(GATE) 14A = = = dt dt CG CG 1.2 3 Using a CG of 10nF will cause L+ to ramp on in about 20ms. L+ Current Limit FLDBK_MODE = 1 16.7 24VMODE = 0 24VMODE = 1 L+ VOLTAGE (V) 7 18 2874 F15 Figure 15. L+ Foldback Characteristic The LTC2874 actively controls the MOSFET gate drive to keep the port current below VACL/RS. It allows the port 20 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information When the L+ pin voltage first reaches 18V, the L+ port current limit is doubled for a timed interval. The current sense voltage VACL is increased 100%, and the circuit breaker time is disabled until the pulse timer expires. ENL+ BIT VDD + 13V VDD L+ GATE The start-up pulse duration is set using the 2XPTC register bits. The default setting of 62ms satisfies the required minimum of 50ms for IO-Link compatibility. Durations of 31ms and 124ms are also available. Set the L+ overcurrent timer (adjusted with the LPTC register bits) to a sufficiently high setting to ensure that the circuit breaker doesn't trip before L+ reaches 18V. Setting 2XPTC to 0x1 disables the start-up pulse function. CURRENT LIMITED OV I(L+) ILOAD FOLDBACK 2874 F16 Figure 16. L+ Enable Behavior with Foldback L+ Overcurrent Fault When a circuit breaker timeout occurs, the corresponding timeout fault event bit (TOC_L+) is set and the GATE pin is pulled down to the L+ pin with a 90mA current. The remaining ports of the LTC2874 are unaffected, and the ENL+ bit remains set. If the RETRY_L+ bit is set, autoretry will re-enable the port after a delay; otherwise, the port latches off until the event bit is cleared. Figure 24 and Figure 25 show example behavior. L+ Supply Current Pulse Capability The LTC2874 can optionally double the available current (to 2 * VACL/RS) when an L+ output supply is first powered on, accommodating connected devices that require higher current during their own start-up phase. This function may be useful in applications where there is no signaling that it's safe to turn on downstream dynamic loads. Figure 17 shows simplified behavior when connected to a 100F load with a 0.2 sense resistor and foldback disabled (FLDBK_MODE = 0). ENL+ BIT L+ Power Good and Power Changed Power good status is signalled when the L+ pin voltage rises to within VL+(PGTH) of the VDD supply rail and the GATE to L+ voltage exceeds 3.8V, indicating that the MOSFET is almost fully enhanced. After a 10s delay, a PWRCHNG event indicates that the PWRGD status has changed, as shown in Figure 18. Once an L+ output is disabled, the PWRGD status bit clears and the PWRCHNG event bit is static. VDD - V(L+PGTH) L+ PWRGD STATUS BIT PWRCHNG EVENT BIT VDD 10s 10s 2874 F18 18V Figure 18. Power Good Status and Power Changed Event 62ms 2X CURRENT PULSE CAPABILITY L+ L+ PORT CURRENT LIMIT CLEAR EVENT 250mA ACTUAL I(L+) 500mA 2874 F17 Figure 17. L+ Current Pulse Capability 2874fb For more information www.linear.com/LTC2874 21 LTC2874 Applications Information Gate Turn-Off When a port is disabled (ENL+ = 0), its MOSFET is turned off with a 1.2mA current pulling down the GATE pin to GND. The L+ pin voltage drops as CL+ discharges. The LTC2874 is designed to turn off the GATE rapidly during certain fault conditions to prevent damage to the MOSFET. The fault events that initiate a faster shut down include UVLO of either supply, VDD overvoltage (unless OV_ALLOW = 1), and overcurrent circuit breaker timeout (TOC_L+). In these cases the GATE pin is discharged to the L+ pin with a 90mA current. At the maximum operating supply, the timer delay accommodates typically 100nF of combined L+ and GATE pin loading on the master board without falsely detecting a connection. Cable disconnection is not sensed. Power good (PWRGD) status is low during the SENSE and WAIT states. L+EN BIT VDD - 1.5 * VPG(TH) 40ms ISENSE Cable Sensing Hot-plugging, or the connection and disconnection of cables to an already enabled port, can cause sparking and reliability problems as connector plating wears off over time. Connection sensing mode (CSENSE_MODE = 1) mitigates this problem, extending connector lifetime. When a port is enabled with this feature active, the LTC2874 waits until it detects an external connection to its L+ pin before enhancing the external MOSFET supplying it. The cable sense function identifies cable connections by measuring capacitive loading. The concept is shown in Figure 19. When a given port is enabled, the L+ and GATE pins are trickle-charged positive with 200A, keeping VGATE close to 0V. The LTC2874 determines that a cable is connected if either L+ doesn't rise within about 40ms (because it is loaded) or L+ subsequently pulls low (because a connected cable steals trickle current charge). Figure 20 and Figure 21 illustrate the behavior. 200A SENSE L+EN = 0 L+EN = 1 40ms L+ HIGH CSENSE EVENT BIT IRQ 2874 F20 Figure 20. Cable Sense Behavior: Connection Before ENL+ L+EN BIT GATE ON VDD - 1.5 * VPG(TH) 40ms ISENSE CABLE CONNECTED AFTER ENL+ L+ IRQ 2874 F21 L+EN = 0 L+EN = 0 CABLE CONNECTED BEFORE ENL+ L+ CSENSE EVENT BIT 40ms L+ LOW GATE OFF GATE ON WAIT Figure 21. Cable Sense Behavior: Connection After ENL+ L+ LOW GATE ON 2874 F19 Figure 19. Cable Sensing State Diagram 22 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information L+ Current Limit Stability Design Example For many applications the LTC2874 current limit is stable with a minimum of external components. In Figure 22, RGATE is required to suppress the tendancy for Q1 to develop parasitic self-oscillation. A value between 10 and 100 is recommended. The bypass capacitors on the VDD input supply play an essential role as well. The MOSFET is sized to handle power dissipation during inrush when L+ loads are being charged. Considering the case of a load capacitor CL+, power dissipation during inrush can be determined based on the principle that: In some applications, additional components are needed to improve stability. Small MOSFETs with especially low CGS are less stable, as are larger sense resistors RS. Improve stability using the RGCG compensation network in Figure 22. For RG, choose a value between 100 (normally sufficient ) and 1k; for CG, use between 2nF and 10nF. Do not connect CG directly between the GATE pin and ground. Board level short-circuit testing is recommended. The worst-case condition for current limit stability occurs when the output is shorted to ground after a normal start-up. The capacitor CG serves a dual purpose, also setting the L+ pin ramp rate described in the Inrush Control section. Careful selection of the power MOSFET is critical to system reliability. For IO-Link compatibility, Linear Technology recommends Fairchild FQT7N10, or a similar planar process device in a SOT-223 package. Larger devices may degrade transient performance of current limiting, while smaller devices are more likely to require external compensation (see L+ Current Limit Stability) and require more care to stay within the rated safe operating area (SOA). RS 0.2 CVDD2 100F CVDD1 1F This stored energy is 0.5 * CV2. For example: Energy in CL+ = 0.5 * 100F * (30V)2 = 0.045J With foldback mode disabled, the time it takes to charge up CL+ is: V *C 30V *100F tSTARTUP = DD L+ = = 12ms VACL 50mV 0.2 RS MOSFET power dissipation is: P= Energy in CL+ = 3.75W tSTARTUP In foldback mode, this power is reduced further. MOSFET Selection VDD Energy in the MOSFET = Energy in CL+ Q1 CABLE SENSE+ SENSE- LTC2874 + CL+ RGATE 10 GATE RG CG For IO-Link applications, another case to consider is the start-up current pulse (see L+ Supply Current Pulse Capability), in which a heavy nonlinear load could be supplied twice the normal current, or 2 * VACL/RS, for up to 72ms. Again assuming 0.2 sense resistors and no benefit from foldback, average MOSFET power dissipation is: (0V +18V) P = 30V - * 0.5A = 3.0W 2 The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package tolerates the more extreme case, 3W for 72ms. The SOA curves of the Fairchild FQT7N10 provide for 350mA at 30V (>10W) for 100ms, satisfying this requirement. 2874 F22 Figure 22. External Components for Improving Stability and Controlling Inrush Current 2874fb For more information www.linear.com/LTC2874 23 LTC2874 Applications Information Power Considerations The LTC2874 has two power supply pins: a logic supply pin (VL) and the primary supply (VDD). The VL supply powers the control logic, serial interface and SPI registers, and allows the LTC2874 to interface with any logic signal from 2.9V to 5.5V. Bypass VL to GND with at least a 0.1F ceramic capacitor. There is no power supply sequencing requirement. Bypass capacitance between VDD and GND is important for reliable operation. If a short circuit occurs at one of the L+ output ports, it can take more than 20s for the LTC2874 to begin regulating the current. During this time the current is limited only by minimal impedance, so a high current spike can cause a voltage transient on the VDD supply with the possibility that the LTC2874 resets due to a UVLO fault. Decouple VDD to ground with at least 100F bulk capacitance and a 1F, 100V X7R ceramic capacitor placed near the VDD pin to minimize spurious resets. Supply Monitors The LTC2874 monitors various conditions on its two input power supplies, and alerts the host microcontroller when supply levels move outside of their operating range. Event bits record when the logic supply VL has moved below its UVLO threshold or when the main supply VDD has moved below its UVLO threshold, below its mode-dependent UV level, or above its programmable OV level (see Figure 23). VDD + 18V 32V 34V 36V - OV_TH[1:0] 7V 17.5V 6V VL 2V 10s UV_VDD EVENT 10s UVLO_VDD EVENT - + 0V_VDD EVENT STATUS - + 24VMODE 10s STATUS - UVLO_VL EVENT + POR To provide immunity against supply voltage spikes, the VDD event bits have a 10s filter time. Status bits are live (no-delay) indicators. Operating Above 30V When operating above 30V, the VDD threshold at which overvoltage circuits disable the CQ and L+ pins must be set higher than the default value (32V). Choose a value of 34V or 36V using the OV_TH[1:0] register bits. Auto-Retry or Latchoff Fault Response When a line output is shorted or the VCB(TH) threshold is otherwise exceeded, a timed circuit breaker disables the L+ power supply output or CQ driver before overheating can damage the MOSFET (L+) or master (CQ). Register bits RETRY_L+ and RETRY_CQ allow independent fault behavior for L+ and CQ pins. Set these bits high for autoretry behavior and low for latchoff. Default behavior is auto-retry. When configured for auto-retry behavior, the LTC2874 periodically re-enables the pin to check if the fault condition is still present. See Erratum #1. The RETRYTC[2:0] register bits adjust the retry timer delay from 0.12s to 15.7s to allow for cooling. Choose retry (RETRYTC) and overcurrent timer (LPTC) settings in tandem to keep the duty cycle of an L+ fault condition sufficiently low to allow for cooling of the external MOSFET. In the case of a CQ fault condition, even the fastest RETRYTC setting limits the duty cycle to <1% to allow for cooling of one or more drivers. When configured for latchoff behavior, the LTC2874 disables the respective L+ or CQ pin until the overcurrent event bit is cleared. In this case, clearing the event register initiates a manual retry. The host is responsible for limiting the duty cycle of the fault condition to avoid overheating the L+ MOSFET or CQ driver. For example, when using the highest available LPTC setting, a manual retry interval of 1s limits the L+ MOSFET duty cycle to 20%. In SIO mode, a manual retry interval of 5ms limits the CQ driver duty cycle to 10%. 2874 F23 Figure 23. Supply UVLO, UV, and OV Monitors 24 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information Examples of both responses to an L+ fault are shown in Figure 24 and Figure 25. tOC(L+) tRETRY tOC(L+) tRETRY VDD EARLIEST POSSIBLE TRANSITION OF L+ IF ENABLED BY ENL+ OR CQ IF ENABLED BY TXEN/DRVEN VDD(UVL) L+ 10ms TOC L+ EVENT BIT HI-Z RXD 2874 F26 IRQ Figure 26. CQ or L+ Pin Start-Up Behavior 2874 F24 SPI Interface Figure 24. Auto-Retry Fault Behavior (for L+ Short) tOC(L+) LATCHOFF tOC(L+) The LTC2874 communicates with the host using a SPI-compatible 4-wire interface. Figure 9 and Figure 10 show typical communication waveforms and timing relationships. Interrupts are signaled to the host via the IRQ pin. LATCHOFF L+ CLEAR EVENT TOC L+ EVENT BIT IRQ 2874 F25 Figure 25. Latchoff Fault Behavior (for L+ Short) The LTC2874 allows the response to VDD supply overvoltage faults to be tailored with similar flexibility. Normally, this fault causes the L+ and CQ pins of all four ports to be disabled. The RETRY_OV bit selects between auto-retry and latchoff behavior. If the OV_ALLOW bit is set high, the LTC2874 will tolerate overvoltage conditions, signaling the event but not disabling any functions. Auto-retry doesn't clear any event registers, nor does writing any event register bit high disable any function. Start-Up Behavior Both external supplies must exceed their undervoltage lockout levels for 10ms before the CQ and L+ outputs are allowed to turn on and before VDD events are reported. During that settling interval, the RXD pins are Hi-Z. Figure 26 shows typical start-up behavior, assuming the VDD supply is the last to power on. When the chip select input CS is set low, it enables the SCK input buffer and the SDO output. Data at the SDI pin is transferred into the shift register at subsequent rising SCK edges. For each 16-bit word, the command bits C2 to C0 are loaded first; then address bits A3 to A0; then a don't-care bit; and finally bits D7 to D0, which supply a byte of data (ordered MSB-to-LSB) for some commands. Data can be transferred to the LTC2874 only when CS is low. SCK may be high or low at the falling edge of CS. Keep SCK low between commands to ensure timely completion of all commands. Commands and their formats are shown in Table 2. Command codes not shown are reserved and should not be used. Table 2. LTC2874 Command List and Format COMMAND DETAIL (FIRST) c2...c0 a3...a0 Bit-8 (LAST) d7...d0 READ Read Register 000 AAAA X XXXXXXXX WRITE Write Register (No Update) 001 AAAA X DDDDDDDD UPDATE Update All Registers 010 XXXX X XXXXXXXX WRTUPD Write One Register and Update All 011 AAAA X DDDDDDDD RESET Reset 111 XXXX X XXXXXXXX 2874fb For more information www.linear.com/LTC2874 25 LTC2874 Applications Information SPI Write, Update, and WrtUpd Commands SPI Reset Command Three of the commands relate to writing data to the registers. The write command transfers data from the shift register to the holding latches of any writable register. The update command transfers data from all holding latches to the SPI registers. The WrtUpd combines these two commands. The reset command returns default values to the SPI register and clears internal latches. It has no effect on the SPI data path itself. This command has sticky behavior, not releasing until a subsequent command (besides reset) is received. For the write and WrtUpd commands, data is transferred from the shift register on the 16th falling edge of SCK. SPI Read Command The read command transfers a byte of data from the holding latches of a SPI register to the serial output pin (SDO). Transitions occur on falling clock edges, allowing data to be sampled by the SPI master on the rising edges, beginning with the 8th SCK. When CS is low, the SDO pin is low except when a high register bit is being read out. When CS is high, SDO is Hi-Z. SEQUENCE AT SDI PIN (FIRST) (LAST) COMMAND RESET WRITE WRITE WRITE UPDATE READ 0x8 0x9 0xA 0x1F 0xF0 0x00 0x0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 Continuous Transfer Capability Commonly for SPI communication, CS is asserted low once per command word. The LTC2874 also supports continuous transfer in which multiple command words, each accompanied by 16 SCK pulses, are grouped in a sequence (Figure 28). This feature is useful for software polling or writing to multiple registers. Keep CS low until after the last command word in the group. Chip Select Addressing Combine LTC2874 devices to build larger masters by assigning each its own CS and sharing the remaining SPI interface wires. See Figure 40. SPI Registers The LTC2874 has 15 registers for configuration and monitoring: seven for control, two for status, four to record events, and two to handle interrupts. Register bit assignments are summarized in Table 3. 2874 F27 Figure 27. Example SPI Commands Data written to the internal data holding latches can be verified prior to committing data to the SPI registers by reading it before an update command is sent. When VL is below approximately 2V, the SPI serial port resets to power-on states and registers are set to default values. The reset command similarly sets the registers to default values (with minor differences listed in the last column of Table 3) and resets internal control circuits. CS SCK 16 SCK |||||||||||||||| 16 SCK PULSES 16 SCK PULSES 16 SCK PULSES 16 SCK PULSES 16 SCK PULSES SDI RESET WRITE WRITE WRITE WRITE UPDATE 2874 F28 Figure 28. Continuous Transfer Capability 26 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information Table 3. SPI Register Table REG NAME 0x0 IRQREG OT SUPPLY WU TOC_L+ PWRCHNG TOC_CQ CSENSE (Read Only) Overtemp Event Occurred Supply Event Occurred Wake-Up Event Occurred L+ OC Timeout Event Occurred L+ Power Changed Event Occurred CQ OC Timeout Event Occurred Cable Sense Event Occurred IRQMASK OT SUPPLY WU TOC_L+ PWRCHNG TOC_CQ CSENSE Overtemp IRQ Mask Supply IRQ Mask Wake-Up IRQ Mask L+ OC Timeout IRQ Mask L+ Power Changed IRQ Mask CQ OC Timeout IRQ Mask Cable Sense IRQ Mask OT_SD OT_WARN Reserved UVLO_VL UVLO_VDD UV_VDD OV_VDD Overtemp Shutdown Occurred Overtemp Warning Occurred VL UVLO Event Occurred VDD UVLO Event Occurred VDD UV Event Occurred VDD OV Event Occurred WU4 WU3 WU2 WU1 TOC_L+4 TOC_L+3 TOC_L+2 TOC_L+1 Wake-Up Event CQ4 Occurred Wake-Up Event CQ3 Occurred Wake-Up Event CQ2 Occurred Wake-Up Event CQ1 Occurred L+4 OC Timeout Event Occurred L+3 OC Timeout Event Occurred L+2 OC Timeout Event Occurred L+1 OC Timeout Event Occurred PWRCHNG4 PWRCHNG3 PWRCHNG2 PWRCHNG1 TOC_CQ4 TOC_CQ3 TOC_CQ2 TOC_CQ1 L+4 Power Changed Event Occurred L+3 Power Changed Event Occurred L+2 Power Changed Event Occurred L+1 Power Changed Event Occurred CQ4 OC Timeout Event Occurred CQ3 OC Timeout Event Occurred CQ2 OC Timeout Event Occurred CQ1 OC Timeout Event Occurred CQ_SNS4 CQ_SNS3 CQ_SNS2 CQ_SNS1 CSENSE4 CSENSE3 CSENSE2 CSENSE1 CQ4 Sense: CQ3 Sense: CQ2 Sense: CQ1 Sense: 0 = CQ High 1 = CQ Low 0 = CQ High 1 = CQ Low 0 = CQ High 1 = CQ Low L+3 Cable L+4 Cable 0 = CQ High Sense Event Sense Event Occurred 1 = CQ Low Occurred L+2 Cable Sense Event Occurred L+1 Cable Sense Event Occurred STATUS1 OT WU_COOL UVLO_VDD OV_VDD OC_L+4 OC_L+3 OC_L+2 OC_L+1 (Read Only) OverWURQ or temperature Cooldown Condition Condition VDD UVLO Condition VDD Overvoltage Condition L+4 Overcurrent Condition L+3 Overcurrent Condition L+2 Overcurrent Condition L+1 Overcurrent Condition STATUS2 PWRGD4 PWRGD3 PWRGD2 PWRGD1 OC_CQ4 OC_CQ3 OC_CQ2 OC_CQ1 (Read Only) L+4 Power Good L+3 Power Good L+2 Power Good L+1 Power Good CQ4 Overcurrent Condition CQ3 Overcurrent Condition CQ2 Overcurrent Condition CQ1 Overcurrent Condition MODE1 24VMODE CSENSE_ MODE 2XPTC[1:0] FLDBK_ MODE RETRY_OV RETRY_L+ RETRY_CQ Enable VDD OV Auto-Retry Enable L+ Pin Auto-Retry Enable CQ Pin Auto-Retry CQ_SNS_ MODE 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 EVENT1 EVENT2 EVENT3 EVENT4 D7 Enable IO-Link Compatible Mode 0x9 MODE2 D6 Enable Cable Sense Mode D5 D4 L+ Start-Up 2X Current Pulse Timer Control: 00 = 62ms 01 = Disabled 10 = 31ms 11 = 124ms D3 Enable Foldback Mode D2 D1 SLEW4 SLEW3 SLEW2 SLEW1 OV_TH[1:0] OV_ALLOW CQ4 Edge Rate: CQ3 Edge Rate: CQ2 Edge Rate: CQ1 Edge Rate: VDD Overvoltage Threshold Select: Allow VDD Overvoltage 0 = Slow 1 = Fast 0 = Slow 1 = Fast 0 = Slow 1 = Fast 0 = Slow 1 = Fast 00 = 18V 01 = 32V 10 = 34V 11 = 36V D0 Reserved DEFAULT 0100,0000 (VL-on Reset) 0000,0000 (SPI Reset) Reserved 1111,1110 Reserved 0001,0000 (VL-on Reset) 0000,0000 (SPI Reset) 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 1000,1111 1111,0100 Enable CQ Sense Mode 2874fb For more information www.linear.com/LTC2874 27 LTC2874 Applications Information Table 3. SPI Register Table REG 0xA 0xB 0xC 0xD 0xE NAME NSF ILLM D7 D6 D5 D4 CTRL2 D2 D1 D0 NSF4[1:0] NSF3[1:0] NSF2[1:0] NSF1[1:0] Noise Suppression Filter, Port 4: Noise Suppression Filter, Port 3: Noise Suppression Filter, Port 2: Noise Suppression Filter, Port 1: 00 = Disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s 00 = Disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s 00 = Disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s 00 = Disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s ILLM4[1:0] ILLM3[1:0] ILLM2[1:0] ILLM1[1:0] Sinking Current, Port 4: Sinking Current, Port 3: Sinking Current, Port 2: Sinking Current, Port 1: 00 = 500k 01 = 2.5mA 10 = 3.7mA 11 = 6.2mA 00 = 500k 01 = 2.5mA 10 = 3.7mA 11 = 6.2mA 00 = 500k 01 = 2.5mA 10 = 3.7mA 11 = 6.2mA 00 = 500k 01 = 2.5mA 10 = 3.7mA 11 = 6.2mA TMRCTRL LPTC[3:0] CTRL1 D3 Reserved 1111,1111 1111,1111 1000, 0101 RETRYTC[2:0] L+ Overcurrent Timer Control (Ports 1 to 4): Auto-Retry Timer Control (Ports 1 to 4): 0000 = 15s 0001 = 30s 0010 = 60s 0011 = 120s 0100 = 0.24ms 0101 = 0.5ms 0110 = 1.0ms 0111 = 2.0ms 000 = 0.12s 001 = 0.24s 010 = 0.5s 011 = 1.0s 100 = 2.0s 101 = 3.9s 110 = 7.9s 111 = 15.7s 1000 = 3.9ms 1001 = 7.8ms 1010 = 16ms 1011 = 30ms 1100 = 60ms 1101 = 0.12s 1110 = 0.25s 1111 = 0.25s WKUP4 WKUP3 WKUP2 WKUP1 DRVEN4 DRVEN3 DRVEN2 DRVEN1 Generate WURQ on CQ4 Generate WURQ on CQ3 Generate WURQ on CQ2 Generate WURQ on CQ1 Enable CQ4 driver Enable CQ3 driver Enable CQ2 driver Enable CQ1 driver ENL+4 ENL+3 ENL+2 ENL+1 SIO_MODE4 SIO_MODE3 SIO_MODE2 SIO_MODE1 Enable L+4 Power Supply Enable L+3 Power Supply Enable L+2 Power Supply Enable L+1 Power Supply CQ4 SIO Mode OC Timeout CQ3 CQ2 SIO Mode SIO Mode OC Timeout OC Timeout CQ1 SIO Mode OC Timeout 0 = 15s 1 = 480s 0 = 15s 1 = 480s 0 = 15s 1 = 480s 0 = 15s 1 = 480s DEFAULT 0000,0000 0000,0000 Notes: 1: Delays are typical unless otherwise noted. 2: Underlined settings are default values. 3: Gray shading indicates Read-Only register bits. 4: Register 0xD WKUP bits are pushbuttons that self-clear. 5: Reserved bits may be converted to features in a future release of the product. 28 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information Table 4. Summary of LTC2874 Event Reporting EVENT REGISTER/ EVENT BITS IRQREG MASK BIT BEHAVIOR NOTE Overtemperature Shutdown Level EVENT1 (0x2) OT_SD 7 Thermal Recovery Temperature has reached shutdown level. L+ and CQ pins are disabled until condition clears. Overtemperature Warning Level EVENT1 (0x2) OT_WARN 7 Thermal Recovery Temperature has reached warning level. Wake-up requests (WURQ) are blocked. VL Supply UVLO EVENT1 (0x2) SUPPLY 6 10ms Recovery VL below UVLO threshold for 10s. VDD Supply UVLO EVENT1 (0x2) SUPPLY 6 10ms Recovery VDD below UVLO threshold for 10s. VDD Supply UV EVENT1 (0x2) SUPPLY 6 Signal Event Only VDD Supply OV EVENT1 (0x2) SUPPLY 6 Latchoff or Auto-Retry VDD above OV threshold for 10s. L+ and CQ pins are disabled unless OV_ALLOW bit set. Wake-Up EVENT2 (0x3) WU 5 8.3ms Wait Wake-up request (WURQ) has started. Additional WURQs are blocked for 8.3ms. L+ Overcurrent Timeout EVENT2 (0x3) TOC_L+ 4 Latchoff or Auto-Retry Duration of L+ current limiting has exceeded programmable timeout. L+ Power Changed EVENT3 (0x4) PWRCHNG 3 Signal Event Only L+ power status has changed (10s filter). CQ Overcurrent Timeout EVENT3 (0x4) TOC_CQ 2 Latchoff or Auto-Retry Duration of current limiting has exceeded mode-dependent timeout. CQ Sense EVENT4 (0x5) CQ_SNS n/a CQ Receiver Output (Read Only) Indicates CQ level (inverted polarity like RXD) when CQ_SNS_MODE bit set high. Doesn't signal IRQ. Cable Sense EVENT4 (0x5) CSENSE 1 L+ Supply Turns On Signals cable or load detected when CSENSE_MODE bit set high. EVENT VDD below UV threshold for 10s. 2874fb For more information www.linear.com/LTC2874 29 LTC2874 Applications Information Event Signaling Driving Relays When an event bit is set, in most cases a bit corresponding to the event type also signals high in the IRQREG register (0x0). If the corresponding bit in the IRQMASK register (0x1) is high, the event causes the IRQ pin to pull low. The IRQ signal generates an interrupt to the host microcontroller, eliminating the need for continuous software polling. The IRQMASK register selects which events can gain the host's attention at a given time. Having 100mA drive capability, the CQ drivers are capable of energizing the coils of many relays. For some applications requiring higher current, the L+ lines may operate as low data rate outputs. Figure 39 shows an example of the L+ pins driving 0.5A relays, with the CQ lines connected as relay sense lines. CQ line drivers are disabled by pin-strapping TXEN1 through TXEN4 low, and CQ pin load currents are disabled by setting ILLM = 0x0 for each port. Activate any relay by setting its ENL+ bit high. The relay sense points are converted to logic levels at the RXD pins. If the CQ_SNS_MODE bit is set high, the sense points may be read from register 0x5 via the serial interface. SPI Receiver The serial interface monitors the CQ line interface pins if the CQ_SNS_MODE bit is set. The polarity of the four CQ_SNS bits matches the polarity of the RXD pins. These bits are reset low when CQ_SNS_MODE isn't enabled (default). Driving Light Bulbs The CQ drivers can safely drive small incandescent light bulbs. Use SIO mode (SIO_MODE = 1) and the fastest auto-retry delay (RETRY_CQ = 1, RETRYTC = 0x0). The drivers will pulse on and off while the filament initially draws high current as it heats up. Figure 29 shows typical waveforms. CM7387-ND 28V T1 CQ 10V/DIV 200ms/DIV Setting the 24VMODE bit high programs the receivers and L+ foldback for 24V operation per Figures 12 and 15. Table 5. Example Settings for IO-Link Compatibility REG VALUE DEFAULT NOTE 0x8 0x8F Y 0x9 0xF4 Y 32V VDD Overvoltage Threshold 0xA 0xFF Y 0.5s Noise Suppression Filters IO-Link Compatibility Mode Enabled; L+ Startup 2x Current Pulse Enabled 0xB 0xFF Y 6mA Sinking Currents 0xC 0x85 Y TOC_L+ Timer NOT Required to be Set Longer Than 62ms Startup Current Pulse Table 6 shows typical SPI register settings for operating the LTC2874 in a 12V application. 2874 F29 Figure 29. Driving an Incandescent Bulb Using SIO Mode and Auto-Retry Larger light bulbs can be driven if microcode defines a faster driver cooling interval between pulses during bulb ignition. Set RETRY_CQ = 0 and clear register 0x4 to begin each new pulse. Because this technique defeats built-in protection against driver self-heating, it must be applied carefully. 30 Table 5 shows typical register settings for IO-Link compatible operation. Applications Other than IO-Link -(CQ) 50mA/DIV IO-Link Compatible Operation Setting the 24VMODE bit low selects VDD-ratioed receiver thresholds (Figure 12) and L+ foldback optimized for 12V operation (Figure 15). Additionally, the WKUP register bits are deactivated. Table 6. Example Settings for 12V Application REG VALUE DEFAULT 0x8 0x5F N NOTE IO-Link Compatibility Mode Disabled; L+ Start-Up 2x Current Pulse Disabled 0x9 0xF0 N 18V VDD Overvoltage Threshold 0xA See Note - Noise Suppression Filtering as Needed 0xB 0x00 N Sinking Currents Disabled 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information Reverse Current Protection VDD To isolate the VDD input supply against reverse current from L+ outputs and isolate L+ pins against cable disturbances on other L+ outputs, use the approach shown in Figure 30. Add blocking diodes (D1-D4) to the MOSFET drains rather than sources to maximize the MOSFET VGS. When the L+ pins are configured with blocking diodes, 1F master-side L+ capacitors (C1-C4) are required to mitigate the increased ringing that can occur in cable-driving applications. Use a smaller value (100nF) for applications requiring cable detection. VDD 1F VDD 100F SENSE+ CQ1 CQ2 CQ3 CQ4 LTC2874 GND * *OPTIONAL TO EXTEND CQ OPERATING RANGE BELOW GROUND 2874 F31 Figure 31. TVS Diode Protection for CQ pins Figure 30 shows the placement of TVS diodes for protecting the L+ outputs, while Figure 31 shows how to protect the CQ pins. MOSFET Fault Detection LTC2874 The L+ supply outputs are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed MOSFET may short from source to drain, which will make the port appear to be on when it should be off. The LTC2874 will disable the port if an overcurrent timeout occurs. SENSE-1 D1 D2 D3 D4 GATE1 L+1 L+2 L+3 L+4 GND VDD C1 C2 C3 C4 2874 F30 Figure 30. Reverse Protection and TVS Diode Protection for L+ Outputs Surge and ESD Protection Considerations Cable interfaces are subject to significant ESD events because long cables can store large reservoirs of charge. The LTC2874 CQ and L+ line pins feature protection to 8kV HBM with respect to GND without latchup or damage during all modes of operation and while unpowered. All the other pins are protected to 6kV HBM. In order to further protect the LTC2874 interface ports against surge and contact/air discharge events based on the IEC 61000-4-5 standard, additional external protection is required. SM6T36A or equivalent TVS clamps are recommended for IO-Link and most other applications. In 24V applications in which the input supply tolerance does not exceed 15%, SM6T33A or equivalent clamps are also suitable. A failed MOSFET may also short from gate to source. This type of short will prevent the LTC2874 from enhancing the MOSFET. The host can detect this condition by the permanent absence of PWRGD. An open or missing MOSFET will similarly not produce PWRGD. Normally a damaged MOSFET will not affect other ports. However, if it causes the sense resistor RS to fuse open, the SENSE- pin will exceed its absolute maximum rating, which might damage the LTC2874. This condition is signalled to the host by an OC_L+ status bit that remains high even when the supply output is disabled (ENL+ = 0). Avoid this situation by performing adequate board-level short circuit testing and using surge-rated sense resistors. High Temperature Considerations For some applications, the PCB must provide heat sinking to keep the LTC2874 cool. Solder the exposed pad on the bottom of the package to ground and tie to large copper layers below using thermal vias. For more information www.linear.com/LTC2874 2874fb 31 LTC2874 Applications Information LTC2874 power dissipation can be estimated by considering the contributions of drivers and sinking currents for a given application, along with quiescent power dissipated by internal circuits operating from two supplies. In general, use the higher case of drive mode and receive mode (sinking current) and ignore the other. Calculate driver power dissipation by taking the product of CQ residual voltage and load current for each port. Here we also factor in worst-case limits and maximum possible DC loading on all ports: PD = 4 * MAX((ILL * VDD), (IRQH/L * VRQH/L)) + (VDD * IDD) + (VL * IL) PD = 4 * MAX((6.8mA * 34V), (0.23A * 1.6V)) + (34V * 8mA) + (5.5V * 1mA) = 1.75W For JA of 34C/W, the increase in junction temperature compared to ambient is 60C. The thermal shutdown circuit signals an OT_SD event and disables the drivers if the internal die temperature is above about 170C. The drivers turn back on when the internal die temperature drops approximately 15C. When the internal die temperature is above about 140C, the OT status bit and OT_WARN event bit signal, enabling an informed host to intervene. Layout Guidelines Standard power layout guidelines apply to the LTC2874: place the decoupling caps for the VDD and VL supplies near their respective supply pins, use ground planes, and use wide traces wherever there are significant currents. The main layout challenge involves the arrangement of the current sense resistors, and their connections to the LTC2874. Because the sense resistor values are small, layout parasitics can cause significant errors. Care is required to achieve specified accuracy. Figure 32 illustrates the problem. In example Figure 32A, two ports have load currents I1 and I2 that connect to VDD through a mutual resistance RM. RM represents the combined resistances of any traces, planes, and vias in 32 the PCB that I1 and I2 share. The LTC2874 measures the voltage difference between its SENSE+ and SENSE- pins to sense the voltage drop across RS1, but as the example shows, RM introduces errors. The second example (Figure 32B) shows how to minimize errors using good layout. The circuit is rearranged so that RM no longer affects VS, and the SENSE+ connection to the LTC2874 is used as a Kelvin sense trace. It is not a perfect Kelvin connection because all four ports controlled by the LTC2874 share the same sense trace, and because the current through the trace (IK) is not zero. However, as the equation in Figure 32(B) shows, the remaining error is a small offset term. Figure 33 shows two LTC2874 chips controlling eight ports (A through H). The ports are separated into two groups of four; each has its own trace on the top PCB layer that connects to the VDD plane through a via. Currents from the U1 sub-circuit are effectively isolated from the U2 subcircuit, reducing the layout problem down to 4-port subsections; this arrangement can be expanded for any number of ports. Figure 34 shows an example of good 4-port layout. In this case, each sense resistor consists of two resistors in parallel. The four groups of resistors are arranged to minimize the overlap in their current flows, reducing mutual resistance. Wide copper paths connect each group of resistors to the vias at the center. The SENSE+ Kelvin trace connects to the center of the resistor array. The via at the center of the sense resistor array has a matching hole in the VDD plane. This arrangement prevents the mutual resistance of the four large vias from influencing the current measurements and introducing errors. An alternative layout is shown in Figure 35. IO-Link Disclaimer Linear Technology Corporation attempts to maintain compatibility with the IO-Link interface and system specification. LTC is not a member of the IO-Link Consortium as set forth by PROFIBUS Nutzeroganisation (PNO) e.V. 2874fb For more information www.linear.com/LTC2874 LTC2874 Applications Information MUTUAL RESISTANCE I1 + I2 + IDD IDD RM VDD RM IDD I2 I1 VDD SENSE+ LTC2874 KELVIN SENSE LINE I1 + I2 + IDD IK SENSE+ +VS RS1 LTC2874 RS2 SENSE- SENSE- VS = I1RS1 + I1RM + I2RM SIGNAL SCALE ERROR CROSSTALK ERROR RK +VS RS1 RS2 I1 I2 VS = I1RS1 - IKRK SIGNAL SMALL OFFSET ERROR (A) (B) 2874 F32 Figure 32. Layout Affects Current Limit Accuracy: (A) Poor and (B) Good Layouts VDD COPPER FILL BY KEEPING THESE COPPER FILLS SEPARATE, MUTUAL RESISTANCE BETWEEN PORTS A TO D AND E TO H IS ELIMINATED. VDD COPPER PLANE VIAS VDD VIAS VIAS SENSE+ VDD LTC2874 VIAS SENSE+ LTC2874 SENSE-1 SENSE-1 SENSE -2 SENSE-2 SENSE -3 SENSE-3 SENSE-4 SENSE-4 U1 U2 PORTS A THROUGH D PORTS E THROUGH H 2874 F33 Figure 33. Layout Strategy to Reduce Mutual Resistance KELVIN SENSE TRACE CONNECTS TO U1 SENSE+ PIN PORT A RS PORT B RS FOUR LARGE VIAS TO VDD PLANE HOLE IN VDD PLANE U1 PORT D RS PORT C RS PIN 1 VIAS TO DRAIN PIN OF THE PORT C MOSFET LOCATED ON THE OPPOSITE SIDE OF THE BOARD Figure 34. Good PCB Layout Example For more information www.linear.com/LTC2874 2874 F34 2874fb 33 LTC2874 Applications Information LTC2874 Q2 CVDD1 Q3 A. Top Layer B. Inner Layer 2 GND VL C. Inner Layer 3 VDD D. Inner Layer 4 D2 RS1 RS2 RS4 RS3 D3 E. Inner Layer 5 F. Bottom Layer Figure 35. Demo Board DC1880A Layout Showing Sense Resistors (on Bottom Layer) and Two of Four MOSFETs 34 2874fb For more information www.linear.com/LTC2874 LTC2874 Typical Applications 8V TO 34V 100F 1F SENSE+ VDD LTC2874 VL 2.9V TO 5.5V SENSE-3 4.7k VCC IRQ SENSE-1 TXEN1 SENSE-4 TXEN2 GATE1 TXEN3 1F CQ1 TXD2 Q2 PORT 1 CQ2 TXD3 L+4 TXD4 CQ3 RXD1 CQ4 RXD4 GATE2 PORT 2 L+2 CS GATE3 SCK L+3 SDI SDO Q1 L+1 TXD1 GND 10 GATE4 TXEN4 C 0.2 SENSE-2 GND Q1, Q2: FQT7N10 2874 F36 Figure 36. 2-Port Configuration with Guaranteed 200mA CQ Drive Capability (and 200mA L+ Supply) 2874fb For more information www.linear.com/LTC2874 35 LTC2874 Typical Applications 8V TO 34V 100F 1F SENSE+ VDD LTC2874 VL 2.9V TO 5.5V SENSE-3 4.7k VCC IRQ SENSE-4 TXEN1 SENSE-1 TXEN2 GATE1 TXEN3 1F TXEN4 10 Q1 L+1 TXD1 CQ1 TXD2 C 0.1 SENSE-2 CQ2 TXD3 CQ3 TXD4 CQ4 GATE2 RXD1 GATE3 GATE4 CS L+2 SCK L+3 SDI GND SDO L+4 GND Q1: FQT7N10 2874 F37 Figure 37. 1-Port Configuration with Guaranteed 400mA CQ Drive Capability (and 400mA L+ Supply) 36 2874fb For more information www.linear.com/LTC2874 LTC2874 Typical Applications 8V TO 30V 1F VDD 100F SENSE+ LTC2874 VL 2.9V TO 5.5V 4.7k IRQ VCC 1F 4 4 4 TXENn 0.2 0.2 0.2 D1 D2 D3 D4 SENSE-1 SENSE-2 SENSE-3 SENSE-4 TXDn GATE1 RXDn GATE2 GATE3 CS C 0.2 GATE4 SCK SDI 10 Q1 10 Q2 10 Q3 10 Q4 DZ DZ DZ DZ L+1 SDO 1 4 CQ1 2 3 L+2 1 4 CQ2 2 3 L+3 1 4 CQ3 2 3 L+4 GND GND 1 4 CQ4 C1 C2 C3 3 C4 DZ DZ DZ D1 TO D4: SCHOTTKY DZ: SM6T36A Q1 TO Q4: FQT7N10 C1 TO C4: 1F (REQUIRED WHEN USING D1-D4) 2 DZ 2874 F38 Figure 38. Blocking Diodes D1-D4 Protect VDD Against Overvoltage Faults on L+ Outputs, TVS Diodes DZ Surge-Protect Cable Interface 2874fb For more information www.linear.com/LTC2874 37 LTC2874 Typical Applications 24V 1F VDD 100F SENSE+ LTC2874 VL 2.9V TO 5.5V 80m 80m 80m SENSE-1 4.7k SENSE-2 IRQ SENSE-3 VCC SENSE-4 1F 4 80m GATE1 RXDn 10 Q1 A L+1 C D1 CQ1 CS K1 B SCK SDI GATE2 SDO 10 Q2 A L+2 D2 CQ2 K2 B GATE3 10 Q3 A L+3 D3 CQ3 K3 B GATE4 TXENn TXDn GND 10 Q4 A L+4 GND CQ4 D4 K4 B 2874 F39 D1 TO D4: 1N4004 Q1 TO Q4: FQT7N10 Figure 39. SPI-Operated Quad Relay Driver (with CQ Relay Sense) Guaranteeing 0.5A Coil Current 38 2874fb For more information www.linear.com/LTC2874 LTC2874 Typical Applications SCLK SCK MOSI SDI MISO SDO SS1 CS IRQ1 IRQ LTC2874 L+ CQ GND L- 4 PORTS SCK C SDI LTC2874 SDO SS2 CS IRQ2 IRQ L+ CQ GND L- 4 PORTS * * * SCK SDI SDO SSn CS IRQn IRQ LTC2874 L+ CQ GND L- 4 PORTS 2874 F40 Figure 40. N-Port Master Hot Swap Controller and PHY 2874fb For more information www.linear.com/LTC2874 39 LTC2874 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev C) Exposed Pad Variation AA 4.75 REF 38 9.60 - 9.80* (.378 - .386) 4.75 REF (.187) 20 6.60 0.10 4.50 REF 2.74 REF SEE NOTE 4 6.40 2.74 REF (.252) (.108) BSC 0.315 0.05 1.05 0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 40 1 0.25 REF 19 1.20 (.047) MAX 0 - 8 0.50 (.0196) BSC 0.17 - 0.27 (.0067 - .0106) TYP 0.05 - 0.15 (.002 - .006) FE38 (AA) TSSOP REV C 0910 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 2874fb For more information www.linear.com/LTC2874 LTC2874 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm x 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 0.05 5.50 0.05 5.15 0.05 4.10 0.05 3.00 REF 3.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.5 REF 6.10 0.05 7.50 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 0.05 5.00 0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.00 REF 37 0.00 - 0.05 38 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 0.10 5.50 REF 7.00 0.10 3.15 0.10 (UH) QFN REF C 1107 0.200 REF 0.25 0.05 0.50 BSC R = 0.125 TYP R = 0.10 TYP BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2874fb For more information www.linear.com/LTC2874 41 LTC2874 Errata Erratum #1 Description In auto-retry mode, clearing the event register re-enables the faulted pin(s) and resets the entry timer, potentially interfering with duty cycle enforcement. Work-Arounds (a) Use latchoff mode. Interrupt service routine must limit duty cycle of faulted pin(s) per guidance given in the Auto-Retry or Latchoff Fault Response section. (b) Use auto-retry mode, clearing faults using an interrupt service time (TIS) that's long compared to the retry time (TIS > RETRYTC * 1.2). (c) Use auto-retry mode, clearing faults using an interrupt service time that's short compared to the retry time (TIS < RETRYTC * 0.8) while also limiting the maximum duty cycle per (a). 42 2874fb For more information www.linear.com/LTC2874 LTC2874 Revision History REV DATE DESCRIPTION PAGE NUMBER A 07/14 Lowered MOSFET gate resistor Increased Input Supply Voltage (Max) B 05/15 1, 13, 23, 35, 36, 37, 42 3 Lowered Input Low Threshold Voltage (Max) 4 Updated Cable Sense timer delay 22 Added "Operating Above 30V" Applications section 24 Changed capacitor values on slave port pins 42 Clarified L+ Supply Current Pulse Operation 21 Clarified PWRCHNG Event Behavior 21 Clarified Auto-Retry and Latchoff Mode Operation Added Erratum #1 24, 25 41 2874fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor of more information www.linear.com/LTC2874 tion that the interconnection its circuits as described herein will not infringe on existing patent rights. 43 LTC2874 Typical Application Complete 24V 3-Wire Power and COM3 Rate Signaling Interface to Sensor or Actuator (One of Four Available Master Ports is Shown) VOUT, IOUT** 5V, 100mA 2.9V TO 5.5V 53.6k VL 10.2k 0.1F 4.7k VDD 1F 100F SENSE+ 14k VLDO, ILDO** 3.3V, 100mA 20 METERS 0.2 SCK 1F SENSE-1 CS SDO GATE1 RXD1 TXEN1 L+1 TXD1 CQ1 GND RT BST 10 4.42k 200mA 100mA 4 4 Q1: FQT7N10 SURGE PROTECTION NOT SHOWN *ADDITIONAL BYPASS CAP AS NEEDED 5 33 1 2 2 3 RST FBLDO SC1 100mA 4 4.7F **IOUT(MAX), IS 100mA AND ILDO(MAX) IS 100mA (REMAINING AVAILABLE IOUT IS: 100mA - ILDO) 470pF 470pF SC2 DIO WAKE EN/UVLO RXD1 L+ 100mA 1 SYNC LDO AGND Q1 VOUT OR VLDO SR LDOIN VOUT IRQ C SW ILIM * SDI CPOR 0.1F 38.3k 24V 82H LT3669 0.1F 1/4 LTC2874 BD FBOUT 10F C TXEN1 Q2 TXD1 CQ1 TXEN2 GND TXD2 fW = 600kHz tRST = 12.5ms 2874 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LT3669/LT3669-2 Industrial Transceivers with Integrated Step Down Regulator and LDO Compatible with IO-Link Interface and System Specification, Operates from 7.5V to 40V, Integrated 100mA/300mA Buck and 150mA LDO LTC2854/LTC2855 3.3V 20Mbps RS485 Transceivers with Integrated Switchable Termination 3.3V Supply, Integrated, Switchable 120 Termination Resistor, 25kV ESD LTC2859/LTC2861 20Mbps RS485 Transceivers with Integrated Switchable Termination 5V Supply, Integrated, Switchable 120 Termination Resistor, 15kV ESD LTC2862/LTC2865 60V Fault Protected 3V to 5.5V RS485/ 20Mbps, Protected from Overvoltage Line Faults to 60V, 15kV ESD RS422 Transceivers LTC2870/LTC2871/ RS232/RS485 Multiprotocol 3V to 5.5V Supply, Automatic Selection of Termination Resistors, Duplex Control, Logic LTC2872 Transceivers with Integrated Termination Supply Pin, Up to 26kV ESD LTM2881 Complete Isolated RS485/RS422 Module(R) Transceiver + Power 3V or 5V Supply, 20Mbps, 2500VRMS Isolation with Integrated DC/DC Converter, Integrated Switchable 120 Termination Resistor, 15kV ESD LTM2882 Dual Isolated RS232 Module Transceiver + Power 3V or 5V Supply, 1Mbps, 2500VRMS Isolation with Integrated DC/DC Converter, 10kV ESD 44 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2874 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2874 2874fb LT 0515 REV B * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013