LTC2874
1
2874fb
For more information www.linear.com/LTC2874
Typical applicaTion
FeaTures DescripTion
Quad IO-Link Master
Hot Swap Controller
and PHY
The LT C
®
2874 provides a rugged, 4-port IO-Link power and
communications interface to remote devices connected
by cables up to 20m in length.
Output supply voltage and inrush current are ramped
up in a controlled manner using external N-channel
MOSFETs, providing improved robustness compared to
fully integrated solutions.
Wake-up pulse generation, line noise suppression, con-
nection sensing and automatic restart after fault conditions
are supported, along with signaling at 4.8kb/s, 38.4kb/s,
and 230.4kb/s.
Configuration and fault reporting are exchanged using
a SPI-compatible 4-wire interface that operates at clock
rates up to 20MHz.
The LTC2874 implements an IO-Link master PHY. For
IO-Link device designs, see the LT
®
3669.
Quad-Port 200mA Power Source and Signaling Interface
applicaTions
n IO-Link Masters
n Intelligent Sensors and Actuators
n Factory Automation Networks
L, LT , LT C , LT M , Linear Technology, the Linear logo, µModule are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. IO-Link is a registered trademark of
PROFIBUS User Organization (PNO). All other trademarks are the property of their respective
owners.
n IO-Link
®
Compatible (COM1/COM2/COM3)
n 8V to 34V Operation
n Hot Swap™ Controller Protected Supply Outputs
n Discrete Power MOSFETs for Ruggedness and
Flexibility
n Configurable 100mA (4-Port), 200mA (2-Port), or
400mA (1-Port) CQ Drive Capability
n Automatic Wake-Up Pulse Generation
n Automatic Cable Sensing
n CQ Pins Protected to ±50V
n Configurable L+ Current Limit with Foldback
n Short Circuit, Input UV/OV and Thermal Protection
n Optional Interrupt and Auto-Retry after Faults
n 2.9V to 5.5V Logic Supply for Flexible Digital Interface
n No Damage or Latchup to ±8kV HBM ESD
n 38-Lead (5mm × 7mm) QFN and TSSOP Packages
Operating Waveforms
SENSE+
VDD
VCC
µC
VL
IRQIRQ
SENSE–1
SENSE–2
SENSE–3
SENSE–4
TXENn
TXDn
RXDn
CS
SCK
SDI
SDO
GATE1
GATE2
GATE3
GATE4
L+1
CQ1
L+2
CQ2
L+3
CQ3
L+4
CQ4
LTC2874
8V TO 34V
2.9V TO 5.5V
2874 TA01a
GNDGND
4.7k
1µF
0.2Ω
10Ω
4
4
4
100µF 1µF
1
4
3
1
4
3
1
4
3
1
4
3
2
2
2
2
4µs/DIV
20V/DIV
LOAD: 4nF
CQ1, CQ3: SLEW = 0
CQ2, CQ4: SLEW = 1
2874 TA01b
CQ4
CQ1
CQ2
CQ3
LTC2874
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For more information www.linear.com/LTC2874
pin conFiguraTion
absoluTe MaxiMuM raTings
Input Supplies
VDD ........................................................ –0.3V to 40V
VL ............................................................ –0.3V to 6V
Input Voltages
CS, SCK, SDI, TXD .................................. –0.3V to 6V
TXEN ............................................ –0.3V to VL + 0.3V
CQ ................................................... VDD – 50V to 50V
GATE – L+ (Note 4) ................................ –0.3V to 10V
L+ ............................................................. –6V to 50V
SENSE+, SENSE– ......................VDD – 2V to VDD + 2V
(Notes 1, 2, 3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
TXEN4
GATE4
SENSE–4
L+4
CQ4
CQ3
GATE3
SENSE–3
L+3
SENSE+
VDD
GATE2
SENSE–2
L+2
CQ2
CQ1
GATE1
SENSE–1
L+1
TXD4
RXD4
TXEN3
TXD3
RXD3
CS
SCK
SDI
GND
GND
VL
TXEN2
TXD2
RXD2
SDO
IRQ
TXEN1
TXD1
RXD1
39
GND
TJMAX = 150°C, θJA = 25°C/W (NOTE 5)
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
13 14 15 16
TOP VIEW
39
GND
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1CQ4
CQ3
GATE3
SENSE–3
L+3
SENSE+
VDD
GATE2
SENSE–2
L+2
CQ2
CQ1
TXD3
RXD3
CS
SCK
SDI
GND
GND
VL
TXEN2
TXD2
RXD2
SDO
L+4
SENSE–4
GATE4
TXEN4
TXD4
RXD4
TXEN3
GATE1
SENSE–1
L+1
RXD1
TXD1
TXEN1
IRQ
23
22
21
20
9
10
11
12
TJMAX = 150°C, θJA = 34°C/W (NOTE 5)
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
Output Voltages
GATE .......................................... –0.3V to (VL+) + 15V
IRQ .......................................................... –0.3V to 6V
RXD, SDO ..................................... –0.3V to VL + 0.3V
Operating Temperature Range
LTC2874I ..............................................–40°C to 85°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package ....................................................... 300°C
LTC2874
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For more information www.linear.com/LTC2874
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2874IFE#PBF LTC2874IFE#TRPBF LTC2874FE 38-Lead Plastic TSSOP –40°C to 85°C
LTC2874IUHF#PBF LTC2874IUHF#TRPBF 2874 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges.
Consult LT C Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
VDD Input Supply Operating Range 24VMODE = 0
24VMODE = 1
l
l
8
20
34
34
V
V
IDD VDD Input Supply Current, All
Ports Enabled
DRVEN = 0xF, ENL+ = 0xF, ILLM = 0x0 l5 8 mA
VDD(UVL) UV Lockout VDD Rising l5.5 6 6.5 V
UV Lockout Hysteresis 0.13 V
VDD(UVTH) UV Bit Threshold VDD Rising
24VMODE = 1
24VMODE = 0
l
l
16.2
6.8
16.8
7.1
17.4
7.4
V
V
UV Bit Threshold Hysteresis 0.2 V
VDD(OVTH) OV Bit Threshold VDD Rising, OV_TH = 0x1 l31 32 33 V
OV Bit Threshold Hysteresis 0.4 V
Logic Supply
VLLogic Supply Range l2.9 5.5 V
ILVL Logic Supply Current Digital Inputs at 0V or VLl0.1 1 mA
L+ Power Supply Output
VL+(PGTH) L+ Power Good Threshold VL+(PGTH) = VDD – V(L+) l1.2 1.5 1.9 V
L+ Power Good Hysteresis 100 mV
ΔVCB(TH) Circuit Breaker Threshold ΔVCB(TH) = V(SENSE+) – V(SENSE–) (Note 7) ΔVACL – 0.8 mV
ΔVACL Analog Current Limit Voltage ΔVACL = V(SENSE+) – V(SENSE–)
V(L+) = 0V, FLDBK_MODE = 1
V(L+) = VDD – 1V
Start-Up, 2XPTC Enabled, V(L+) > 18V (Note 7)
l
l
9.2
42
16.7
50
100
24.2
58
mV
mV
mV
tOC(L+) L+ Pin OC Fault Filter V(SENSE+) – V(SENSE–) = 250mV,
LPTC = 0x03 (Figure 1)
l110 122.5 135 µs
tD(ACL) ΔVSENSE to GATE Low V(SENSE+) – V(SENSE–) = 250mV,
LPTC = 0x03 (Figure 1)
CG = 0nF
CG = 10nF
l
19
24
25
µs
µs
Start-Up Current Pulse Duration 2XPTC = 0x0 l52 62 72 ms
SENSE– Pin Input Current V(SENSE–) = 24V l0 10 25 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset
to their default states. (Note 2)
LTC2874
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For more information www.linear.com/LTC2874
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Drive
ΔVGATE External N-Channel Gate Drive
(VGATE – VL+)
I(GATE) = –1µA
VDD = 17V to 30V
VDD = 8V
l
l
10
4.5
13
15
15
V
V
IGATE(UP) GATE Pin Output Current,
Sourcing
V(SENSE+) – V(SENSE–) = 0V, V(GATE) = 1V l–10 –14 –20 µA
IGATE(DN) GATE Pin Output Current, Sinking ENL+ = 0, V(GATE) = 10V 1.2 mA
IGATE(LIM) Pull-Down Current from GATE to
SOURCE During UVLO or L+ OC
Timeout Event
V(SENSE+) – V(SENSE–) = 0.2V, ΔVGATE = 10V 90 mA
(VGATE – VL+) for Power Good V(L+) = 8V to 30V l3.0 3.8 4.5 V
CQ Line Driver
VRQH, VRQL Residual Voltage (Note 6) Output High, I(CQ) = –100mA
Output Low, I(CQ) = 100mA
l
l
1.2
1.1
1.6
1.5
V
V
IQPKH, IQPKL Wake-Up Request (WURQ)
Current
(Figure 2) l±500 ±700 mA
IQH, IQL Current Limit (Figure 3) l±110 ±160 ±230 mA
tOC(CQ) Overcurrent Timeout CL = 100pF, VDD – CQ or CQ = 5V (Figure 3)
SLEW = 0, SIO_MODE = 0
SLEW = 1, SIO_MODE = 0
l
l
13
13
24
24
µs
µs
CQ Line Receiver
VTHH Input High Threshold Voltage 24VMODE = 1
24VMODE = 0
l
l
10.5
0.5 • VDD
11.9 13
0.7 • VDD
V
V
VTHL Input Low Threshold Voltage 24VMODE = 1
24VMODE = 0
l
l
8
0.3 • VDD
9.4 11
0.5 • VDD
V
V
VHYS Input Hysteresis 24VMODE = 1
24VMODE = 0
l
l
2.0
0.05 • VDD
2.5 2.9
0.2 • VDD
V
V
Input Resistance V(CQ) = VDD – 1V, ILLM = 0x0 l390 510 630 kΩ
VOH Output High Voltage I(RXD) = –100µA lVL – 0.4 V
VOL Output Low Voltage I(RXD) = 100µA l0.4 V
Digital I/O
Input Threshold Voltage 2.9V ≤ VL ≤ 5.5V l0.33 • VL0.67 • VLV
Input Leakage Current 0V ≤ VIN ≤ VL
CS, TXD
SCK, SDI, TXEN
l
l
–10
–1
1
10
µA
µA
Input Capacitance (Note 7) l2.5 pF
VOH(SDO) SDO Output High Voltage I(SDO) = –1mA lVL – 0.4 V
VOL(SDO) SDO Output Low Voltage I(SDO) = 1mA l0.4 V
VOL(IRQ)IRQ Open Drain Output Low
Voltage
I(IRQ) = 3mA
I(IRQ) = 5mA
l
l
0.4
0.7
V
V
Other Pin Functions
ILL Receive-Mode Load/Discharge
Current
ILLM = 0x3, 0V ≤ V(CQ) ≤ 5V
ILLM = 0x3, 5V < V(CQ) ≤ 30V
ILLM = 0x2, 5V < V(CQ) ≤ 30V
ILLM = 0x1, 5V < V(CQ) ≤ 30V
l
l
l
l
0
5
3.2
2.2
6.2
6.2
3.7
2.5
6.8
6.8
4.2
2.8
mA
mA
mA
mA
Input to GATE Off Propagation
Delay
ENL+
UVLO_VDD (Note 7) or OV_VDD Event
l
l
2
10
4
15
µs
µs
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset
to their default states. (Note 2)
LTC2874
5
2874fb
For more information www.linear.com/LTC2874
swiTching characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VDD = 24V, VL = 3.3V, and registers are reset
to their default states.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
GATE Turn-On Delay l10 20 µs
tRETRY Auto-Retry Delay RETRYTC = 0x5 3.9 s
ESD Protection
CQ and L+ Pins
All Other Pins
Human Body Model (Note 7)
±8
±6
kV
kV
Driver and Receiver
fDTR Maximum Data Transfer Rate CL = 4nF
SLEW = 0
SLEW = 1
l
l
38.4
230.4
kb/s
kb/s
TBIT Bit Time SLEW = 0
SLEW = 1
26.04
4.34
µs
µs
CCQ CQ Pin Input Capacitance (Note 7) 100 pF
Driver
tDR, tDF Rise or Fall Time SLEW = 0 (Figure 4)
CL = 100pF
CL = 4nF
l
l
3
3
5.2
5.2
µs
µs
SLEW = 1 (Figure 4)
CL = 100pF
CL = 4nF
l
l
0.5
0.5
0.869
0.869
µs
µs
tPHLD, tPLHD Propagation Delay CL = 100pF (Figure 5)
SLEW = 0
SLEW = 1
l
l
4
1.3
8
3
µs
µs
tSKEWD Skew CL = 100pF (Figure 5)
SLEW = 0
SLEW = 1
0.5
0.5
µs
µs
tZHD, tZLD Enable Time RL = 10kΩ, CL = 100pF, ILLM = 0x0 (Figure 6)
SLEW = 0
SLEW = 1
l
l
12
3
µs
µs
tHZD, tLZD Disable Time RL = 10kΩ, CL = 100pF, ILLM = 0x0 (Figure 6) l3 µs
tWUDLY Wake-Up Request (WURQ) Delay (Figure 2) l7.5 20 µs
tWU WURQ Pulse Duration (Figure 2) l75 80 85 µs
WURQ Cooldown Timer l8.3 10 ms
Receiver
tH, tLDetection Time (Figure 7)
TBIT = 208.3µs (COM1), NSF = 0x1
TBIT = 26.0µs (COM2), NSF = 0x2
TBIT = 4.34µs (COM3), NSF = 0x3
l
l
l
1/16
1/16
1/16
1/10
1/9
1/7
TBIT
TBIT
TBIT
tND Noise Suppression Time (Figure 8, Note 9)
TBIT = 208.3µs (COM1), NSF = 0x1
TBIT = 26.0µs (COM2), NSF = 0x2
TBIT = 4.34µs (COM3), NSF = 0x3
l
l
l
1/10
1/9
1/7
1/16
1/16
1/16
TBIT
TBIT
TBIT
tPHLR, tPLHR Receiver Propagation Delay NSF = 0x0, CL = 100pF (Figure 7) l200 600 ns
tSKEWR Receiver Skew NSF = 0x0, CL = 100pF (Figure 7) 100 ns
LTC2874
6
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For more information www.linear.com/LTC2874
Operation at 230.4kb/s (COM3)
and 38.4kb/s (COM2) Driver Eye Diagram (COM3) CQ Residual Voltage vs VDD
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 24V, VL = 2.9V to 5.5V unless otherwise noted. (See Figure 9) (Note 7)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SPI Interface
tSU CS to SCK Set-Up Time l7 ns
tHD SCK Falling to CS Hold Time l7 ns
tCH SCK High Time l19 ns
tCL SCK Low Time l19 ns
tDS SDI Set-Up Time l4 ns
tDH SDI Hold Time l4 ns
tDO SCK Falling to SDO Valid C(SDO) = 10pF
4.5V ≤ VL ≤ 5.5V
2.9V ≤ VL < 4.5V
l
l
20
40
ns
ns
SCK Frequency 50% Duty Cycle (Note 8) l20 MHz
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltages are with respect to GND. All currents into device pins
are positive; all currents out of device pins are negative.
Note 3. Numerical subscripts corresponding to port number are
sometimes omitted from pin names for brevity.
Note 4. An internal clamp limits each GATE pin to a minimum of 10V
above its respective L+ pin. Externally driving these pins to voltages
beyond the clamp may damage the device.
Note 5. This IC includes current limiting and overtemperature protection
that are intended to protect the device during momentary overload
conditions. Junction temperature can exceed the rated maximum
during current limiting. Overtemperature protection will become active
at a junction temperature greater than the rated maximum operating
temperature. Continuous operation above the specified maximum
operating junction temperature may impair device reliability.
Note 6. Residual voltages are defined as follows: VRQH = VDD – V(CQ), and
VRQL = V(CQ) – V(GND).
Note 7. Guaranteed by design and not production tested.
Note 8. SCK frequency is limited by SDO propagation delay as follows:
tSCK ≥ 2 • (tDO + ts), where ts is the setup time of the receiving device.
Note 9. Guaranteed by production testing of tH and tL.
Typical perForMance characTerisTics
TA = 25°C, VDD = 24V, VL = 3.3V, unless
otherwise noted.
VDD SUPPLY VOLTAGE (V)
5
RESIDUAL VOLTAGE (V)
1.2
1.3
1.4
25 30
2874 G03
1.1
1.0 10 15 20 35
VRQL
85°C
25°C
–40°C
ICQ = ±100mA
VRQH
1µs/DIV
10V/DIV
PRBS = 28 – 1
CQ1: LOAD = 4nF
CQ4: 20m CABLE + 1nF + 300Ω
CQ2, CQ3: ASYNCHRONOUS COM3 SWITCHING
L+1 TO L+4: ENABLED AND BYPASSED AT FAR END
2874 G02
CQ1 NO CABLE
20m CABLE
(FAR END)
CQ4
10µs/DIV
20V/DIV
LOAD: 4nF
CQ1, CQ3: SLEW = 0
CQ2, CQ4: SLEW = 1
2874 G01
CQ1
CQ2
CQ3
CQ4
LTC2874
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For more information www.linear.com/LTC2874
Typical perForMance characTerisTics
Driver Current Limit vs
Temperature CQ Short Circuit Protection Driver Enable/Disable
Driving 20m Cable to 1µF Load
Driver Propagation Delay vs
Temperature
CQ Driver Short-Circuit Current vs
Short-Circuit Voltage
CQ Pin Current
Wake-Up Pulse Width vs
Temperature Wake-Up Current vs Temperature
4µs/DIV
10V/DIV
5V/DIV
500mA/DIV
TXD = GND
SIO_MODE = 0
LOAD: 50pF
2874 G05
CQ SHORT
TO GND
CIRCUIT
BREAKER
IRQ
–I(CQ)
CQ PIN VOLTAGE (V)
–60
CURRENT (mA)
120
160
200
20 40
2874 G09
80
40
0
–200
–40
–80
–120
–160
–40 –20 060
VDD = 30V
VDD = 8V
BEFORE TIME-OUT
OUTPUT
HIGH
OUTPUT
LOW
ABSMAX
TA = 25°C, VDD = 24V, VL = 3.3V, unless
otherwise noted.
TEMPERATURE (°C)
–50
PULSE WIDTH (µs)
85.0
50 75
2874 G11
82.5
75.0
80.0
77.5
–25 025 100
IQPKL PULSE, VDD = 30V
IQPKL PULSE, VDD = 20V
IQPKH PULSE, VDD = 30V
IQPKH PULSE, VDD = 20V
LOAD = 26Ω TO GND OR VDD
TEMPERATURE (°C)
–50
CURRENT (mA)
1000
50 75
2874 G12
900
400
700
600
800
500
–25 025 100
IQPKL, VDD = 30V
IQPKL, VDD = 20V
IQPKH, VDD = 30V
IQPKH, VDD = 20V
LOAD = 26Ω TO GND OR VDD
100µs/DIV
10V/DIV
5V/DIV
10V/DIV
NSF = 0x2
SLEW = 0
SIO_MODE = 1
2874 G07
CQ (NEAR END)
CQ (FAR END)
RXD (NEAR END)
2µs/DIV
2V/DIV
10V/DIV
SLEW = 1, ILLM = 0x0
LOAD: 100pF (GND) + 10kΩ (VDD OR GND)
2874 G06
TXEN
CQ (TXD LOW)
CQ (TXD HIGH)
TEMPERATURE (°C)
–50
DELAY (µs)
4
5
6
50 75
2874 G08
3
2
1
0–25 025 100
LOAD = 100pF
SLEW = 0
SLEW = 1
tPLHD
tPHLD
CQ PIN VOLTAGE (V)
–60
CURRENT (µA)
100
140
20 40
2874 G10
60
20
–140
–20
–60
–100
–40 –20 060
85°C
–40°C
VDD = 8V
VDD = 30V
VDD – V(CQ) = 50V
ILLM = 0
DRIVER OFF
TEMPERATURE (°C)
–50
CURRENT (mA)
600
800
1000
50 75
2874 G04
400
200
0–25 025 100
FOUR CONNECTED CQ PINS
TWO CONNECTED CQ PINS
EACH CQ PIN
–IQH
IQL
LTC2874
8
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For more information www.linear.com/LTC2874
L+ Start-Up with 100µF Load
L+ Start-Up (Set by CG) and
Disable 2X Current Pulse at 18V
Typical perForMance characTerisTics
Wake-Up Pulse: IQPKH Wake-Up Pulse: IQPKL
Receiver Output Voltage vs Load
Current
Receiver Input Threshold vs
Temperature
Receiver Propagation or Filter
Delay vs Temperature
Receiver Pulse Rejection and
Detection Delay vs Temperature
20µs/DIV
5V/DIV
5V/DIV
10V/DIV
CQ LOAD: 4nF + 100Ω
2874 G13
16th SCK
CQ
IRQ
20µs/DIV
5V/DIV
5V/DIV
10V/DIV
CQ LOAD: 4nF + 100Ω
2874 G14
16th SCK
CQ
IRQ
TA = 25°C, VDD = 24V, VL = 3.3V, unless
otherwise noted.
TEMPERATURE (°C)
–50
DELAY (µs)
23
50 75
2874 G17
22
0
20
4
3
2
21
1
–25 0 25 100
RISING RXD
FALLING RXD
NSF = 0x1
LOAD = 100pF
NSF = 0x2
NSF = 0x3
NSF = 0x0
TEMPERATURE (°C)
–50
PULSE WIDTH (µs)
23
50 75
2874 G18
22
0
20
4
3
2
21
1
–25 0 25 100
DETECTED
REJECTED
NSF = 0x1
VL = 2.9V TO 5.5V
NSF = 0x2
NSF = 0x3
4ms/DIV
10V/DIV
2XPTC = 0x1
LPTC = 0xB
2874 G19
FLDBK_MODE = 1
FLDBK_MODE = 0
L+1
L+2
L+3
L+4
LOAD CURRENT (mA)
0.0
VOLTAGE (V)
0.5
0.3
2874 G15
0.4
0.0
0.2
0.3
0.1
0.1 0.2 0.4
VL = 2.9V
VL = 3.3V
VL = 5V
VL – VOH
VOL
TEMPERATURE (°C)
–50
THRESHOLD VOLTAGE (V)
13
50 75
2874 G16
12
8
10
11
9
–25 0 25 100
VDD = 30V
VDD = 20V
VTHH
VTHL
24VMODE = 1
40ms/DIV
10V/DIV
2XPTC = 0x1
FLDBK_MODE = 0
LOAD: 10µF
LPTC = 0xD
CG: 22nF
2874 G20
L+1
L+2
L+3
L+4
100ms/DIV
10V/DIV
200mA/DIV
2XPTC = 0x0
FLDBK_MODE = 0
LOAD: 3500µF
2874 G21
L+
–(L+)
LTC2874
9
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For more information www.linear.com/LTC2874
Typical perForMance characTerisTics
IGATE(UP) vs Temperature
External MOSFET VGS (∆VGATE) vs
Temperature L+ Overcurrent Behavior
L+ Current Limit Sense Voltage vs
Temperature
L+ Power Good Threshold vs
Temperature
Logic Input Threshold vs
VL Supply Voltage
VDD Overvoltage Indicator vs
Temperature
L+ Overcurrent Circuit Breaker
Delay vs ∆VSENSE Duty Cycle
ILL Sinking Current vs
CQ Voltage
TEMPERATURE (°C)
–50
CURRENT (µA)
–14.4
50 75
2874 G22
–13.6
–14.0
–13.8
–14.2
–25 0 25 100
VDD = 30V
VDD = 20V
VDD = 8V
FOUR PORTS ON
TEMPERATURE (°C)
–50
∆VGATE (V)
14.0
50 75
2874 G23
12.0
13.0
12.5
13.5
–25 0 25 100
VDD = 30V
VDD = 20V
VDD = 8V
FOUR PORTS ON
TA = 25°C, VDD = 24V, VL = 3.3V, unless
otherwise noted.
TEMPERATURE (°C)
–50
SUPPLY VOLTAGE (V)
40
50 75
2874 G28
30
34
38
36
32
–25 0 25 100
VDD = RISING
OV_TH = 0x3
OV_TH = 0x2
OV_TH = 0x1
TEMPERATURE (°C)
–50
VDD – L+ (V)
1.8
50 75
2874 G26
1.2
1.5
1.6
1.7
1.4
1.3
–25 0 25 100
VDD = 30V
VDD = 20V
VDD = 8V
RISING L+
FALLING L+
CQ PIN VOLTAGE (V)
0
CURRENT (mA)
8
30 40
2874 G29
0
6
4
2
10 20 50
INPUT
RESISTANCE
ILLM = 0x3
ILLM = 0x2
ILLM = 0x1
ILLM = 0x0
TA = 85°C
TA = 25°C
TA = –40°C
VL SUPPLY VOLTAGE (V)
2.5
THRESHOLD VOLTAGE (V)
3.0
4.5 5.0
2874 G27a
1.0
2.0
2.5
1.5
3.0 3.5 4.0 5.5
TA = 85°C
TA = 25°C
TA = –40°C
INPUT LOW
INPUT HIGH
DUTY CYCLE (%)
0
DELAY (ms)
10000
80
2874 G27b
0.01
100
10
1
1000
0.1
20 40 60 100
LPTC = 0xF
LPTC = 0x8
LPTC = 0x4
LPTC = 0x2
LPTC = 0x1
LPTC = 0x0
100µs/DIV
10V/DIV
5V/DIV
500mA/DIV
LPTC = 0x4
IRQMASK = 0xF6
FLDBK_MODE = 0
LOAD: 50pF
2874 G24
L+
IRQ
LOAD
STEP
(8Ω)
–I(L+) CIRCUIT
BREAKER
TEMPERATURE (°C)
–50
∆VACL (mV)
18.0
50 75
2874 G25
15.0
16.5
17.0
16.0
15.5
17.5
–25 0 25 100
VDD = 30V
VDD = 20V
VDD = 8V
V(L+) = 0V
FLDBK_MODE = 1
LTC2874
10
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For more information www.linear.com/LTC2874
Typical perForMance characTerisTics
VDD Supply Current vs Supply
Voltage VDD Supply Current vs Data Rate
SDO Voltage vs Load Current
CQ Driver Edge Time vs Supply
Voltage Driving 12V Relay Coils
TA = 25°C, VDD = 24V, VL = 3.3V, unless
otherwise noted.
VDD SUPPLY VOLTAGE (V)
5
SUPPLY CURRENT (mA)
70
20 25
2874 G30
0
20
10
60
50
40
30
10 15 3530
CQ1 TO CQ4 SWITCHING 1010,
L+1 TO L+4 ENABLED
SIO, 0.6kb/s, 1µF
COM2, 0.05nF
COM2. 4nF
COM2, 10nF
COM3, 0.05nF
COM3, 1nF
COM3, 4nF
DATE RATE (kb/s)
0
SUPPLY CURRENT (mA)
70
150 200
0
20
10
60
50
40
30
50 100 250
4nF
1nF
VDD = 30V
VDD = 20V COM3
COM2
0.05nF
COM1
CQ1 TO CQ4 SWITCHING 1010
L+1 TO L+4 ENABLED
LOAD CURRENT (mA)
0
VOLTAGE (V)
6
3 4 5 6 7
2874 G32
0
2
1
5
4
3
128
VL = 5V
VL = 3.3V
VL = 2.9V
VDD SUPPLY VOLTAGE (V)
5
EDGE TIME (µs)
15 20 25
2874 G33
0
2
1
5
4
3
10 3530
RISING
FALLING
LOAD = 100pF
SLEW = 1
SLEW = 0
20ms/DIV
10V/DIV
24VMODE = 0
SLEW = 0
SIO_MODE = 1
RELAYS: G2R-1-E-T130 DC12 + CATCH DIODE
2874 G34
CQ1
CQ2
CQ3
CQ4
LTC2874
11
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For more information www.linear.com/LTC2874
pin FuncTions
CQ2 (Pin 15/Pin 11): Port 2 C/Q line. See CQ1.
CQ1 (Pin 16/Pin 12): Port 1 Bidirectional Communication
or Signaling (C/Q) Line. When the port 1 driver is enabled
(either by TXEN1 or under SPI control), this pin is an output
referenced to GND, inverted in polarity with respect to the
TXD1 input. Otherwise, this pin is an input that a remote
device may drive and an optional, programmable current
sink is active. Receiver output RXD1 monitors this pin in
both cases.
GATE1 (Pin 17/Pin 13): Gate Drive for External N-Channel
MOSFET, Port 1. When the MOSFET is turned on, a 14µA
current drives the gate to 13V above the L+1 output supply
voltage. During a current limit condition, the voltage at
GATE1 reduces to maintain constant L+ port current. If a
timer expires, GATE1 pulls down, turning off the MOSFET,
and a TOC_L+ event is recorded.
SENSE–1 (Pin 18/Pin 14): L+1 Supply Current Sense
Negative Input. An external sense resistor, RS1 (normally
0.2Ω), connected between this pin and SENSE+ programs
the load current limit (∆VACL/RS1). Current is controlled by
an analog current limit amplifier and timed circuit breaker.
See L+ PIN POWER CONTROL in the Applications Infor-
mation section. Tie to VDD if unused. Do not leave open.
L+1 (Pin 19/Pin 15): Port 1 Output Supply Monitor and
Source Connection. Connect this pin to the source of the
external MOSFET for port 1.
RXD1 (Pin 20/Pin 16): Port 1 Data Output from CQ1
Receiver, Referenced to VL. Active even when the driver
is on. RXD1 polarity is inverted with respect to the line
data at the CQ1 pin.
(FE/UHF)
TXEN4 (Pin 1/Pin 35): Port 4 CQ4 Driver Enable. See
TXEN1.
GATE4 (Pin 2/Pin 36): Port 4 Gate Drive. See GATE1.
SENSE–4 (Pin 3/Pin 37): L+4 Supply Current Sense Nega-
tive Input. See SENSE–1.
L+4 (Pin 4/Pin 38): Port 4 Power Supply Output. See
L+1.
CQ4 (Pin 5/Pin 1): Port 4 C/Q line. See CQ1.
CQ3 (Pin 6/Pin 2): Port 3 C/Q line. See CQ1.
GATE3 (Pin 7/Pin 3): Port 3 Gate Drive. See GATE1.
SENSE–3 (Pin 8/Pin 4): L+3 Supply Current Sense Nega-
tive Input. See SENSE–1.
L+3 (Pin 9/Pin 5): Port 3 Power Supply Output. See
L+1.
SENSE+ (Pin 10/Pin 6): L+ Current Sense Common
Positive Input. Connect external sense resistors RS1
through RS4, normally 0.2Ω, between this pin and each
of the SENSE– pins in a star configuration. See Applica-
tions Information. Tie to VDD if unused. Do not leave
open.
VDD (Pin 11/Pin 7): Supply Voltage Input (8V to 34V).
Bypass to GND with a 1µF ceramic capacitor placed near
the pin and at least 100µF additional bulk capacitance.
GATE2 (Pin 12/Pin 8): Port 2 Gate Drive. See GATE1.
SENSE–2 (Pin 13/Pin 9): L+2 Supply Current Sense Nega-
tive Input. See SENSE–1.
L+2 (Pin 14/Pin 10): Port 2 Power Supply Output. See
L+1.
LTC2874
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For more information www.linear.com/LTC2874
pin FuncTions
(FE/UHF)
TXD1 (Pin 21/Pin 17): Port 1 Data Input to CQ1 Driver,
Referenced to VL. Tie to VL if unused.
TXEN1 (Pin 22/Pin 18): Port 1 CQ1 Driver Enable, Refer-
enced to VL. Tie to GND if unused.
IRQ (Pin 23/Pin 19): Interrupt Output. Open drain output
that pulls low to alert the host microcontroller when
an event occurs, eliminating the need for continuous
software polling. Disable individual IRQ events using the
IRQMASK register. IRQ typically has a pull-up resistor to VL.
SDO (Pin 24/Pin 20): SPI Interface Data Output, Refer-
enced to VL.
RXD2 (Pin 25/Pin 21): Port 2 Data Output from CQ2
Receiver. See RXD1.
TXD2 (Pin 26/Pin 22): Port 2 Data Input to CQ2 Driver.
See TXD1.
TXEN2 (Pin 27/Pin 23): Port 2 CQ2 Driver Enable. See
TXEN1.
VL (Pin 28/Pin 24): Logic supply (2.9V to 5.5V) for the
control logic, registers, receiver outputs, driver inputs,
and SPI interface. Bypass to GND with at least a 0.1µF
capacitor.
GND (Pins 29, 30, Exposed Pad Pin 39/Pins 25, 26, Ex-
posed Pad Pin 39): Device Ground. The exposed pad metal
of the package provides both electrical contact to ground
and good thermal contact to the PCB. Solder to the board
and tie directly to the ground plane using thermal vias.
SDI (Pin 31/Pin 27): SPI Interface Data Input, Referenced
to VL. Tie to GND if unused.
SCK (Pin 32/Pin 28): SPI Interface Clock Input, Referenced
to VL. Tie to GND if unused.
CS (Pin 33/Pin 29): SPI Interface Chip Select Input (Ac-
tive Low), Referenced to VL. Tie to VL if unused.
RXD3 (Pin 34/Pin 30): Port 3 Data Output from CQ3
Receiver. See RXD1.
TXD3 (Pin 35/Pin 31): Port 3 Data Input to CQ3 Driver.
See TXD1.
TXEN3 (Pin 36/Pin 32): Port 3 CQ3 Driver Enable. See
TXEN1.
RXD4 (Pin 37/Pin 33): Port 4 Data Output from CQ4
Receiver. See RXD1.
TXD4 (Pin 38/Pin 34): Port 4 Data Input to CQ4 Driver.
See TXD1.
LTC2874
13
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For more information www.linear.com/LTC2874
block DiagraM
SLEW1
DRVEN1
VL
CS
SCK
SDI
SDO
TXEN1
SENSE–2
GATE2
L+2
CQ2
SENSE–3
GATE3
L+3
CQ3
SENSE–4
GATE4
L+4
CQ4
TXEN2
TXD2
RXD2
TXEN3
TXD3
RXD3
TXEN4
TXD4
RXD4
TXD1
RXD1
WKUP1
PORT 2
PORT 1
PORT 3
PORT 4
NSF1
IRQ
CVL
0.1µF
4.7k
2.9V TO 5.5V
2874 BD
SENSE+
8V TO 34V
SENSE–1
VDD
CONTROL AND
MONITORING
REGISTERS
UVLO AND
SUPPLY
MONITORS
THERMAL
PROTECTION
CHARGE
PUMP
TO GATE DRIVERS
VDD – 1.5V
ENL+1 L+1
CQ1
18V
WAKEUP
GENERATION
DRIVER
CONTROL
DRIVER
CONTROL
FAULT
CONTROL
FOLDBACK
16.7mV TO 50mV
2X
PULSE
PWRGD1
GATE1
CABLE
SENSE
FAULT
CONTROL
GATE
DRIVER
SPI
OV_VDD
UV_VDD
UVLO_VDD
UVLO_VL
RCVR
FILTER
+
–
ILLM1
GND
CVDD1
1µF
RS1
0.2Ω
RGATE1
10Ω Q1
1 OF 4
CABLES
CVDD2
100µF
–
+
–
+
–
+
–
+
ACL
LTC2874
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For more information www.linear.com/LTC2874
TesT circuiTs / TiMing DiagraMs
Figure 1. L+ Pin Overcurrent
Figure 2. Wake-Up Parameters
Figure 3. CQ Pin Overcurrent
Figure 4. Driver Edge Rate
2874 F03
tOC(CQ)
50%
50%
VDD – CQ
OR CQ
GND
OR
VL
TXD
VDD – 5V
OR
5V
TXEN
VL
CQ
I(CQ)
IRQ
0V
0A
VOL(IRQ)
VL
5V
–IQH OR IQL
A
+
–
2874 F04
TXD CQ
TXEN
VL
CL
TXD
CQ 90%
10%
90%
10%
0V
VRQL
VDD – VRQH
VL
tDF tDR
2874 F01
tD(ACL)
∆VCB(TH)
∆VSENSE
IRQ
∆VGATE
tOC(L+)
250mV
0V
13V
2V 0V
VL
VOL(IRQ)
50%
2874 F02
tWUDLY
50%
SCK
(16th CLOCK)
CS
SCK
TXEN
0V OR VL
RL = 52.3Ω || 51.7Ω = 26Ω
VDD
RL
RL
CQ
SDI
I(CQ)
I(CQ) TWU
0.5A
0.5A
0.5A
VL
0V
0A
IQPKH
IQPKL
0A
0.5A
LTC2874
15
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For more information www.linear.com/LTC2874
TesT circuiTs / TiMing DiagraMs
Figure 5. Driver Timing
Figure 6. Driver Enable/Disable Timing
Figure 7. Receiver Timing
Figure 8. Receiver Noise Suppression
2874 F05
TXD CQ
TXEN
VL
CL
TXD
CQ
0V
VRQL
VDD – VRQH
VL
tPHLD tPLHD
VTHL(MIN) VTHH(MAX)
50% 50%
tSKEWD = |tPLHD – tPLHD|
CQ RXD
CL
2874 F07
VTHH(MAX)
NOISE
SUPPRESSION
OFF
NOISE
SUPPRESSION
ON
VTHL(MIN)
50%
50%
50%
50%
CQ
RXD
RXD
0V
VOH
VOL
VOL
VOH
VDD
tPHLR
tPHLR + tH • TBIT
tSKEWR = |tPHLR – tPLHR|
tPLHR + tL • TBIT
tPLHR
2874 F08
SHORT GLITCH
REJECTED
LONG GLITCH
DETECTED
tND
CQ
RXD
VDD
VTHH
VTHL
0V
VOH
VOL
TBIT TBIT
TXEN
CQ
VL
OR
GND
GND
OR
VDD
CL
RL
2874 F06
VTHH(MAX)
VTHL(MIN)
50% 50%
TXEN
CQ
CQ
0V
VDD – VRQH
0V
VDD – 3V
3V VRQL
VDD
VL
tZHD tHZD
tZLD tLZD
LTC2874
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For more information www.linear.com/LTC2874
TesT circuiTs / TiMing DiagraMs
Figure 9. SPI Interface Timing (Read)
Figure 10. SPI Interface Timing (Write or WrtUpd)
2874 F10
CS
SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDI C1C2 C0 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0
SDO
HI-Z HI-Z
2874 F09
CS
SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDI 00 0 A3 A2 A1 A0 X X X X X X X X X
SDO D7 D6 D5 D4 D3 D2 D1 D0
tSU tDS
tDH
tCH tHD
tCL
HI-Z
tSCK
HI-Z
tDO
LTC2874
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For more information www.linear.com/LTC2874
operaTion
The LTC2874 is an industrial master Hot Swap bus
controller and physical interface (PHY) that provides
power and communication to four independent 3-wire
ports through cables up to 20m in length (see Figure 11A).
The primary applications are 24V systems specified by
IEC 61131-9 single-drop communication interface (SDCI)
for small sensors and actuators, commonly known as
IO-Link. Each port on the LTC2874 includes a Hot Swap
power supply output, data transceiver, and a current
sink, as shown in Figure 11B. This set of features allows
a typical master controller for four ports to be built with
the LTC2874, a host microcontroller, and four power
MOSFETs. The basic configuration is shown on page 1.
The LTC2874 turns each port’s supply voltage on and off
in a controlled manner using external N-channel MOSFETs.
External sense resistors individually set the current
limits for each port. Optional foldback behavior reduces
maximum power dissipation in the external MOSFETs
over their operating range. Each output is protected by a
circuit breaker that responds to an overcurrent fault after
a programmable timeout delay. A current-pulse-upon-18V
feature provides additional IO-Link capability for driving
heavy, nonlinear loads.
The rugged
LTC2874 line interface has been designed to tol-
erate abusive conditions encountered on cable interfaces.
The CQ pins will tolerate 50V above L– (GND) and –50V
from VDD. The L+ pins offer commensurate ruggedness for
power supply outputs (see Absolute Maximum Ratings).
Discrete power MOSFETs offer the best possible system
ruggedness and allow design flexibility. They also ensure
that ports remain fully independent in the event of extreme
fault conditions.
Normally, the LTC2874 will automatically restart after
supply overvoltage or port overcurrent timeout faults. The
auto-retry delay is programmable. Alternatively, latchoff
behavior is available. Overcurrent circuit breaker delays
for CQ pins are mode dependent; for L+ pins they are
programmable.
The LTC2874 provides a 4-wire SPI-compatible interface
for configuration and monitoring. The host can detect
faults and other events by polling four event registers or by
monitoring the IRQ pin, a programmable interrupt request.
Standalone Operation
The LTC2874 is designed for use with a host controller. The
SPI-compatible interface is the only means of operating
the Hot Swap power supply outputs. The transceivers can
operate standalone without the serial interface, restricted
by the default register configuration settings.
Figure 11. (A) SDCI Class A 3-Wire Interface
(B) LTC2874 Master 3-Wire Interface Port
The bidirectional CQ pins are individually programmable
to operate in coded switching (COM) or switching signal
(standard IO, or SIO) format with reconfigurable behavior
including slew rate, noise suppression filter, and sinking
current. Drivers are protected against overcurrent faults
by circuit breakers that respond to a fault condition after
a mode-specific delay. For IO-Link compatibility, under
SPI control, the LTC2874 automatically generates 80µs
wake-up request (WURQ) pulses with correct polarity.
L+
C/Q
L–
L+
L–
ILL
C/Q
L+, L–: POWER SUPPLY
C/Q: COMMUNICATION OR
SWITCHING SIGNAL
(A) (B)
2874 F11
MASTER DEVICE
Hot Swap
VDD
DRV
LTC2874
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For more information www.linear.com/LTC2874
Drivers
The LTC2874 line drivers convert digital levels at the TXD
pins to inverted polarity line levels at the CQ pins. Drive at
data rates of up to 230.4kb/s. For IO-Link operation, they
support COM1, COM2, and COM3 transmission. The four
drivers operate concurrently and independently.
The LTC2874 line drivers are current limited to 160mA. Each
is protected by an overcurrent circuit breaker with mode-
selectable timeout. For normal signaling (SIO_MODE = 0),
the circuit breaker will trip after being in current limit for
15µs. This timeout is more than sufficient to support IO-
link requirements.
The drivers feature a controlled programmable slew rate
for optimum EMC performance. Rise and fall times are
programmed using a register bit and are independent of
the VDD supply voltage. Set each driver’s SLEW bit high
for edge times of 0.5µs, or low for edge times of 3µs.
Each driver is enabled either by its TXEN pin or DRVEN
register bit. When disabled, drivers are Hi-Z and the CQ
pin impedance is dominated by the ILL current sink (unless
disabled) and the receiver input resistance.
While the line drivers normally operate push-pull, each can
also operate in open-drain mode by driving the data signal
into its TXEN pin. For operation with an external pull-up,
tie its TXD pin high. For an external pull-down, disable
that port’s current sink (ILLM = 0) and tie its TXD pin low.
SIO Mode
Up to 1µF of load capacitance can be driven in SIO, or
standard I/O, mode. Set SIO_MODE = 1 and reduce the
edge rate (SLEW = 0). In SIO mode, the overcurrent circuit
breaker timeout is extended to 480µs.
Configuring CQ Outputs for 200mA or 400mA
The LTC2874 driving capability can be increased by
connecting CQ outputs and operating drivers in parallel.
Figure 36 shows a 2-port configuration that guarantees
a minimum CQ drive strength of 200mA, and Figure 37
shows a configuration for 400mA. Combine only CQ out-
puts from a single LTC2874.
applicaTions inForMaTion
Receivers
The four receivers convert 24V signals detected at the
CQ line inputs to inverted-polarity logic levels at the RXD
outputs. Receiver threshold behavior is selectable, as
shown in Figure 12. When the 24VMODE bit is set low,
the receiver thresholds for all four ports track the input
VDD supply.
Each receiver has an optional digital noise filter that rejects
narrow pulses on the CQ line. Filter delays of 0.6µs, 2.8µs
or 20.3µs are selected using port-specific NSF register
bits. Setting NSF = 0x0 disables the filter.
When the receiver is operated at an IO-Link compatible
data rate (COM3, COM2 or COM1) and the NSF bits are set
accordingly, the filter rejects pulses shorter than 1/16 of
the bit time. Figure 13 illustrates the rejection and detec-
tion bands for a positive noise glitch.
Except when Hi-Z at start-up (see Figure 26), receivers
are always active.
Driver and receiver settings appropriate for SIO mode and
IO-Link operation are summarized in Table 1.
Table 1. Recommended Driver and Receiver Settings
OPERATION SLEW NSF SIO_MODE
SIO 0 0x1 1
COM1 0 0x1 0
COM2 0 0x2 0
COM3 1 0x3 0
Figure 12. CQ Receiver Input Threshold (Typical)
VDD SUPPLY VOLTAGE (V)
RECEIVER THRESHOLDS (V)
10 20
20
24VMODE = 1
24VMODE = 0
11.9V
VTHH
VTHL
0.55*VDD
0.45*VDD
9.4V
15
10
5
00
2874 F12
30 40
LTC2874
19
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For more information www.linear.com/LTC2874
applicaTions inForMaTion
Current Sinks
Each CQ pin has a programmable current sink for use with
sensors having high side outputs. Each port’s current sink
is independently set to a value of 0mA, 2.5mA, 3.7mA, or
6.2mA with port-specific ILLM register bits. The highest
setting guarantees 5mA for IO-link. The second setting
guarantees 2.2mA for compatibility with IEC 61131-2
digital inputs. Each current sink disables when its driver is
enabled or a wake-up request is in progress on that port.
Automatic Wake-Up Generation
The LTC2874 generates an 80µs 500mA wake-up pulse
for the purpose of gaining the attention of a remote IO-
Link device. To initiate WURQ generation on a particular
port, the respective WKUP bit must be set high. Acting
as a pushbutton, the bit will self-clear once the WURQ is
underway. The sequence begins by automatically determin-
ing the correct polarity for the pulse, first by disabling the
driver (as needed) and sensing the CQ line for 5µs. The
driver switches on to generate the pulse, then returns to
its state prior to the WURQ (normally off). The complete
sequence is shown in Figure 14.
Although WURQs may be generated with the driver enabled,
we recommend the following procedure for best results:
1. Disable driver.
2. Clear any driver fault by setting TOC_CQ event bit low.
3. Generate WURQ by setting WKUP bit high.
Several measures prevent overheating during WURQ,
when driver power dissipation can be high (for example,
easily 15W at maximum operating voltage). First, if any
overtemperature condition is detected when the WKUP bit
is first set high, polarity sensing and pulse generation are
delayed until the condition clears. Second, only one port
at a time is allowed a WURQ, determined by lowest port
number in the event of a simultaneous request. Third, upon
completion of a WURQ, an 8.3ms cool-down interval is
enforced before another WURQ can be generated. While
a WURQ is underway on any port, the WKUP bits cannot
be set. (Their holding latches can be set high with a write
command, and even read out, but when updated by an
update or WrtUpd command, they will clear and not change
the register bits themselves. See the Serial Interface section
for more information.) Finally, a thermal shutdown condi-
tion will cause the driver to turn off. Normal overcurrent
circuit breaker timers are disabled during wake-up.
Setting the 24VMODE register bit low disables wake-up
generation; the WKUP bits have no effect and will not
self clear.
L+ PIN POWER CONTROL
External MOSFET, Sense R Summary
One function of the LTC2874 is to control delivery of power
through cables to four remote devices. On each port it does
this by controlling the gate voltage of an external power
MOSFET based on the current monitored by an external
sense resistor and the output voltage at the L+ pin. This
circuitry couples the raw VDD input supply to each port
through the MOSFET in a controlled manner that satisfies
the power needs of the connected device while minimizing
power dissipation in the MOSFET and disturbances on the
VDD backplane.
Figure 13. Receiver Noise Rejection and Detection
Behavior for CQ Positive Glitch
Figure 14. Wake-up Sequence
2874 F14
WKUP
BIT
WKUP BIT
SELF-CLEARS
SENSE
5µs 8.3ms LOCKOUT80µs
READY
AGAIN
CQ
WU
EVENT BIT
2874 F13
GLITCH DURATION
GLITCH HIGH LEVEL
0V 1/16 TBIT
NSF = 0x01, 0x10:
N = 3/16
NSF = 0x11:
N = 4/16
VTHH
N • TBIT
REJECTEDREJECTED
REJECTED
UNDEFINED
REJECTED DETECTED
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The current limit of each LTC2874 L+ port is set with a
resistor of value ΔVACL/ILIMIT. Specified variation in ΔVACL
(±10%) and tolerance of the resistor must be taken into
account. For IO-Link applications (which require a guaran-
teed minimum of 0.2A), 0.2Ω sense resistors (RS1 to RS4)
will set the typical limit 25% above the required minimum.
Inrush Control
When the L+ supply of any port is enabled (ENL+ = 1),
the LTC2874 ramps up the GATE pin of that port’s external
MOSFET in a controlled manner. The gate drivers use a
shared charge pump that derives its power from VDD.
Under normal power-up circumstances, the MOSFET gate
rises until the port current reaches the current limit, at
which point the GATE pin is servoed to maintain the cur-
rent limit. The ramp rate of the L+ port output voltage is:
dV(L+)
dt =
I(L+)
C
L
+
=
ΔV
ACL
R
S
•C
L
+
where CL+ is the capacitance on the L+ pin, including sup-
ply bypass capacitance of the connected device.
During this inrush period, an integrating up/down counter
times the duration that the current exceeds the circuit
breaker threshold ΔVCB(TH). When output charging is
complete, the port current falls and the GATE pin resumes
rising to fully enhance the MOSFET and minimize its on-
resistance. The final VGS is nominally 13V. If the timer
expires before the inrush period completes, the port is
turned off and a TOC_L+ fault is reported. The timer
delay is adjustable from 17.5µs to 0.25s using the LPTC
register bits.
Optionally, the L+ pin ramp rate can be slowed further using
the RGCG network shown in Figure 22. For a sufficiently
large capacitor, the ramp rate is:
dV(L+)
dt =
dV(GATE)
dt =
I(GATE)
C
G
=
14µA
C
G
Using a CG of 10nF will cause L+ to ramp on in about 20ms.
L+ Current Limit
The LTC2874 actively controls the MOSFET gate drive to
keep the port current below ΔVACL/RS. It allows the port
current to exceed ΔVCB(TH)/RS for a limited time before
powering down the port. This duration is timed by an
integrating up/down counter for that port whose mini-
mum timeout, which is common to all ports, is set in the
TMRCTRL register (0xC). If the current drops below the
circuit breaker current threshold before the timer expires,
the timer counts back down at the same rate. This allows
the current limit circuitry to tolerate intermittent overload
signals with duty cycles below about 50%; longer duty
cycle overloads will turn the port off.
L+ Current Limit Foldback Protection
During port start-up (inrush) or when a cable is connected
(hot-plugged) to an enabled port, most of the supply
voltage is dropped across the MOSFET as it begins to
supply charging current to the remote device. To protect
the MOSFET from overheating, the LTC2874 has a cur-
rent limit foldback circuit that limits the maximum power
dissipated by the external MOSFET, thereby increasing its
robustness. Figure 15 shows how ΔVACL is linearly reduced
(folded back) according to the voltage on the L+ pin. The
circuit breaker voltage ΔVCB(TH) is also folded back and
remains no higher than ΔVACL. Figure 16 shows typical
power-on behavior with foldback.
Foldback mode may interfere with start-up into some
resistive loads. Setting the FLDBK_MODE bit low disables
foldback behavior.
Figure 15. L+ Foldback Characteristic
2874 F15
50
16.7
1.2
3
7
18
24VMODE = 0
24VMODE = 1
L+ VOLTAGE (V)
∆VACL (mV)
FLDBK_MODE = 0
FLDBK_MODE = 1
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When the L+ pin voltage first reaches 18V, the L+ port
current limit is doubled for a timed interval. The current
sense voltage ΔVACL is increased 100%, and the circuit
breaker time is disabled until the pulse timer expires.
The start-up pulse duration is set using the 2XPTC register
bits. The default setting of 62ms satisfies the required
minimum of 50ms for IO-Link compatibility. Durations of
31ms and 124ms are also available. Set the L+ overcurrent
timer (adjusted with the LPTC register bits) to a sufficiently
high setting to ensure that the circuit breaker doesn’t trip
before L+ reaches 18V. Setting 2XPTC to 0x1 disables the
start-up pulse function.
L+ Power Good and Power Changed
Power good status is signalled when the L+ pin voltage
rises to within VL+(PGTH) of the VDD supply rail and the GATE
to L+ voltage exceeds 3.8V, indicating that the MOSFET
is almost fully enhanced.
After a 10µs delay, a PWRCHNG event indicates that the
PWRGD status has changed, as shown in Figure 18.
Once an L+ output is disabled, the PWRGD status bit clears
and the PWRCHNG event bit is static.
Figure 16. L+ Enable Behavior with Foldback
Figure 17. L+ Current Pulse Capability
Figure 18. Power Good Status and Power Changed Event
2874 F16
ENL+
BIT
OV
VDD
ILOAD
GATE
CURRENT
LIMITED
FOLDBACK
VDD + 13V
I(L+)
L+
2874 F18
L+
10µs 10µs
CLEAR
EVENT
VDD – V(L+PGTH)
PWRGD
STATUS BIT
PWRCHNG
EVENT BIT
L+ Overcurrent Fault
When a circuit breaker timeout occurs, the corresponding
timeout fault event bit (TOC_L+) is set and the GATE pin
is pulled down to the L+ pin with a 90mA current. The
remaining ports of the LTC2874 are unaffected, and the
ENL+ bit remains set. If the RETRY_L+ bit is set, auto-
retry will re-enable the port after a delay; otherwise, the
port latches off until the event bit is cleared. Figure 24 and
Figure 25 show example behavior.
L+ Supply Current Pulse Capability
The LTC2874 can optionally double the available current
(to 2 • ΔVACL/RS) when an L+ output supply is first powered
on, accommodating connected devices that require higher
current during their own start-up phase. This function may
be useful in applications where there is no signaling that
it’s safe to turn on downstream dynamic loads.
Figure 17 shows simplified behavior when connected to
a 100µF load with a 0.2Ω sense resistor and foldback
disabled (FLDBK_MODE = 0).
2874 F17
L+ PORT
CURRENT LIMIT
250mA
VDD
18V
500mA
ACTUAL
I(L+)
ENL+
BIT
L+
62ms
2X CURRENT
PULSE CAPABILITY
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Gate Turn-Off
When a port is disabled (ENL+ = 0), its MOSFET is turned
off with a 1.2mA current pulling down the GATE pin to
GND. The L+ pin voltage drops as CL+ discharges.
The LTC2874 is designed to turn off the GATE rapidly
during certain fault conditions to prevent damage to the
MOSFET. The fault events that initiate a faster shut down
include UVLO of either supply, VDD overvoltage (unless
OV_ALLOW = 1), and overcurrent circuit breaker timeout
(TOC_L+). In these cases the GATE pin is discharged to
the L+ pin with a 90mA current.
Cable Sensing
Hot-plugging, or the connection and disconnection of
cables to an already enabled port, can cause sparking and
reliability problems as connector plating wears off over
time. Connection sensing mode (CSENSE_MODE = 1)
mitigates this problem, extending connector lifetime. When
a port is enabled with this feature active, the LTC2874 waits
until it detects an external connection to its L+ pin before
enhancing the external MOSFET supplying it.
The cable sense function identifies cable connections
by measuring capacitive loading. The concept is shown
in Figure 19. When a given port is enabled, the L+ and
GATE pins are trickle-charged positive with 200µA, keep-
ing ΔVGATE close to 0V. The LTC2874 determines that a
cable is connected if either L+ doesn’t rise within about
40ms (because it is loaded) or L+ subsequently pulls low
(because a connected cable steals trickle current charge).
Figure 20 and Figure 21 illustrate the behavior.
At the maximum operating supply, the timer delay accom-
modates typically 100nF of combined L+ and GATE pin
loading on the master board without falsely detecting a
connection. Cable disconnection is not sensed.
Power good (PWRGD) status is low during the SENSE
and WAIT states.
Figure 19. Cable Sensing State Diagram
Figure 20. Cable Sense Behavior: Connection Before ENL+
Figure 21. Cable Sense Behavior: Connection After ENL+
2874 F20
L+EN
BIT
CSENSE
EVENT BIT
40ms
ISENSE
IRQ
L+
VDD – 1.5 • VPG(TH)
GATE ON
CABLE CONNECTED
BEFORE ENL+
2874 F21
L+EN
BIT
VDD – 1.5 • VPG(TH)
CSENSE
EVENT BIT
40ms
ISENSE
CABLE CONNECTED
AFTER ENL+
IRQ
L+
GATE ON
2874 F19
L+EN = 0
L+EN = 0
L+ LOW
L+EN = 0
40ms
L+ LOW
40ms
L+ HIGH
200µA
SENSE
GATE
ON
GATE
OFF WAIT
L+EN = 1
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L+ Current Limit Stability
For many applications the LTC2874 current limit is stable
with a minimum of external components. In Figure 22,
RGATE is required to suppress the tendancy for Q1 to de-
velop parasitic self-oscillation. A value between 10Ω and
100Ω is recommended. The bypass capacitors on the VDD
input supply play an essential role as well.
In some applications, additional components are needed
to improve stability. Small MOSFETs with especially low
CGS are less stable, as are larger sense resistors RS.
Improve stability using the RGCG compensation network
in Figure 22. For RG, choose a value between 100Ω (nor-
mally sufficient ) and 1kΩ; for CG, use between 2nF and
10nF. Do not connect CG directly between the GATE pin
and ground.
Board level short-circuit testing is recommended. The
worst-case condition for current limit stability occurs when
the output is shorted to ground after a normal start-up.
The capacitor CG serves a dual purpose, also setting the
L+ pin ramp rate described in the Inrush Control section.
MOSFET Selection
Careful selection of the power MOSFET is critical to system
reliability. For IO-Link compatibility, Linear Technology
recommends Fairchild FQT7N10, or
a similar planar process
device in a SOT-223 package. Larger devices may degrade
transient performance of current limiting, while smaller
devices are more likely to require external compensation
(see L+ Current Limit Stability) and require more care to
stay within the rated safe operating area (SOA).
Design Example
The MOSFET is sized to handle power dissipation during
inrush when L+ loads are being charged. Considering the
case of a load capacitor CL+, power dissipation during
inrush can be determined based on the principle that:
Energy in the MOSFET = Energy in CL+
This stored energy is 0.5 • CV2. For example:
Energy in CL+ = 0.5 • 100µF • (30V)2 = 0.045J
With foldback mode disabled, the time it takes to charge
up CL+ is:
tSTARTUP=
V
DD
•C
L+
ΔVACL
R
S
=
30V •100µF
50mV
0.2Ω
=12ms
MOSFET power dissipation is:
P =
Energy in C
L+
t
STARTUP
=3.75W
In foldback mode, this power is reduced further.
For IO-Link applications, another case to consider is the
start-up current pulse (see L+ Supply Current Pulse Capa-
bility), in which a heavy nonlinear load could be supplied
twice the normal current, or 2 • ΔVACL/RS, for up to 72ms.
Again assuming 0.2Ω sense resistors and no benefit from
foldback, average MOSFET power dissipation is:
P = 30V – (0V+18V)
2
•0.5A =3.0W
The SOA (safe operating area) curves of candidate
MOSFETs must be evaluated to ensure that the heat ca-
pacity of the package tolerates the more extreme case,
3W for 72ms. The SOA curves of the Fairchild FQT7N10
provide for 350mA at 30V (>10W) for 100ms, satisfying
this requirement.
Figure 22. External Components for Improving Stability and
Controlling Inrush Current
2874 F22
SENSE+
LTC2874
GATE
RGATE
10Ω
Q1
CABLE
CVDD2
100µF SENSE–
RG
CG
VDD
CVDD1
1µF CL+
RS
0.2Ω
+
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Power Considerations
The LTC2874 has two power supply pins: a logic supply
pin (VL) and the primary supply (VDD). The VL supply
powers the control logic, serial interface and SPI registers,
and allows the LTC2874 to interface with any logic signal
from 2.9V to 5.5V. Bypass VL to GND with at least a 0.1µF
ceramic capacitor. There is no power supply sequencing
requirement.
Bypass capacitance between VDD and GND is important
for reliable operation. If a short circuit occurs at one of
the L+ output ports, it can take more than 20µs for the
LTC2874 to begin regulating the current. During this time
the current is limited only by minimal impedance, so a high
current spike can cause a voltage transient on the VDD
supply with the possibility that the LTC2874 resets due to
a UVLO fault. Decouple VDD to ground with at least 100µF
bulk capacitance and a 1µF, 100V X7R ceramic capacitor
placed near the VDD pin to minimize spurious resets.
Supply Monitors
The LTC2874 monitors various conditions on its two input
power supplies, and alerts the host microcontroller when
supply levels move outside of their operating range. Event
bits record when the logic supply VL has moved below its
UVLO threshold or when the main supply VDD has moved
below its UVLO threshold, below its mode-dependent UV
level, or above its programmable OV level (see Figure 23).
Figure 23. Supply UVLO, UV, and OV Monitors
2874 F23
18V
32V
34V
36V
OV_TH[1:0]
24VMODE
0V_VDD
EVENT
UV_VDD
EVENT
UVLO_VL
EVENT
STATUS
UVLO_VDD
EVENT
STATUS
6V
VDD
–
+
–
+
–
+
10µs
7V
17.5V
10µs
10µs
2V
VL
POR
–
+
To provide immunity against supply voltage spikes, the
VDD event bits have a 10µs filter time. Status bits are live
(no-delay) indicators.
Operating Above 30V
When operating above 30V, the VDD threshold at which
overvoltage circuits disable the CQ and L+ pins must be
set higher than the default value (32V). Choose a value of
34V or 36V using the OV_TH[1:0] register bits.
Auto-Retry or Latchoff Fault Response
When a line output is shorted or the ΔVCB(TH) threshold is
otherwise exceeded, a timed circuit breaker disables the
L+ power supply output or CQ driver before overheating
can damage the MOSFET (L+) or master (CQ). Register
bits RETRY_L+ and RETRY_CQ allow independent fault
behavior for L+ and CQ pins. Set these bits high for auto-
retry behavior and low for latchoff. Default behavior is
auto-retry.
When configured for auto-retry behavior, the LTC2874
periodically re-enables the pin to check if the fault
condition is still present. See Erratum #1. The RE-
TRYTC[2:0] register bits adjust the retry timer delay
from 0.12s to 15.7s to allow for cooling. Choose retry
(RETRYTC) and overcurrent timer (LPTC) settings in tandem
to keep the duty cycle of an L+ fault condition sufficiently
low to allow for cooling of the external MOSFET. In the
case of a CQ fault condition, even the fastest RETRYTC
setting limits the duty cycle to <1% to allow for cooling
of one or more drivers.
When configured for latchoff behavior, the LTC2874
disables the respective L+ or CQ pin until the overcur-
rent event bit is cleared. In this case, clearing the event
register initiates a manual retry. The host is responsible
for limiting the duty cycle of the fault condition to avoid
overheating the L+ MOSFET or CQ driver. For example,
when using the highest available LPTC setting, a manual
retry interval of 1s limits the L+ MOSFET duty cycle to
20%. In SIO mode, a manual retry interval of 5ms limits
the CQ driver duty cycle to 10%.
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Examples of both responses to an L+ fault are shown in
Figure 24 and Figure 25.
SPI Interface
The LTC2874 communicates with the host using a
SPI-compatible 4-wire interface. Figure 9 and Figure 10
show typical communication waveforms and timing rela-
tionships. Interrupts are signaled to the host via the IRQ pin.
When the chip select input CS is set low, it enables the
SCK input buffer and the SDO output. Data at the SDI pin
is transferred into the shift register at subsequent rising
SCK edges. For each 16-bit word, the command bits C2
to C0 are loaded first; then address bits A3 to A0; then a
don’t-care bit; and finally bits D7 to D0, which supply a byte
of data (ordered MSB-to-LSB) for some commands. Data
can be transferred to the LTC2874 only when CS is low.
SCK may be high or low at the falling edge of CS. Keep
SCK low between commands to ensure timely completion
of all commands.
Commands and their formats are shown in Table 2. Com-
mand codes not shown are reserved and should not be used.
Table 2. LTC2874 Command List and Format
COMMAND DETAIL (FIRST)
c2…c0
a3…a0
Bit-8
(LAST)
d7…d0
READ Read Register 000 AAAA X XXXXXXXX
WRITE Write Register
(No Update)
001 AAAA X DDDDDDDD
UPDATE Update All
Registers
010 XXXX X XXXXXXXX
WRTUPD Write One
Register and
Update All
011 AAAA X DDDDDDDD
RESET Reset 111 XXXX X XXXXXXXX
The LTC2874 allows the response to VDD supply overvoltage
faults to be tailored with similar flexibility. Normally, this
fault causes the L+ and CQ pins of all four ports to be
disabled. The RETRY_OV bit selects between auto-retry
and latchoff behavior. If the OV_ALLOW bit is set high,
the LTC2874 will tolerate overvoltage conditions, signaling
the event but not disabling any functions.
Auto-retry doesn’t clear any event registers, nor does
writing any event register bit high disable any function.
Start-Up Behavior
Both external supplies must exceed their undervoltage
lockout levels for 10ms before the CQ and L+ outputs are
allowed to turn on and before VDD events are reported. Dur-
ing that settling interval, the RXD pins are Hi-Z. Figure 26
shows typical start-up behavior, assuming the VDD supply
is the last to power on.
Figure 25. Latchoff Fault Behavior (for L+ Short)
Figure 24. Auto-Retry Fault Behavior (for L+ Short)
Figure 26. CQ or L+ Pin Start-Up Behavior
2874 F24
TOC L+
EVENT BIT
L+
tOC(L+) tRETRY tOC(L+) tRETRY
IRQ
2874 F25
TOC L+
EVENT BIT
L+
tOC(L+) LATCHOFF tOC(L+) LATCHOFF
CLEAR
EVENT
IRQ
2874 F26
10ms
HI-Z
VDD(UVL)
VDD
EARLIEST POSSIBLE TRANSITION OF
L+ IF ENABLED BY ENL+ OR
CQ IF ENABLED BY TXEN/DRVEN
RXD
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SPI Write, Update, and WrtUpd Commands
Three of the commands relate to writing data to the reg-
isters. The write command transfers data from the shift
register to the holding latches of any writable register.
The update command transfers data from all holding
latches to the SPI registers. The WrtUpd combines these
two commands.
For the write and WrtUpd commands, data is transferred
from the shift register on the 16th falling edge of SCK.
SPI Read Command
The read command transfers a byte of data from the
holding latches of a SPI register to the serial output pin
(SDO). Transitions occur on falling clock edges, allowing
data to be sampled by the SPI master on the rising edges,
beginning with the 8th SCK. When CS is low, the SDO pin
is low except when a high register bit is being read out.
When CS is high, SDO is Hi-Z.
Figure 27. Example SPI Commands
Data written to the internal data holding latches can be
verified prior to committing data to the SPI registers by
reading it before an update command is sent.
SPI Reset Command
The reset command returns default values to the SPI
register and clears internal latches. It has no effect on the
SPI data path itself. This command has sticky behavior,
not releasing until a subsequent command (besides reset)
is received.
Continuous Transfer Capability
Commonly for SPI communication, CS is asserted low
once per command word. The LTC2874 also supports
continuous transfer in which multiple command words,
each accompanied by 16 SCK pulses, are grouped in a
sequence (Figure 28). This feature is useful for software
polling or writing to multiple registers. Keep CS low until
after the last command word in the group.
Chip Select Addressing
Combine LTC2874 devices to build larger masters by
assigning each its own CS and sharing the remaining SPI
interface wires. See Figure 40.
SPI Registers
The LTC2874 has 15 registers for configuration and
monitoring: seven for control, two for status, four to
record events, and two to handle interrupts. Register bit
assignments are summarized in Table 3.
When VL is below approximately 2V, the SPI serial port
resets to power-on states and registers are set to default
values. The reset command similarly sets the registers
to default values (with minor differences listed in the last
column of Table 3) and resets internal control circuits.
Figure 28. Continuous Transfer Capability
2874 F28
RESET WRITE WRITE WRITE WRITE UPDATE
16 SCK
PULSES
SDI
SCK
CS
16 SCK
PULSES
16 SCK
PULSES
16 SCK
PULSES
16 SCK
PULSES
16 SCK
||||||||||||||||
COMMAND
RESET
WRITE
WRITE
WRITE
UPDATE
READ
0x8
0x9
0xA
0x1F
0xF0
0x00
0x0
2874 F27
(FIRST) (LAST)
SEQUENCE AT SDI PIN
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
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Table 3. SPI Register Table
REG NAME D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
0x0 IRQREG
(Read
Only)
OT
Overtemp
Event
Occurred
SUPPLY
Supply
Event
Occurred
WU
Wake-Up
Event
Occurred
TOC_L+
L+ OC
Timeout
Event
Occurred
PWRCHNG
L+ Power
Changed
Event
Occurred
TOC_CQ
CQ OC
Timeout
Event
Occurred
CSENSE
Cable Sense
Event
Occurred
Reserved 0100,0000
(VL-on Reset)
0000,0000
(SPI Reset)
0x1 IRQMASK OT
Overtemp
IRQ Mask
SUPPL
Y
Supply
IRQ Mask
WU
Wake-Up
IRQ Mask
TOC_L+
L+ OC
Timeout
IRQ Mask
PWRCHNG
L+ Power
Changed
IRQ Mask
TOC_CQ
CQ OC
Timeout
IRQ Mask
CSENSE
Cable Sense
IRQ Mask
Reserved 1111,1110
0x2 EVENT1 OT_SD
Overtemp
Shutdown
Occurred
OT_WARN
Overtemp
Warning
Occurred
Reserved UVLO_VL
VL UVLO
Event
Occurred
UVLO_VDD
VDD UVLO
Event
Occurred
UV_VDD
VDD UV
Event
Occurred
OV_VDD
VDD OV
Event
Occurred
Reserved 0001,0000
(VL-on Reset)
0000,0000
(SPI Reset)
0x3 EVENT2 WU4
Wake-Up
Event CQ4
Occurred
WU3
Wake-Up
Event CQ3
Occurred
WU2
Wake-Up
Event CQ2
Occurred
WU1
Wake-Up
Event CQ1
Occurred
TOC_L+4
L+4 OC
Timeout
Event
Occurred
TOC_L+3
L+3 OC
Timeout
Event
Occurred
TOC_L+2
L+2 OC
Timeout
Event
Occurred
TOC_L+1
L+1 OC
Timeout
Event
Occurred
0000,0000
0x4 EVENT3 PWRCHNG4
L+4 Power
Changed
Event
Occurred
PWRCHNG3
L+3 Power
Changed
Event
Occurred
PWRCHNG2
L+2 Power
Changed
Event
Occurred
PWRCHNG1
L+1 Power
Changed
Event
Occurred
TOC_CQ4
CQ4 OC
Timeout
Event
Occurred
TOC_CQ3
CQ3 OC
Timeout
Event
Occurred
TOC_CQ2
CQ2 OC
Timeout
Event
Occurred
TOC_CQ1
CQ1 OC
Timeout
Event
Occurred
0000,0000
0x5 EVENT4 CQ_SNS4
CQ4 Sense:
0 = CQ High
1 = CQ Low
CQ_SNS3
CQ3 Sense:
0 = CQ High
1 = CQ Low
CQ_SNS2
CQ2 Sense:
0 = CQ High
1 = CQ Low
CQ_SNS1
CQ1 Sense:
0 = CQ High
1 = CQ Low
CSENSE4
L+4 Cable
Sense Event
Occurred
CSENSE3
L+3 Cable
Sense Event
Occurred
CSENSE2
L+2 Cable
Sense Event
Occurred
CSENSE1
L+1 Cable
Sense Event
Occurred
0000,0000
0x6 STATUS1
(Read
Only)
OT
Over-
temperature
Condition
WU_COOL
WURQ or
Cooldown
Condition
UVLO_VDD
VDD UVLO
Condition
OV_VDD
VDD Over-
voltage
Condition
OC_L+4
L+4 Over-
current
Condition
OC_L+3
L+3 Over-
current
Condition
OC_L+2
L+2 Over-
current
Condition
OC_L+1
L+1 Over-
current
Condition
0000,0000
0x7 STATUS2
(Read
Only)
PWRGD4
L+4 Power
Good
PWRGD3
L+3 Power
Good
PWRGD2
L+2 Power
Good
PWRGD1
L+1 Power
Good
OC_CQ4
CQ4 Over-
current
Condition
OC_CQ3
CQ3 Over-
current
Condition
OC_CQ2
CQ2 Over-
current
Condition
OC_CQ1
CQ1 Over-
current
Condition
0000,0000
0x8 MODE1 24VMODE
Enable
IO-Link
Compatible
Mode
CSENSE_
MODE
Enable
Cable Sense
Mode
2XPTC[1:0]
L+ Start-Up 2X Current
Pulse Timer Control:
00 = 62ms
01 = Disabled
10 = 31ms
11 = 124ms
FLDBK_
MODE
Enable
Foldback
Mode
RETRY_OV
Enable
VDD OV
Auto-Retry
RETRY_L+
Enable
L+ Pin
Auto-Retry
RETRY_CQ
Enable
CQ Pin
Auto-Retry
1000,1111
0x9 MODE2 SLEW4
CQ4 Edge
Rate:
0 = Slow
1 = Fast
SLEW3
CQ3 Edge
Rate:
0 = Slow
1 = Fast
SLEW2
CQ2 Edge
Rate:
0 = Slow
1 = Fast
SLEW1
CQ1 Edge
Rate:
0 = Slow
1 = Fast
OV_TH[1:0]
VDD Overvoltage
Threshold Select:
00 = 18V
01 = 32V
10 = 34V
11 = 36V
OV_ALLOW
Allow VDD
Overvoltage
CQ_SNS_
MODE
Enable CQ
Sense Mode
1111,0100
LTC2874
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Table 3. SPI Register Table
REG NAME D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
0xA NSF NSF4[1:0]
Noise Suppression Filter,
Port 4:
00 = Disabled
01 = 20.3µs
10 = 2.8µs
11 = 0.6µs
NSF3[1:0]
Noise Suppression Filter,
Port 3:
00 = Disabled
01 = 20.3µs
10 = 2.8µs
11 = 0.6µs
NSF2[1:0]
Noise Suppression Filter,
Port 2:
00 = Disabled
01 = 20.3µs
10 = 2.8µs
11 = 0.6µs
NSF1[1:0]
Noise Suppression Filter,
Port 1:
00 = Disabled
01 = 20.3µs
10 = 2.8µs
11 = 0.6µs
1111,1111
0xB ILLM ILLM4[1:0]
Sinking Current, Port 4:
00 = 500kΩ
01 = 2.5mA
10 = 3.7mA
11 = 6.2mA
ILLM3[1:0]
Sinking Current, Port 3:
00 = 500kΩ
01 = 2.5mA
10 = 3.7mA
11 = 6.2mA
ILLM2[1:0]
Sinking Current, Port 2:
00 = 500kΩ
01 = 2.5mA
10 = 3.7mA
11 = 6.2mA
ILLM1[1:0]
Sinking Current, Port 1:
00 = 500kΩ
01 = 2.5mA
10 = 3.7mA
11 = 6.2mA
1111,1111
0xC TMRCTRL LPTC[3:0]
L+ Overcurrent Timer Control (Ports 1 to 4):
0000 = 15µs 1000 = 3.9ms
0001 = 30µs 1001 = 7.8ms
0010 = 60µs 1010 = 16ms
0011 = 120µs 1011 = 30ms
0100 = 0.24ms 1100 = 60ms
0101 = 0.5ms 1101 = 0.12s
0110 = 1.0ms 1110 = 0.25s
0111 = 2.0ms 1111 = 0.25s
Reserved RETRYTC[2:0]
Auto-Retry Timer Control (Ports 1 to 4):
000 = 0.12s
001 = 0.24s
010 = 0.5s
011 = 1.0s
100 = 2.0s
101 = 3.9s
110 = 7.9s
111 = 15.7s
1000, 0101
0xD CTRL1 WKUP4
Generate
WURQ
on CQ4
WKUP3
Generate
WURQ
on CQ3
WKUP2
Generate
WURQ
on CQ2
WKUP1
Generate
WURQ
on CQ1
DRVEN4
Enable
CQ4 driver
DRVEN3
Enable
CQ3 driver
DRVEN2
Enable
CQ2 driver
DRVEN1
Enable
CQ1 driver
0000,0000
0xE CTRL2 ENL+4
Enable L+4
Power
Supply
ENL+3
Enable L+3
Power
Supply
ENL+2
Enable L+2
Power
Supply
ENL+1
Enable L+1
Power
Supply
SIO_MODE4
CQ4
SIO Mode
OC Timeout
0 = 15µs
1 = 480µs
SIO_MODE3
CQ3
SIO Mode
OC Timeout
0 = 15µs
1 = 480µs
SIO_MODE2
CQ2
SIO Mode
OC Timeout
0 = 15µs
1 = 480µs
SIO_MODE1
CQ1
SIO Mode
OC Timeout
0 = 15µs
1 = 480µs
0000,0000
Notes:
1: Delays are typical unless otherwise noted.
2: Underlined settings are default values.
3: Gray shading indicates Read-Only register bits.
4: Register 0xD WKUP bits are pushbuttons that self-clear.
5: Reserved bits may be converted to features in a future release of the product.
LTC2874
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Table 4. Summary of LTC2874 Event Reporting
EVENT
EVENT REGISTER/
EVENT BITS
IRQREG
MASK BIT BEHAVIOR NOTE
Overtemperature
Shutdown Level
EVENT1 (0x2)
OT_SD
7 Thermal
Recovery
Temperature has reached shutdown level.
L+ and CQ pins are disabled until condition clears.
Overtemperature
Warning Level
EVENT1 (0x2)
OT_WARN
7 Thermal
Recovery
Temperature has reached warning level. Wake-up
requests (WURQ) are blocked.
VL Supply UVLO EVENT1 (0x2)
SUPPLY
6 10ms
Recovery
VL below UVLO threshold for 10µs.
VDD Supply UVLO EVENT1 (0x2)
SUPPLY
6 10ms
Recovery
VDD below UVLO threshold for 10µs.
VDD Supply UV EVENT1 (0x2)
SUPPLY
6 Signal Event Only VDD below UV threshold for 10µs.
VDD Supply OV EVENT1 (0x2)
SUPPLY
6 Latchoff or
Auto-Retry
VDD above OV threshold for 10µs. L+ and CQ pins are
disabled unless OV_ALLOW bit set.
Wake-Up EVENT2 (0x3)
WU
5 8.3ms Wait Wake-up request (WURQ) has started. Additional
WURQs are blocked for 8.3ms.
L+ Overcurrent Timeout EVENT2 (0x3)
TOC_L+
4 Latchoff or
Auto-Retry
Duration of L+ current limiting has exceeded
programmable timeout.
L+ Power Changed EVENT3 (0x4)
PWRCHNG
3 Signal Event Only L+ power status has changed (10µs filter).
CQ Overcurrent Timeout EVENT3 (0x4)
TOC_CQ
2 Latchoff or
Auto-Retry
Duration of current limiting has exceeded
mode-dependent timeout.
CQ Sense EVENT4 (0x5)
CQ_SNS
n/a CQ Receiver Output
(Read Only)
Indicates CQ level (inverted polarity like RXD) when
CQ_SNS_MODE bit set high. Doesn’t signal IRQ.
Cable Sense EVENT4 (0x5)
CSENSE
1 L+ Supply Turns On Signals cable or load detected when CSENSE_MODE bit
set high.
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Event Signaling
When an event bit is set, in most cases a bit corresponding
to the event type also signals high in the IRQREG register
(0x0). If the corresponding bit in the IRQMASK register
(0x1) is high, the event causes the IRQ pin to pull low.
The IRQ signal generates an interrupt to the host micro-
controller, eliminating the need for continuous software
polling. The IRQMASK register selects which events can
gain the host’s attention at a given time.
SPI Receiver
The serial interface monitors the CQ line interface pins if the
CQ_SNS_MODE bit is set. The polarity of the four CQ_SNS
bits matches the polarity of the RXD pins. These bits are
reset low when CQ_SNS_MODE isn’t enabled (default).
Driving Light Bulbs
The CQ drivers can safely drive small incandescent light
bulbs. Use SIO mode (SIO_MODE = 1) and the fastest
auto-retry delay (RETRY_CQ = 1, RETRYTC = 0x0). The
drivers will pulse on and off while the filament initially
draws high current as it heats up. Figure 29 shows typi-
cal waveforms.
Driving Relays
Having 100mA drive capability, the CQ drivers are capable of
energizing the coils of many relays. For some applications
requiring higher current, the L+ lines may operate as low
data rate outputs. Figure 39 shows an example of the L+
pins driving 0.5A relays, with the CQ lines connected as relay
sense lines. CQ line drivers are disabled by pin-strapping
TXEN1 through TXEN4 low, and CQ pin load currents are
disabled by setting ILLM = 0x0 for each port. Activate
any relay by setting its ENL+ bit high. The relay sense
points are converted to logic levels at the RXD pins. If the
CQ_SNS_MODE bit is set high, the sense points may be
read from register 0x5 via the serial interface.
IO-Link Compatible Operation
Table 5 shows typical register settings for IO-Link com-
patible operation.
Setting the 24VMODE bit high programs the receivers
and L+ foldback for 24V operation per Figures 12 and 15.
Table 5. Example Settings for IO-Link Compatibility
REG VALUE DEFAULT NOTE
0x8 0x8F Y IO-Link Compatibility Mode Enabled;
L+ Startup 2x Current Pulse Enabled
0x9 0xF4 Y 32V VDD Overvoltage Threshold
0xA 0xFF Y 0.5μs Noise Suppression Filters
0xB 0xFF Y 6mA Sinking Currents
0xC 0x85 Y TOC_L+ Timer NOT Required to be Set
Longer Than 62ms Startup Current Pulse
Applications Other than IO-Link
Table 6 shows typical SPI register settings for operating
the LTC2874 in a 12V application.
Setting the 24VMODE bit low selects VDD-ratioed receiver
thresholds (Figure 12) and L+ foldback optimized for 12V
operation (Figure 15). Additionally, the WKUP register bits
are deactivated.
Table 6. Example Settings for 12V Application
REG VALUE DEFAULT NOTE
0x8 0x5F N IO-Link Compatibility Mode Disabled;
L+ Start-Up 2x Current Pulse Disabled
0x9 0xF0 N 18V VDD Overvoltage Threshold
0xA See Note – Noise Suppression Filtering as Needed
0xB 0x00 N Sinking Currents Disabled
Larger light bulbs can be driven if microcode defines a
faster driver cooling interval between pulses during bulb
ignition. Set RETRY_CQ = 0 and clear register 0x4 to
begin each new pulse. Because this technique defeats
built-in protection against driver self-heating, it must be
applied carefully.
Figure 29. Driving an Incandescent Bulb Using
SIO Mode and Auto-Retry
200ms/DIV
10V/DIV
50mA/DIV
2874 F29
CQ
CM7387-ND 28V T1
–(CQ)
LTC2874
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Reverse Current Protection
To isolate the VDD input supply against reverse current
from L+ outputs and isolate L+ pins against cable distur-
bances on other L+ outputs, use the approach shown in
Figure30. Add blocking diodes (D1-D4) to the MOSFET
drains rather than sources to maximize the MOSFET VGS.
When the L+ pins are configured with blocking diodes, 1µF
master-side L+ capacitors (C1-C4) are required to mitigate
the increased ringing that can occur in cable-driving ap-
plications. Use a smaller value (100nF) for applications
requiring cable detection. Figure 30 shows the placement of TVS diodes for protect-
ing the L+ outputs, while Figure 31 shows how to protect
the CQ pins.
MOSFET Fault Detection
The L+ supply outputs are designed to tolerate significant
levels of abuse, but in extreme cases it is possible for the
external MOSFET to be damaged. A failed MOSFET may
short from source to drain, which will make the port appear
to be on when it should be off. The LTC2874 will disable
the port if an overcurrent timeout occurs.
A failed MOSFET may also short from gate to source. This
type of short will prevent the LTC2874 from enhancing the
MOSFET. The host can detect this condition by the per-
manent absence of PWRGD. An open or missing MOSFET
will similarly not produce PWRGD.
Normally a damaged MOSFET will not affect other ports.
However, if it causes the sense resistor RS to fuse open,
the SENSE– pin will exceed its absolute maximum rating,
which might damage the LTC2874. This condition is
signalled to the host by an OC_L+ status bit that remains
high even when the supply output is disabled (ENL+ = 0).
Avoid this situation by performing adequate board-level
short circuit testing and using surge-rated sense resistors.
High Temperature Considerations
For some applications, the PCB must provide heat sinking
to keep the LTC2874 cool. Solder the exposed pad on the
bottom of the package to ground and tie to large copper
layers below using thermal vias.
Figure 30. Reverse Protection and TVS Diode Protection for
L+ Outputs
Figure 31. TVS Diode Protection for CQ pins
SENSE+
VDD
SENSE–1
GATE1
GND
L+1
L+2
L+3
L+4
LTC2874
2874 F30
D1 D2 D3 D4
VDD
1µF
C4C3C2C1
100µF
GND
VDD
VDD
*OPTIONAL TO EXTEND CQ OPERATING RANGE BELOW GROUND
*
CQ1
CQ2
CQ3
CQ4
LTC2874
2874 F31
Surge and ESD Protection Considerations
Cable interfaces are subject to significant ESD events
because long cables can store large reservoirs of charge.
The LTC2874 CQ and L+ line pins feature protection to
±8kV HBM with respect to GND without latchup or damage
during all modes of operation and while unpowered. All
the other pins are protected to ±6kV HBM.
In order to further protect the LTC2874 interface ports
against surge and contact/air discharge events based on
the IEC 61000-4-5 standard, additional external protec-
tion is required.
SM6T36A or equivalent TVS clamps are recommended for
IO-Link and most other applications. In 24V applications
in which the input supply tolerance does not exceed 15%,
SM6T33A or equivalent clamps are also suitable.
LTC2874
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LTC2874 power dissipation can be estimated by consider-
ing the contributions of drivers and sinking currents for a
given application, along with quiescent power dissipated
by internal circuits operating from two supplies. In gen-
eral, use the higher case of drive mode and receive mode
(sinking current) and ignore the other. Calculate driver
power dissipation by taking the product of CQ residual
voltage and load current for each port. Here we also factor
in worst-case limits and maximum possible DC loading
on all ports:
PD = 4 • MAX((ILL • VDD), (IRQH/L • VRQH/L)) +
(VDD • IDD) + (VL • IL)
PD = 4 • MAX((6.8mA • 34V), (0.23A • 1.6V)) +
(34V • 8mA) + (5.5V • 1mA) = 1.75W
For θJA of 34°C/W, the increase in junction temperature
compared to ambient is 60°C.
The thermal shutdown circuit signals an OT_SD event and
disables the drivers if the internal die temperature is above
about 170°C. The drivers turn back on when the internal
die temperature drops approximately 15°C.
When the internal die temperature is above about 140°C,
the OT status bit and OT_WARN event bit signal, enabling
an informed host to intervene.
Layout Guidelines
Standard power layout guidelines apply to the LTC2874:
place the decoupling caps for the VDD and VL supplies
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to the
LTC2874. Because the sense resistor values are small,
layout parasitics can cause significant errors. Care is
required to achieve specified accuracy.
Figure 32 illustrates the problem. In example Figure 32A,
two ports have load currents I1 and I2 that connect to
VDD through a mutual resistance RM. RM represents the
combined resistances of any traces, planes, and vias in
the PCB that I1 and I2 share. The LTC2874 measures the
voltage difference between its SENSE+ and SENSE– pins
to sense the voltage drop across RS1, but as the example
shows, RM introduces errors.
The second example (Figure 32B) shows how to minimize
errors using good layout. The circuit is rearranged so that
RM no longer affects VS, and the SENSE+ connection to
the LTC2874 is used as a Kelvin sense trace. It is not a
perfect Kelvin connection because all four ports controlled
by the LTC2874 share the same sense trace, and because
the current through the trace (IK) is not zero. However, as
the equation in Figure 32(B) shows, the remaining error
is a small offset term.
Figure 33 shows two LTC2874 chips controlling eight ports
(A through H). The ports are separated into two groups
of four; each has its own trace on the top PCB layer that
connects to the VDD plane through a via. Currents from
the U1 sub-circuit are effectively isolated from the U2
subcircuit, reducing the layout problem down to 4-port
subsections; this arrangement can be expanded for any
number of ports.
Figure 34 shows an example of good 4-port layout. In
this case, each sense resistor consists of two resistors
in parallel. The four groups of resistors are arranged to
minimize the overlap in their current flows, reducing mu-
tual resistance. Wide copper paths connect each group of
resistors to the vias at the center.
The SENSE+ Kelvin trace connects to the center of the resis-
tor array. The via at the center of the sense resistor array
has a matching hole in the VDD plane. This arrangement
prevents the mutual resistance of the four large vias from
influencing the current measurements and introducing
errors. An alternative layout is shown in Figure 35.
IO-Link Disclaimer
Linear Technology Corporation attempts to maintain
compatibility with the IO-Link interface and system speci-
fication. LT C is not a member of the IO-Link Consortium
as set forth by PROFIBUS Nutzeroganisation (PNO) e.V.
LTC2874
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Figure 32. Layout Affects Current Limit Accuracy: (A) Poor and (B) Good Layouts
SENSE+
VDD
IDD
+VSRS1
RM
MUTUAL
RESISTANCE
I1
I1 + I2 + IDD
SENSE–
LTC2874
SIGNAL
SCALE ERROR
CROSSTALK ERROR
(A) (B) 2874 F32
RS2
I2
VS = I1RS1 + I1RM + I2RM
SENSE+
VDD
IDD
+VSRS1
RM
KELVIN
SENSE LINE
IK
I1 + I2 + IDD
SENSE–
LTC2874
SIGNAL
SMALL OFFSET ERROR
RK
RS2
I1I2
VS = I1RS1 – IKRK
applicaTions inForMaTion
Figure 34. Good PCB Layout Example
Figure 33. Layout Strategy to Reduce Mutual Resistance
KELVIN SENSE TRACE CONNECTS
TO U1 SENSE+ PIN
FOUR LARGE VIAS
TO VDD PLANE
HOLE IN VDD PLANE
VIAS TO DRAIN PIN OF
THE PORT C MOSFET
LOCATED ON THE OPPOSITE
SIDE OF THE BOARD
PORT D RS
PIN 1
U1 PORT C RS
PORT A RSPORT B RS
2874 F34
SENSE+
VDD
VDD COPPER FILL
VIAS VIAS
SENSE–1
SENSE–2
SENSE–3
SENSE–4
LTC2874
PORTS A THROUGH D
U1 U2
2874 F33
SENSE+
VDD
SENSE–1
SENSE–2
SENSE–3
SENSE–4
LTC2874
PORTS E THROUGH H
VIAS VIAS
VDD COPPER PLANE
BY KEEPING THESE COPPER FILLS SEPARATE, MUTUAL
RESISTANCE BETWEEN PORTS A TO D AND E TO H IS ELIMINATED.
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A. Top Layer B. Inner Layer 2
C. Inner Layer 3 D. Inner Layer 4
E. Inner Layer 5 F. Bottom Layer
Figure 35. Demo Board DC1880A Layout Showing Sense Resistors (on Bottom Layer) and Tw o of Four MOSFETs
LTC2874 Q2
Q3
CVDD1
GND
VL VDD
RS1
RS4
RS2
D2
D3
RS3
LTC2874
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Typical applicaTions
Figure 36. 2-Port Configuration with Guaranteed 200mA CQ Drive Capability (and 200mA L+ Supply)
SENSE+
VDD
VCC
µC
VL
IRQ
SENSE–2
SENSE–3
SENSE–1
SENSE–4TXEN1
TXEN2
TXEN3
TXEN4
TXD1
TXD2
TXD3
TXD4
RXD1
RXD4
CS
SCK
SDI
SDO
L+1
CQ1
CQ2
L+4
CQ3
CQ4
GATE2
L+2
GATE3
L+3
LTC2874
8V TO 34V
2.9V TO 5.5V
2874 F36
GATE1
GATE4
GND
GND
100µF
4.7k
1µF
1µF
0.2Ω
10Ω
PORT 1
Q1
Q1, Q2: FQT7N10
Q2
PORT 2
LTC2874
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Typical applicaTions
Figure 37. 1-Port Configuration with Guaranteed 400mA CQ Drive Capability (and 400mA L+ Supply)
SENSE+
VDD
VCC
µC
VL
IRQ
SENSE–2
SENSE–3
SENSE–4
SENSE–1TXEN1
TXEN2
TXEN3
TXEN4
TXD1
TXD2
TXD3
TXD4
RXD1
CS
SCK
SDI
SDO
L+1
CQ1
CQ2
CQ3
CQ4
GATE2
GATE3
GATE4
L+2
L+3
L+4
LTC2874
8V TO 34V
2.9V TO 5.5V
2874 F37
GATE1
GND
GND
4.7k
1µF
0.1Ω
10Ω
Q1
Q1: FQT7N10
100µF 1µF
LTC2874
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Typical applicaTions
Figure 38. Blocking Diodes D1-D4 Protect VDD Against Overvoltage Faults on L+ Outputs,
TVS Diodes DZ Surge-Protect Cable Interface
SENSE+
VDD
VCC
µC
VL
IRQ
SENSE–1
SENSE–2
SENSE–3
SENSE–4
TXENn
TXDn
RXDn
CS
SCK
SDI
SDO
GATE1
GATE2
GATE3
GATE4
L+1
CQ1
L+2
CQ2
L+3
CQ3
L+4
CQ4
LTC2874
8V TO 30V
2.9V TO 5.5V
2874 F38
GND
D1 TO D4: SCHOTTKY
DZ: SM6T36A
Q1 TO Q4: FQT7N10
C1 TO C4: 1µF (REQUIRED WHEN USING D1-D4)
GND
1µF
4.7k
1µF
C4C3C2C1
0.2Ω 0.2Ω 0.2Ω 0.2Ω
DZ DZ DZ DZ
DZ DZ DZ DZ
D1 D2 D3 D4
10Ω
10Ω
10Ω
10Ω
Q1
Q2
Q3
Q4
4
4
4
100µF
1
4
3
1
4
3
1
4
3
1
4
3
2
2
2
2
LTC2874
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A
B
A
B
A
B
A
B
SENSE+
VDD
VCC
µC
VL
IRQ
SENSE–1
SENSE–2
SENSE–3
SENSE–4
TXENn
TXDn
RXDn
CS
SCK
SDI
SDO
K1
K2
K3
K4
GATE1
GATE2
GATE3
GATE4
L+1
CQ1
L+2
CQ2
L+3
CQ3
L+4
CQ4
LTC2874
24V
2.9V TO 5.5V
2874 F39
GND
GND
1µF
4.7k
1µF
80mΩ 80mΩ 80mΩ 80mΩ
10Ω Q1
Q2
Q3
Q4
D4
4
10Ω
10Ω
10Ω
100µF
D1 TO D4: 1N4004
Q1 TO Q4: FQT7N10
D3
D2
D1
Typical applicaTions
Figure 39. SPI-Operated Quad Relay Driver (with CQ Relay Sense) Guaranteeing 0.5A Coil Current
LTC2874
39
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For more information www.linear.com/LTC2874
Figure 40. N-Port Master Hot Swap Controller and PHY
Typical applicaTions
2874 F40
SCK
SDI
SDO
CS
IRQ
L+
CQ
GND
LTC2874
SCLK
MOSI
MISO
SS1
IRQ1
SS2
IRQ2
SSn
IRQn
SCK
SDI
SDO
CS
IRQ
L+
CQ
GND
LTC2874
SCK
SDI
SDO
CS
IRQ
L+
CQ
GND
LTC2874
4 PORTS
4 PORTS
4 PORTS
L–
L–
L–
µC
•
•
•
LTC2874
40
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For more information www.linear.com/LTC2874
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.75
(.187) REF
FE38 (AA) TSSOP REV C 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
LTC2874
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For more information www.linear.com/LTC2874
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
5.00 ±0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ±0.10
7.00 ±0.10
0.75 ±0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 ±0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ±0.10
0.40 ±0.10
0.70 ±0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ±0.05
4.10 ±0.05
5.50 ±0.05 5.15 ±0.05
6.10 ±0.05
7.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
LTC2874
42
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For more information www.linear.com/LTC2874
erraTa
ERRATUM #1
Description
In auto-retry mode, clearing the event register re-enables
the faulted pin(s) and resets the entry timer, potentially
interfering with duty cycle enforcement.
Work-Arounds
(a) Use latchoff mode. Interrupt service routine must limit
duty cycle of faulted pin(s) per guidance given in the
Auto-Retry or Latchoff Fault Response section.
(b) Use auto-retry mode, clearing faults using an interrupt
service time (TIS) that’s long compared to the retry
time (TIS > RETRYTC • 1.2).
(c) Use auto-retry mode, clearing faults using an interrupt
service time that’s short compared to the retry time
(TIS < RETRYTC • 0.8) while also limiting the maximum
duty cycle per (a).
LTC2874
43
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For more information www.linear.com/LTC2874
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 07/14 Lowered MOSFET gate resistor
Increased Input Supply Voltage (Max)
Lowered Input Low Threshold Voltage (Max)
Updated Cable Sense timer delay
Added “Operating Above 30V” Applications section
Changed capacitor values on slave port pins
1, 13, 23, 35, 36, 37, 42
3
4
22
24
42
B 05/15 Clarified L+ Supply Current Pulse Operation
Clarified PWRCHNG Event Behavior
Clarified Auto-Retry and Latchoff Mode Operation
Added Erratum #1
21
21
24, 25
41
LTC2874
44
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For more information www.linear.com/LTC2874
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2013
LT 0515 REV B • PRINTED IN USA
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2874
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT3669/LT3669-2 Industrial Transceivers with Integrated
Step Down Regulator and LDO
Compatible with IO-Link Interface and System Specification, Operates from 7.5V to 40V,
Integrated 100mA/300mA Buck and 150mA LDO
LTC2854/LTC2855 3.3V 20Mbps RS485 Transceivers with
Integrated Switchable Termination
3.3V Supply, Integrated, Switchable 120Ω Termination Resistor, ±25kV ESD
LTC2859/LTC2861 20Mbps RS485 Transceivers with
Integrated Switchable Termination
5V Supply, Integrated, Switchable 120Ω Termination Resistor, ±15kV ESD
LTC2862/LTC2865 ±60V Fault Protected 3V to 5.5V RS485/
RS422 Transceivers
20Mbps, Protected from Overvoltage Line Faults to ±60V, ±15kV ESD
LTC2870/LTC2871/
LTC2872
RS232/RS485 Multiprotocol
Transceivers with Integrated Termination
3V to 5.5V Supply, Automatic Selection of Termination Resistors, Duplex Control, Logic
Supply Pin, Up to ±26kV ESD
LTM2881 Complete Isolated RS485/RS422
μModule
®
Transceiver + Power
3V or 5V Supply, 20Mbps, 2500VRMS Isolation with Integrated DC/DC Converter,
Integrated Switchable 120Ω Termination Resistor, ±15kV ESD
LTM2882 Dual Isolated RS232 μModule
Transceiver + Power
3V or 5V Supply, 1Mbps, 2500VRMS Isolation with Integrated DC/DC Converter,
±10kV ESD
Complete 24V 3-Wire Power and COM3 Rate Signaling Interface to Sensor or Actuator
(One of Four Available Master Ports is Shown)
1
4
2
3
BD
FBOUT
µC
CPOR SW
VOUT
OR
VLDO
RT
ILIM
LDOIN
LDO
FBLDO
AGND
DIO
EN/UVLO
L+
Q2
CQ1
BST
SR
SYNC
RST
SC1
SC2
WAKE
RXD1
TXEN1
TXD1
TXEN2
TXD2
LT3669
GND
1µF
10.2k 0.1µF
10µF
38.3k
53.6k
VOUT
4.42k
14k
VLDO, ILDO**
3.3V, 100mA
20 METERS
**IOUT(MAX), IS 100mA AND ILDO(MAX) IS 100mA
(REMAINING AVAILABLE IOUT IS: 100mA – ILDO)
fW = 600kHz
tRST = 12.5ms
VOUT, IOUT**
5V, 100mA
470pF470pF4.7µF
0.1µF
82µH
2874 TA02
1
4
3
5
VDD
µC
VL
IRQ
SDI
SCK
CS
SDO
RXD1
TXEN1
TXD1
Q1: FQT7N10
SURGE PROTECTION NOT SHOWN
*ADDITIONAL BYPASS CAP AS NEEDED
L+1
CQ1
GATE1
SENSE–1
SENSE+
LTC2874
1/4
GND
0.1µF
2.9V TO 5.5V
*
4.7k
1µF
24V
0.2Ω
Q1
100µF
10Ω
200mA
100mA
100mA
100mA
2
1
4
3