Data Sheet April 1998 microelectronics group Lucent Technologies Bell Labs Innovations T7290A DS1/T1/CEPT/E1 Line Interface Features a Fully integrated DS1/T1/CEPT/E1 line interface = For use in systems that are compliant with CB119, AT&T PUB 43801, AT&T PUB 43802, AT&T PUB 62411, TR-TSY-000170, TR-TSY-000009, ITU-T G.703, G.735, G.823, and 1.431 specifications s Dual-rail system interface a On-chip transmit equalization a On-chip jitter attenuator = Monolithic clock recovery with frequency- acquisition aide a High jitter accommodation (>0.4 U.!.) = No external crystal required Three clocking modes to accommodate multiple system clocking requirements a Multiple link-status and alarm features = Microprocessor interface option w AIS (blue alarm) transmission m Loopback modes for fault isolation a Minimal external circuitry required Description The Lucent Technologies Microelectronics Group T7290A DS1/T1/CEPT/E1 Line Interface is a fully integrated line transceiver capable of operation at the domestic DS1/T1 carrier rate (1.544 Mbits/s) or the international CEPT/E1 rate (2.048 Mbits/s). The T7290A device combines features found in existing line-interface devices with additional desirable fea- tures. The on-chip, low-impedance output drivers provide shaped waveforms to the transformer, guaranteeing template conformance. The T7290A device inter- faces to the digital cross connect (DSX) at lengths up to 655 feet during DS1 operation and interfaces to line impedances of 75 Q or 120 Q during CEPT oper- ation. The device line interface also can transmit waveforms compatible with T1 lines. The T7290A line interface provides phase-locked loop clock recovery and data retiming on received data. Also, on-chip, selectable jitter attenuation is available. The jitter attenuator can be placed in the receive or transmit data path. No external crystals are required with the T7290A device. Digital contro! circuitry allows for multiple loopbacks, testing, and alarm status monitoring. A microproces- sor interface option allows for either control via a microprocessor or direct pin-selectable control (hardware mode). The T7290A device is manufactured by using a low- power CMOS technology and is available in a 28-pin, plastic SOJ package or a 28-pin, plastic DIP pack- age. Note: Modification of an existing T7290 application may be required when migrating to a T7290A- based architecture. The functions of the TBS, TSC, LP1, DLOS, and LOS pins have been changed or modified. Please refer to the T7290A Migration from T7290 section of this data sheet. Me 00500e6 0032711 b1b MmData Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Table of Contents Contents Page FOAtUICS ......ccccecccccesceccessccceesseeessnsssuceceussssccenesecscaaeceenessaaenseesonaneeasescescessseneeeessnanensnengenaeessasosaneccensensenseaseneanesenaegsnoree 1 D@SCTIPtON........cecesecsesecescesssceesesteectescrsesesesesessncasneseeesecaserseneseeerssserssessssseseneesauansusecensaanenceenenanssassensncoonoessanaseressensnss 1 Pin Information ...........::cc.c-ccceccsccsesscesscccescesceccerensansecenscneerssnacsescacecesarscceeesanaeessnsuereesesesaeccessossusssasousensenereceessseesesanes 4 ROCCIVED ...ccccccsseccccccssecscesssceescssccusssoeseccesscuscescecssnnneetansneeessnsrercsssasaususersceenannetecssuaneeseassgcauessssonaussonseneressseceeeassageaente 6 Data Interface .........:ccccccssecccsccececcssseecssssnsseecesssesasneecsuevscuseseseeesscestessssaessunsonsesseeesasseceesccronsssaaaensavseartorerscensessnanes snes 6 Clock Recovery and Data Retiming.............cscsssserecceccesssssrssssssensasssananeesesseaeassnsousensanensnnanenenncnsassanesserenenensaenes 6 Frequency-ACquisition Aide ...........csccssssssesssssseseseneneceeersssosssersesnsvsnscsnsnenesgensassnesssseasesesaneenerevenenensercocenaeassnenes 6 Witter ccccccccccocccsccsccsesccccececesscecocesesseeccsesscsccnenscesescessencneceeecersresssauasacuauansssssanenensseeccssseesreuseneaaneeceussoreseesenesepesseanaacanas 7 Data Patterns.........cccccccccssssesccocecesscsscssssssseensanesessusesceecsenecsseeesceceessuasecususansavecsecessseasesnaesensaesenenerserasseuanseeeeecaneansees 8 LOSS Of SIQKal .........ccssssescesesscsserstssssessssessesnearsesesesusceeesessesssensnenseenatanseasseasseeseessenessatneananseneneacssasicecseneacessonstetans 8 TrANSMitter .........cccscccsscecscsscecscocscsssscsssneccesscecenerseseecesseeesecscsueseoessseuesasseeerenesssessseanecesessaneonaneeserersunensecensaesenssaeennnees 8 Output Pulse Shape 0... cscsssesessesssssseeeeesesenensscestseseseeesnseensnscanansessssesesseeseneseneanscausnnaesesereegecssocsaessacasaasnenananenes 8 Output Pulse Generation .............sssssscssssssesessessenenenesescesessneneseeerseerenensonsesssseeesssseeneesensenenensscneesecenseecersaananenennes 10 Jitter AtteMUator ............ccccccccscccccccessecsessosnsceececeeececensnnensnsecerencecceeseseessoussseneseesessanssscuueaocsaonsessesessseauenseseesenuneenaaeeeees 11 Alarms and Maintenance..........0:...:cccccscccescccessecesssneceseeessnesvscesesccesecsssusntessecusasunnapesseressuaeessocsaeaseussanerssrassaeeeasseesaes 13 Digital Loss of Signal (DLOS)...........:cssssssssssssssssssseestseensessenerecsssnsnsvensuseesneassensnsscensassanensnasansnenassorsacoseesssesene ss 13 Output Loss of Signal (OUT-LOS)..........ccecsesseseesssseseecesseeeessenssneasensensesnsenaversesssensnseneaensenneneentaescnecssenaenecesanens 13 Jitter Attenuator Alarm (ESA) ........ccssssscseccssesscsssssssensnsensesensenserenessnseesnessescesessesasscsscevensseesesasenasensaeaeaneeauerenanse 14 Transmitter Short Circuit... .cccccccccecccessseecsccesssscecesneeecenanseressnseceesessccessssnsceeenesaaanseesnsspepaaeeesssosesseusanenscecereeneenesss 14 AIS (Blue Signal) Generator 0.0... sssscsseessssseessseeeenesesenseesesenstassscensnsnanansennseeneassaeseneenseneecenenconenssecesesasansaegetes 14 LOOPDACKS ........eeesesecesesceescseescsesnscsesesneessnsnsenesesnssnsescereccersenensessaasavaenesscesoseressscoseessssescanaeasacensnertececensscccecaeansenenss 14 Microprocessor Interface .........ssecsssecsecesserserscsecsenesesseseaesensesensseensssesesecessssessasssasnasnunsnseesrescassesenssaseananeanonenensates 14 IN-Circuit TeSting ............-ececesssssesseccescesseeessessesceeeseeasseseeanneesessesussseosssssussenasesategeaeusnsaneaserececesaaeccasanansosarensanstets 14 Absolute Maximum Rattings...........cscccccssesesesssssssseuseeseessesnesssssseessessecrscssesuaneesonecsossussatenssenaecauansaaeasnenseerareransaaes 15 Handling Precautions ..........sscesecessssssssesecessenanseeseossenseesescceseesacseesasssusunseosucaceesorscsseesenesenussnsaccantanesasataseccesessessensnts 15 Electrical Characteristics ......0.......cccccscssssssssecnssessecsscesersessecessesdseaceuscusoncesecnaaeseasceeaaneenssassesneaevarsasseoesoarensraeeeasenaes 16 Operating Conditions ............ccsssssssseseeeeseeseneeesenssssnesessenessneenenenensssnssseesessreceeseenasasaeenuauseacaseesensneecacsenananeasnnaes 16 Timing Characteristics 0.0.0... cscescssssessessssssseseeesseecanneeasscssnsseeceeceescssnsnsessessenausenesesenneanenessseseaseneenaanensenanenesecrses 17 Applications ...........c-cscesssessssscsesenserscsssssnsnseesesescenanaseanenenssnnteaesseesorsssseesseonsssaseustsasneseenanessensssanenanaacouaconsasscacanenesses 19 Lime Termination ..........:cccsccccsccessceccocnssccessssscesecssescccesaesecsceeenessencsausnaneasescauceeetsneeeesseenseasssaaacoueusnersuasersecsaanesaees 19 Outline Diagrams. ..........-.ccccsesceccsesessssssssssssssseesessseeseneesenseesensenessansasacaceeseracassseaseusucsecescesessnansustensenssesscasareneneessnaeatas 21 2B-Pin, Plastic SOU... csccssesssscccessnscesesecssasseeesesnsasusanaseesneeesscsenaasseeeneceseeeseeaaneeaseneensaesnreesseneeeseeneneeneeyennyegey 21 28-Pin, Plastic DIP............sssssssssccesssccssseesceesesenssausesseussnessesesensessesecuseesseasesesnnesensnscsssessenseeeeeneeasaaetnaesneanensece 22 Ordering Information............sescccssssesescssssesssessnsseeseansceeesececserenessssenssnssensnsvausnsusenesesearessneseseasarssssasnsnesennesenesescsnseses 22 T7290A Migration from T7290..........:.sssscssssssssssssereesseesssenesessessensssesasnenenerassesesesscssscsacsseseasancanstensnensaeacansesaseseneusanes 23 DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates..............sssssscsssssersessscesnseeeeneatsces 23 2 Lucent Technologies Inc. M 0050026 0032712 552T7290A DS1/T1/CEPT/E1 Line Interface Description (continued) Data Sheet April 1998 5-2484(C)r.6 dQND a0qA, VOND voor o$f<> sgo i Ed] @d00710->| 300030 | zd1 dOO10__> bi dT ZaGOW O-> sova [2300 }3dOW 0--] 5 -_ 130w SOTLNO tat 030] gh }_ 93 Z03 0 |___ ge 205 Loa O> }____ 193 TOS $a o___-________ sal { TOWN 0X3 o> yx TyNDIS Y HOLINOW ed? zaqow Sa OSL | LIWSNVHL a ywOOTO | 4O SSO A r W1OLO- ry oa oO 2 WIVONIo VivddL 72 1) PAD PKA ene? le z | NN Oo Pt kK 2 ; SHSAING 72 0a 7204 104 w19S + NALLY | YaLLIt + sore on aL MIOXS { vSa f P| Nowisinooy | woxa Zz > oaus tt | zaqdow ' , you rea LdOW \ <q LY ivoNe C7 wioyen ; Td 5 <t- | 73 / _ i ry? ~ HL sold y_Y ed 1a | solv | LaGOW 7 sora sow SOTNIO NA Figure 1. Block Diagram @@ 00500eb 0032713 4455 Lucent Technologies Inc.Data Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Pin Information Ec1c)1 = 2ebece TRI C] 2 277 Ec3 Vopa [] 3 26 [ GNDp GNDa [1] 4 251 re R1 CIs 2417) voop Tile 231) te MODE2 [7 T7290A 22 [7] RNDATA MODE1 CJ 8 21 {4 RPDATA Loops [J 9 20) RCLK LooPA [J 10 19] TNDATA Tes 4 11 18] TPDATA IN-LOS C 12 17 Tctk Esa (13 16] EXcLK out-Los ( 14 15 CS -1810 (F).a Table 1. Pin Descriptions Figure 2. Pin Diagram Pin Symbol Type* Name/Function 1,27,28| EC1, EC3, EC2 iS | Equalizer/Rate Control 13. Three control leads for selecting transmit equalization. 2 TRI [" | 3-State (Active-Low). This pin is set low to configure all output buffers into a high-impedance state during in-circuit testing. 3 Vpbpa |5V+5% Analog Supply. The powerup rise time (0 V to 4.75 V) must be less than 15 ms. 4 GNDa | Analog Ground. 5 Ri | | Receive Bipolar Ring. Negative bipolar receive data. 6 T1 | | Receive Bipolar Tip. Positive bipolar receive data. 7,8 MODE2, MODE1 9 | Mode Select 2 and 1. Two control leads for selecting clock and data paths through the jitter attenuator. 9,10 | LOOPB, LOOPA I | Loopback Control B and A. Two control leads for selecting clock and data loopback paths. 41 TBS Io | Transmit Blue Signal (AIS). This pin is set high to transmit the blue signal (all 1s). A remote loopback (LP2) has priority over the transmit blue signal. 12 IN-LOS O | Input Loss of Signal. This pin is set high if analog loss of signal at the receiver inputs is detected or if digital loss of signal of the recovered data is detected. IN-LOS can be tied directly to TBS to initiate a transmit blue signal upon loss of signal. * |= input, O = output, I! = input with pull-up, I = input with pull-down. Lucent Technologies tnc. M@ 0050026 0032714 325Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol Type Name/Function 13 ESA | Jitter Attenuator Alarm. This pin is set high if the phase jitter of the incom- ing signal exceeds the tolerance of the jitter attenuator's buffer. This may result in a loss of receive data. 14 OUT-LOS O | Output Loss of Signal. This pin is set high when either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent. 15 cs i? | Chip Select for Microprocessor Interface (Active-Low). CS loads data into the device on its falling edge and latches the data on its rising edge. CS is set low for hardware mode. 16 EXCLK | | External Clock. DS1/T1 clock signal (1.544 MHz + 130 ppm) or CEPT/E1 clock signal (2.048 MHz + 80 ppm) for transmit blue signal, jitter attenuator calibration, and PLL acquisition aid. EXCLK must be an independent clock to guarantee device performance for all specifications. This clock should be continuously active (i.e., ungapped and unswitched) and void of jitter for the above features to operate. 17 TCLK 1 | Transmit Clock. DS1/T1 clock signa! (1.544 MHz + 130 ppm) or CEPT/E1 clock signal (2.048 MHz + 80 ppm). 18 TPDATA 1 | Transmit Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) positive bipolar data. 19 TNDATA | | Transmit Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) negative bipolar data. 20 RCLK O | Receive Clock. Recovered receive clock signal for the terminal equipment. 21 RPDATA O | Receive Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) recovered positive data (NRZ). 22 RNDATA O | Receive Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) recovered negative data (NRZ). 23 T2 QO! Transmit Bipolar Tip. Positive bipolar transmit data. 24 Vppp |5V+5% Digital Supply. The powerup rise time (0 V to 4.75 V) must be less than 15 ms. 25 R2 O | Transmit Bipolar Ring. Negative bipolar transmit data. 26 GNDpb | Digital Ground. * | = input, O = output, !4 = input with pull-up, [9 = input with pull-down. Lucent Technologies Inc. 5 MM 00500eb 0032715 2b]T7290A DS1/T1/CEPT/E1 Line Interface Data Sheet April 1998 Receiver Data Interface The receive line-interface transmission format of the T7290A device is alternate mark inversion (AMI). The receive digital output format is dual-rail, nonreturn to zero (NRZ). Receiver specifications are shown in Table 2. Clock Recovery and Data Retiming The bipolar input signals from T1 and R1 are peak- detected and sliced by the receiver front end. Timing recovery is performed by a phase-locked loop (PLL) that locks an internal free-running, current-controlled oscillator (ICO) to the data-rate component. EC1, EC2, and EC3 rate control inputs must be set appropriately for DS1 or CEPT/E1 operation. Table 2. Receiver Specifications Frequency-Acquisition Aide For robust operation, PLL is enhanced with a fre- quency-acquisition capability. The frequency-acquisi- tion circuitry is intended to guarantee proper phase locking during start-up situations, such as powerup or data activation. Once the T7290A device is phase- locked to data, the frequency-acquisition mode is not activated unless a digital loss of signal occurs, in which case RCLK is frequency-locked/phase-locked to EXCLK. RCLK is always active and does not have any instantaneous phase hits or discontinuities. A continuously active (i.e., ungapped and unswitched) reference clock must be present at EXCLK to enable the frequency-acquisition circuitry. EXCLK must be an independent reference such as an oscillator or system clock for proper operation. The EXCLK clock frequency must be 1.544 MHz + 130 ppm for T1/DS1 operation or 2.048 MHz + 80 ppm for CEPT/E1 operation. Parameter Min Typ Max Unit Receiver Sensitivity:* DS1 0.85 _ _ Vp CEPT 0.7 _ _ Vp Analog LOS Level: DS1 _ 0.48 _ Vp CEPT _ 0.28 Vp PLL:t 3 dB Bandwidth _ 33 _ kHz Peaking _ 1.2 2 dB ICO Free-run Frequency Error _ _ +6 % Input Density (1s)* 12.5 _ % Return Loss: 51 kHz102 kHz 12 _ _ dB 102 kHz2.048 MHz 18 _ dB 2.048 MHz3.072 MHz 14 _ _ dB * Values shown are for flat loss only. Receiver also meets ITU-T G.708 interface immunity test (6 dB cable loss with 18 dB interference) for CEPT/E1 operation. + Transfer characteristics (1/8 input). + The maximum number of consecutive zeros = 15. Return loss specifications according to ITU-T G.703/RC6367A (CEPT only). @ 0050026 0032716 17h Lucent Technologies Inc.Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Receiver (continued) Jitter PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. PLL has a minimum input jitter tolerance exceeding all requirements shown in Figure 3. The measured receiver jitter tolerance for DS1 and CEPT operation is also shown in Figure 3, with pseudorandom input data (2'5 1) and with EXCLK synchronous with the data source. The receiver transfers incoming jitter to RCLK with no more than 2 dB of gain at any frequency, which can be further reduced with the jitter attenuator. 500.0 F TRI-TSY-000170, PUB 43801 NY J PUB 62411 p * oo -*. PUB 62411 (LOOP TIMED) = 100.0 NO AA J 3 NOMS MINIMUM JITTER ww 50.0 NN \ [ ATTENUATOR PERFORMANCE Qa \ \ N 2 23.0 + oe 5 \NON\ MEASURED RECEIVER 3 SSO J) EEN 2 10.0 TAT SUB 43808 NS N NOT ACTIVE) tu MEASURED E 5.0 F- ------X RECEIVER DS1 Y \ PERFORMANCE < je N NY (JITTER ATTENUATOR Ww YN OS NOT ACTIVE) o 1.0 \ y , ITU-T G.823 a 0.5 Oo NON ce ee 0.1 l | | 1 10 100 4000 100,000 JITTER FREQUENCY (Hz) se11671C)04 Data Points (Hz, U.I.) ITU-T TR-TSY-000170, | TR-TSY-000009, AT&T AT&T Measured Measured G.823 AT&T PUB AT&T PUB PUB PUB Receiver DS1 | Receiver CEPT 43801 43802 62411 62411 Performance Performance Looped | (BER=10) | (BER =10~) Timed 1,2.9 10, 300 10,5 1, 138 1, 138 2.0k, 6.51 2.0k, 9.43 20, 1.5 10k, 0.3 500, 5 48, 138 85, 138 5.0k, 2.03 5.0k, 2.84 2.4k, 1.5 50k, 0.3 8k, 0.1 10k, 0.2 10k, 0.4 8.0k, 1.12 8.0k, 1.70 18k, 0.2 _ AOk, 0.1 100k, 0.2} 100k, 0.4 10k, 0.97 10k, 1.38 100k, 0.2 _ _ _ 15k, 0.84 15k, 1.00 _ _ _ 20k, 0.66 20k, 0.84 _ _ _ _ _ 30k, 0.52 30k, 0.57 _ _ AOk, 0.49 40k, 0.48 _ 70k, 0.48 70k, 0.47 _ _ _ _ 100k, 0.48 100k, 0.47 Lucent Technologies Inc. Figure 3. PLL Jitter Tolerance Requirements MM 00500eb 0032717 034Data Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Receiver (continued) detector output becomes active. Hysteresis (250 mV) is provided in the analog detector to eliminate ALOS chattering. Either the analog or the digital detector sets Data Patterns IN-LOS high. Any data pattern with a minimum long-term 1s density The time required to detect analog loss of signal of 12.5% with 15 or fewer consecutive Os is allowed. (ALOS) depends on the incoming signal amplitude before it disappears. Typical ALOS detection times are given in Table 3. Loss of Signal Table 3. Typical ALOS Detection Times Both digital (DLOS) and analog (ALOS) loss-of-signal . i = detection is used in the T7290A device. The digital sig- Signal Amplitude Typical ALOS nal detector is described later under the Alarms and (Vp) Detection Time (ms) Maintenance section. The analog signal detector uses 3.6 5.0 the output of the receiver peak detector to determine if 2.5 3.7 a signal is present at T1 and R1. If the input amplitude 1.7 28 drops below approximately 0.48 Vp for DS1/T1 opera- 1.0 1.4 tion or 0.28 Vp for CEPT/E1 operation, the analog Transmitter Output Pulse Shape Transmitter specifications are shown in Table 4. The T1 pulse shape template is specified at the network interface as shown in Figure 4. The DS1 pulse shape template is specified at the DSX and is illustrated in Figure 5. CEPT transmit waveforms at the device output conform to the template shown in Figure 6. Table 4. Transmitter Specifications Parameter Min Typ Max Unit Output Pulse Amplitude:* T1 2.7 3.0 3.3 V DS1 (at DSX) 2.4 3.0 3.6 V CEPT (into 75 ) 2.13 2.37 2.61 V CEPT (into 120 Q) 2.7 3.0 3.3 V Output Pulse Width: T1 279 324 369 ns DS1 330 350 370 ns CEPT 219 244 269 ns Output Power Levels: T1 (3 kHz band at 772 kHz) 12.0 16.5 19.0 dBm T1 (3 kHz band at 1544 kHz)t -25 -39 dB DS1 (2 kHz band at 772 kHz) 12.6 16.5 17.9 dBm DS1 (2 kHz band at 1544 kHz)T -29 -39 dB Positive/Negative Pulse Imbalance: Ds1* 0.1 0.5 dB CEPTS 2 +5 % CEPT Zero Level** _ 1 10 % Return Loss:tt 51 kHz102 kHz 8 _ _ dB 102 kHz2.048 MHz 14 _ _ dB 2.048 MHz3.072 MHz 10 _ dB * In accordance with the interfaces described in the Line Termination section under Applications. + Below the power at 772 kHz. + Total power difference. , Percentage of the pulse amplitude and pulse width. Percentage of the pulse amplitude. tt Meets CH-PTT return loss specifications (CEPT only). 8 Lucent Technologies Inc. M@ 0050026 0032714 T70Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Transmitter (continued) Output Pulse Shape (continued) 1.0 - 0.5 5 NORMALIZED AMPLITUDE (A) ! ! po J 250 500 750 TIME (ns) ! 1000 1250 5-1604(F)r.3 T1 Isolated-Pulse Corner Points According to NORMALIZED AMPLITUDE (A) ! 250 500 750 TIME (ns) 1000 1250 5-1160(C)r.6 DSX-1 Pulse Template Corner Points According FCC Part 68 to CB119 Maximum Curve Minimum Curve Maximum Curve Minimum Curve Normalized Normalized Normalized Normalized ns Voltage ns Voltage ns Voltage ns Voltage 0 0.05 0 0.05 0 0.05 0 0.05 242 0.05 350 0.05 250 0.05 350 0.05 325 0.80 350 0.50 325 0.80 350 0.50 325 1.20 400 0.90 325 1.15 400 0.95 425 1.20 500 0.95 425 1.15 500 0.95 500 1.05 600 0.90 500 1.05 600 0.90 675 1.05 650 0.50 675 1.05 650 0.50 728 0.05 650 0.45 725 -0.07 650 0.45 1000 0.05 800 0.45 1100 0.05 800 0.45 4250 0.05 896 0.26 1250 0.05 925 0.20 _ 1100 0.05 _ 1100 0.05 _ _ 1250 0.05 _ 1250 0.05 Note: Successive corner points are joined by straight lines. Figure 4. T1 Isolated-Pulse Template Lucent Technologies Inc. Note: Successive corner points are joined by straight lines. Figure 5. DSX-1 Isolated-Pulse Template @@ 00500e6 0032715 507Data Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Transmitter (continued) Output Pulse Shape (continued) 269 ns ney ae y, SL, i, es YY, V= 100% yio% _ Z pox T Y | = eae-"50 Z 6 nominal PULSE el Vv AIT PA | AV AV Ai AW Aly AI sore ALY AV, 4\V | y, y ye | 4 4 | ! ey : mE apm iv gr Fi0% 4 A, 10% PZ 20% !] oy 7 ee) - 4 ns (244 + 244) -3145(C)r.7 Note: V corresponds to the nominal peak value. Figure 6. ITU-T G.703 Pulse Template Output Pulse Generation The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal to a balanced bipolar data signal (AMI format). Positive 1s are produced by a positive pulse on device pin T2, and neg- ative 1s are produced by a positive pulse on device pin R2. Binary Os are converted to null pulses. All pulse shapes are controlled on-chip according to equalizer control inputs, as defined in Table 5. Transmitter specifications are shown in Table 4. Table 5. Equalizer/Rate Control Clock Transmitter Maximum Service Rate Equalization* | CableLosst; EC1 EC2 EC3 T1 1.544 MHz 22% 0 i) 7) 0 ft.131 ft. 0.6 0 0 1 131 ft.262 ft. 1.2 0 1 0 DS1 1.544 MHz 262 ft.393 ft. 1.8 0 1 1 393 ft524 ft. 2.4 1 0 0 524 ft655 ft. . 3.0 1 0 1 75Q _ 1 1 0 CEPT 2.048 MHz 1200 7 1 7 * Distance to DSX in feet for 22-Ga. PIC (ABAM) cable (DS1 only). Use maximum loss figures for other cable types. dB at 772 kHz. + According to FCC Part 68, Subpart D, Option A for 0 dB line build-out. 10 Lucent Technologies Inc. M@ 00500eb 0032720 b25Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Jitter Attenuator Jitter transfer functions describe the amount of jitter that is transferred from the input to the output of the specified equipment. The jitter transfer functions are affected by the jitter attenuator circuitry, which can be placed in the receive data path, placed in the transmit data path, or bypassed. Placement of this circuit is con- trolled as described in Table 6. The external clock (EXCLK) must be present for the attenuation function to operate. When attenuation is selected, the T7290A device exhibits a jitter transfer function that has no peaking and a single 3.6 Hz pole frequency (DS1) or 4.8 Hz pole frequency (CEPT). Figure 7 displays a typ- ical DS1 jitter transfer function for a constant input jitter amplitude of 2.0 U.I. peak-to-peak. The amount of generated output jitter when no input jit- ter is present is measured by using the scheme shown in Figure 8. The jitter filters depicted represent the AT&T PUB 62411 specification for a 1.544 MHz data rate. The jitter produced at the labeled points does not exceed the following peak-to-peak levels: 0.05 U.I. at point 1, 0.025 U.1. at point 2, 0.025 U.1. at point 3, and 0.02 U.I. at point 4. A similar test can be performed for ITU-T 1.431 qualification at the 2.048 MHz data rate, in which two jitter filters are 20 Hz100 kHz (0.125 U.I.) and 700 Hz100 kHz (0.02 U.1.). The jitter tolerance of the attenuator meets the require- ments of the TR-TSY-000009, AT&T PUB 43802, and ITU-T G.823 (see Figure 3). The attenuator also ensures that jitter accommodation is a minimum of 28 U.1. peak-to-peak (DS1) or 40 U.I. peak-to-peak (CEPT) (1 U.I. = 648 ns [T1/DS1] or 488 ns [CEPT}) during attenuation. The jitter attenuation function is identical when placed in either transmit or receive path. Ideally, the tolerance of the attenuator is +32 bits (64 U.I.). However, if Af (Hz) = frequency (EXCLK) frequency (input clock) and N = 23 (DS1) or 30.5 (CEPT), then the tolerance is degraded and equals: 64-2x (RND_U p(ABStan 4 1)) (U.L.) Figure 9 shows the phase step response (DS1) of the attenuator given Af. The response is based on a phase offset (U.1.) generated by the read pointer of the buffer. It is this phase offset that degrades the attenuator's tol- erance. / 40 dB/DECADE a -10- 2 ITU-T G.735, z 20 dB/ ITU-T 1.431 O -20+ DECADE = TR-TSY- < 000009, 3 ~30 TYPICAL PUB 43802 Gi PERFORMANCE E 20 dB/DECADE Ee -40r th E Ser 20 dB/DECADE = -60 -70 oo l 1 10 40 100 350! 1k 2.5k | 15k 400 10k JITTER FREQUENCY (Hz) -1311(C)r.4 Data Points (Hz, dB) TR-TSY-000009, ITU-T G.735, AT&T PUB 43802 ITU-T 1.431 1,0.1 10, 0.5 350, 0.1 40, 0.5 2.5k, 33.6 400, -19.5 15k, 49.2 15k, -19.5 Figure 7. Jitter Transfer Function of the Jitter Attenuator Lucent Technologies Inc. 11 M@ 0050026 0032721 54SData Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Jitter Attenuator (continued) When the T7290A device is used only as a jitter attenuator, loopback 1 (LP1) should be active and the attenuator must be placed in the transmit path (MODE1:2 = 01). Table 6. Connectivity of Jitter Attenuator Connectivity of Jitter Attenuator* MODE1 MODE2 Bypass 0 0 Transmit Path 0 1 Receive Path , 1 0 Test Modet 1 1 * The jitter attenuator must be enabled after Vop exceeds 4.75 V during device powerup. + Jitter attenuator is powered down during this mode (see Table 8 under the Electrical Characteristics section). + Not used for normal operation. FILTERS (SLOPES MUST BE 20 dB PER DECADE) 4 _ / ) = TOEACH POINT 10 Hz 8 kHz PEAK DETECTOR 3 > O MEASURED JITTER 8 Hz 40 kHz SIGNAL"]_ DETECTOR [? (700 Hz) (100 kHz) TRUE RMS VOLTMETER / | \ 2 ee J 10 Hz 40 Wz -o TO EACH POINT (20 Hz) (100 kHz) 1 SPECTRUM o ---"| ANALYZER -1163(F 2 Figure 8. Measurement of Generated Jitter 12 Lucent Technologies Inc. @! 0050026 0032722 4Tl omData Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Jitter Attenuator (continued) 20 A PHASE STEP RESPONSE (lafl = 0 400 Hz) Var t -__ _- 15 _ of TY TT 5 READ COUNTER OFFSET (U.I.) TTTT TT T oOo 50 100 150 TIME (ms) -2485(C)r.3 Figure 9. Jitter Attenuator Phase Response Alarms and Maintenance Digital Loss of Signal (DLOS) A digital loss of signal (DLOS = 1) is indicated if 128 or more consecutive Os occur in the receive data stream during DS1/T1 operation. During CEPT operation, a DLOS is indicated when 32 or more consecutive 0s occur in the receive data stream. DLOS is then deacti- vated when the ones density exceeds 12.5% and there are no more than 15 consecutive Os (T1, DS1, and CEPT), signifying the return of good signal. DLOS deactivation monitors the data in fixed 32-bit windows. Each window must have at least four 1s with no more than 15 consecutive 0s. Consecutive Os are also moni- tored across the window boundary. This condition must persist for two consecutive 32-bit windows, at which time DLOS is deactivated at the end of the window. Upon DLOS detection, RCLK is phase-locked to the external clock (EXCLK) so that other system devices slaved to the line clock continue to operate without instantaneous phase hits or discontinuities. Either an analog loss of signal (ALOS) or a digital loss of signal (DLOS) activates the IN-LOS output pin. Lucent Technologies Inc. M@ 00500eb 0032723 338 Output Loss of Signal (OUT-LOS) An output loss of signal (OUT-LOS = 1) is indicated if either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent. If the jit- ter attenuator is placed in the transmit path, SCLK is monitored. If the jitter attenuator is not used in the transmit path, TCLK is monitored. For every ten clock periods of the PLL oscillator clock, denoted as UGRCLK in Figure 1, a strobe is generated. If a single transmit clock period occurs between strobes, then OUT-LOS = 0. If no transmit clock period occurs between strobes, then OUT-LOS = 1, and the output drivers (T2 and R2) are placed into a high-impedance state and no data is transmitted. UGRCLK is always present, even in the absence of both EXCLK and T1/R1 input data; therefore, UGRCLK is the most suit- able clock for monitoring OUT-LOS. 13T7290A DS1/T1/CEPT/E1 Line Interface Data Sheet April 1998 Alarms and Maintenance (continued) Jitter Attenuator Alarm (ESA) A jitter attenuator alarm (ESA = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenua- tor. Bit errors occur when ESA is active. This signal is asserted until error-free operation resumes. See Figure 9 to determine the tolerance limits of the attenu- ator. Transmitter Short Circuit A transmitter monitor is provided to detect nonfunction- ing links and protect the device from damage. If one of the transmitter's line drivers (T2 or R2) is shorted to the power supply or ground, or if T2 and R2 are shorted together, internal circuitry protects the device from damage. After 35 transmit clock cycles, the transmitter is powered up in its normal operating mode. The drivers attempt to correctly transmit the next data bit (+1, 0, or 1). If the short is still present, the transmitter is again internally protected for 35 transmit clock cycles. This process is continuously repeated until the short has dis- appeared. The TSC alarm is not available off-chip. AIS (Blue Signal) Generator When the transmit blue signal is set (TBS = 1), a contin- uous stream of bipolar 1s is transmitted onto the line synchronous with EXCLK. The TPDATA and TNDATA inputs are ignored during this mode. If the IN-LOS output is externally connected to the TBS input, an IN-LOS error initiates a transmit blue signal as long as IN-LOS = 1. Also, TBS input is ignored when a remote loopback is selected. There is no microprocessor inter- face for the TBS input, i.e., any change on the TBS pin is fed directly into the device and is not impeded by the CS function. Loopbacks The T7290A device has three independent loopback paths, which are activated as shown in Table 7. A local loopback (LP1) connects the jitter attenuator's output clock and data to the receive clock and data out- put pins. MODE1:2 = 01 must be selected for this loop- back to operate (jitter attenuator in the transmit path). Valid transmit output data continues to be sent to the network. However, if the transmit blue is initiated (TBS = 1), an all-1s signal is sent to the network and 14 does not corrupt the looped data. The IN-LOS alarm still monitors the entire receive function. A remote loopback (LP2) loops the recovered clock and retimed data into the transmitter and back onto the line. The receive front end, receive PLL, jitter attenuator (if engaged), and transmit driver circuitry are all exercised. The transmit clock, transmit data, and TBS inputs are ignored. Valid receive output data continues to be sent. to RPDATA and RNDATA. This loop can be used to isolate failures between systems. A digital local loopback (LP3) directly loops the transmit clock and data to the receive clock and data output pins. The blue signal can be transmitted when in this loopback. LP (rather than LP1) must be selected if MODE2 = 0. Table 7. Loopback Control Operation Symbol; LOOPA| LOOPB Normal _ 0 0 Digital Local Loopback LP3 0 1 Remote Loopback LP2* 1 0 Local Loopback LP1 1 1 * TBS is ignored. Microprocessor Interface A chip-select input (CS) configures the device in either hardware mode or microprocessor mode. The chip-select function applies to the following inputs: MODE1, MODE2, EC1, EC2, EC3, LOOPA, and LOOPB. in the hardware mode, any change on these asynchronous input pins is fed directly into the device. To maintain hardware mode, set CS = 0. In the microprocessor mode, new digital con- trol inputs are loaded into the T7290A device on the fall- ing edge of CS and are latched on the rising edge of CS. Figure 11 shows a timing diagram of this function. Note that there are special requirements only when using microprocessor mode. For example, the state of the input should not change while CS = 0. Also, the state of the internal latch is undefined (unknown to the user) until the first falling edge of CS is encountered. In-Circuit Testing The device has the ability to allow for in-circuit testing by activating the high-impedance mode (TRI = 0). During this mode, all output buffers (T2, R2, RCLK, RPDATA, RNDATA, IN-LOS, ESA, and OUT-LOS) are 3-stated. During the 3-stated condition, the absolute maximum voltage ratings must not be exceeded on any pin. Lucent Technologies Inc. MB 0050026 0032724 274 mmData Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be soldered safely at temperatures up to 300 C. Parameter Symbol Min Max Unit de Supply Voltage Range Vop -0.5 6.5 V Power Dissipation Pp _ 500 mw Storage Temperature Tstg -65 125 C Maximum Voitage (any pin) with Respect to Vpp 0.5 V Minimum Voltage (any pin) with Respect to GND _ -0.5 _ Vv Maximum Allowable Voltages (T1, R1) with Respect to GND _ -5.0 5.0 Vv Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 Q, capacitance = 1000 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here is obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage T7290A-EL >1200V T7290A-PL >1200 V Lucent Technologies Inc. 15 M@@ 0050026 0032725 100 myData Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Electrical Characteristics Operating Conditions 40 C < Tas +85 C, Vop = 5 V + 5%, except as noted. Vop rise time (0 V to 4.75 V) must be less than 15 ms. Table 8. Power Specifications Parameter Symbol Min Typ Max Unit Power Dissipation:* Pp Without Jitter Attenuator: T1 _ 125 131 mw psit 132 139 mW CEPT (75 Q) 126 132 mw CEPT (120 22) _ 120 126 mW With Jitter Attenuator: T1 _ 165 173 mw psit 172 181 mw CEPT (75 Q) _ 174 183 mw CEPT (120 Q) 168 176 mW * Conditions with 50% 1s on the transmit side, Ta = 25 C, Von = 5 V. t+ Equalizer settings: EC1 = 0, EC2=1, EC3=1. Table 9. Logic Interface Characteristics An internal pull-up device is provided on the TRI lead. Internal pull-down devices are provided on the following leads: CS, MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, and LOOPB. The internal pull-up or pull-down devices require the input to source or sink no more than 20 pA. Parameter Symbol Min Max Unit input Voltage: Low Vit GNDb 0.8 Vv High Vin 2.0 Vopo Vv Output Voltage: Low VoL GNDb 0.4 Vv High Von 2.4 Vopp Vv Input Capacitance Ci 20 pF Load Capacitance CL _ 40 pF Source Current [source _ 4.9 mA Sink Current Isink _ 49 mA 16 Lucent Technologies Inc. me 005002b 00327?eb O87Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Timing Characteristics All duty-cycle and timing relationships for receive and transmit data signals are referenced to a TTL, 1.4V threshold level. Figure 10 shows this timing. Table 10. Interface Data Timing (See Figure 10.) Symbol Parameter Min Typ Max Unit _ TCLK Duty Cycle 40 50 60 % tTCLTCL | TCLK Clock Period: DS1/T1 * 647.7 ns CEPT 488 ns tTDVTCL | Transmit Data Setup Time 50 _ _ ns tTCLTDX | Transmit Data Hold Time 40 _ ns tTCH1TCH2 | Clock Rise Time (10%90%) _ _ 40 ns tTCL2TCL1 | Clock Fall Time (10%90%) _ _ 40 ns tRDVRCH | Receive Data Setup Time 140 _ _ ns tRCHRDX | Receive Data Hold Time 180 ns tRCLRDV | Receive Propagation Delay _ _ 40 ns * A tolerance of +130 ppm. + Atolerance of +80 ppm. TCLK }e tTCLTCL tTCH1ITCH2 RPDATA | eTDVTCL {TCLTDX TPDATA OR x TNDATA tRCLRD RCLK PN of \ tROVRCH OR RNDATA F SV Figure 10. Interface Data Timing Lucent Technologies Inc. M! 0050026 O03e7e? T3835 5-1156(C)r.8 17Data Sheet T7290A DS1/T1/CEPT/E1 Line Interface April 1998 Timing Characteristics (continued) Table 11. Microprocessor Interface Timing (See Figure 11.) Symbol Parameter Min Max Unit tSVCSL Control Signal Setup Time 50 _ ns tCSLCSH Control Signal Pulse Width Time 40 _ ns tCSHSX Control Signal Hold Time 40 _ ns tCSH1CSH2 | Control Signal Rise Time (10%-90%) 40 ns tCSL2CSL1 Control Signal Rise Time (10%90%) _ 40 ns tCSL2CSL P tCSH1CSH2 cs MOpeD 1 tCSLCSH> EC1 x E02 XK EC3 4 LOOPA LOOPB tSVCSL bk+ w-| tCSHSX bqe Figure 11. Microprocessor Interface Timing -1165(F)r.4 18 Lucent Technologies Inc. MM 00S00cb 0032728 31TData Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Applications Line Termination For the following applications (shown in Figures 12-15), the Lucent 2741 and 2745 Series transformers are rec- ommended. The same transformers used for the T7290 device can be used for the T7290A device. The tolerance of all transformer turns ratios is a maximum of +2%. The tolerance of all resistors in the transmit path (excluding the cable termination) is a maximum of +1%. RECEIVE DATA > ee Ti RPDATA } 500 2 RECEIVE RNDATA +} 200 2 INPUT = 500 Q RCLK ->_> + 12 L Ri Voop Pt 8 VDDA T7290A 1 uF GNDo - TRANSMIT DATA GNDa SS ee T2 = 1009 $ LoaD | TRANSMIT TPDATA |~+_ OUTPUT TNDATA }-_ % R2 TCLK 1.08:1 5-1152(C)r.6 Figure 12. DS1 Application for Twisted-Pair Interface RECEIVE DATA>- 1 RPDATA |} EQUAL: RECEIVE RNDATA }_ IZER INPUT ACK 12 7 I Rt FOR 0 dB LINE BUILD-OUT. GNDpb +_ TRANSMIT DATA GNDa 21.52 St e AWW T2 TPDATA be 100 08 LOAD TRANSMIT Vpop +5V WAVEFORM MEETS FIGURE 3 Vppa , i TEMPLATE AT THIS POINT T7290A 1 pF OUTPUT TNDATA e 21.52 95 1.36:1 WwW R2 TCLK + -1153(C) Figure 13.T1 Application Diagram Lucent Technologies Inc. 19 M 0050026 0032729 456 mmT7290A DS1/T1/CEPT/E1 Line interface Data Sheet April 1998 Applications (continued) Line Termination (continued) RECEIVE DATA _ ee 71 RPDATA L}-- 866 2 RECEIVE RNDATA +> 200 2 INPUT = 866 2 RCLK -> - 1:2 Rt Voop Rona 45V VDDA T7290A 1 pF GNDob <+_ TRANSMIT DATA 26.19 GNDA ee T2 = TRANSMIT TPDATA |___ 120 2 3 LOAD OUTPUT 26.10 TNDATA }_ R2 TCLK |4___ 1.36:1 5-1154(C) Figure 14. CEPT Application for Twisted-Pair Interface RECEIVE DATA = eo. Ti RPDATA |--> 2702 RECEIVE RNDATA - 200 2 INPUT = 2702 RCLK }> L ~ 4:2 RI = Vpop t+ +5V VDDA T7290A 1 pF GNDpb ~< TRANSMIT DATA 15.49 GNDa ee T2 = TRANSMIT TPDATA t+ 7523 LOAD OUTPUT 15.49 TNDATA - WA-] R2 TCLK tq_ L 1.36:1 5-1155(C)r.6 Figure 15. CEPT Application for Coaxial interface 20 Lucent Technologies Inc. M 0050026 0032730 575 aData Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Outline Diagrams 28-Pin, Plastic SOJ Dimensions are in millimeters. rTz Oo ; PIN #1 IDENTIFIER ZONE Ww et __ __ __ __. SEATING PLANE |S [0.10 etter TYP 0.51 MAX _. = 0.79 MAX -4413(C).14 Number of Package Dimensions (SOJ) Pins (N) Maximum Length Maximum Width Maximum Width Maximum Height Including Leads (L) Without Leads (B) Inciuding Leads (W) Above Board (H) 28 18.03 7.62 8.87 3.18 Lucent Technologies Inc. 21 M@ 0050026 0032731 404 aT7290A DS1/T1/CEPT/E1 Line Interface Outline Diagrams (continued) 28-Pin, Plastic DIP Dimensions are in millimeters. Vv rc ch PIN #1 IDENTIFIER ZONE --0- / i Lt } SEATING PLANE 0.38 MIN Data Sheet April 1998 laa 2.54 TYP 0.58 MAX _,| __ 5-4410(C).12 Number of Package Dimensions (DIP) Pins (N) Maximum Length Maximum Width Maximum Width Maximum Height Including Leads (L) Without Leads (B) Including Leads (W) Above Board (H) 28 37.34 13.97 15.49 5.59 Ordering Information Device Code Package Temperature Comcode (Ordering Number) T - 7290A - - PL 28-Pin DIP ~40 C to +85 C 106785645 T - 7290A - - EL 28-Pin SOJ 40 C to +85 C 106785637 22 Lucent Technologies Inc. Mi 0050026 0032732 340 mmtp Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface T7290A Migration from T7290 The T7290A is a replacement for the T7290 family of devices that includes the T7290-EL, T7290-PL, T7290-EL2, and T7290-PL2. The following list describes the functional changes made to the T7290 to produce the T7290A. Modification of an existing T7290 application may be required. u The TBS input of the T7290A directly controls the TBS function. The TBS function of the T7290 is gated by chip - select (CS). = The transmitter short circuit (TSC) output alarm has been eliminated; however, the transmit drivers are still pow- ered down under short-circuit conditions. The pin is renamed as output loss of signal (OUT-LOS) and indicates when either the transmit clock (TCLK) or the smoothing clock (GCLK) output of the jitter attenuator is absent. ws Loopback 1 (LP1) has been modified to route signals through the jitter attenuator only. The MODE2 pin must be set high for this loopback to operate (jitter attenuator on). a The digital loss-of-signal (DLOS) functionality is now compatible for use in systems that must be compliant with Bellcore TR-TSY-000009. a The loss-of-signal (LOS) output indication is renamed as input loss of signal (IN-LOS) and is now the ORed func- tion of analog loss of signal (ALOS) and digital loss of signal (DLOS) regardless of the loopback setting. a The frequency acquisition mode is enabled when a digital loss-of-signal (DLOS) condition occurs, in which case the receive clock (RCLK) is frequency-locked/phase-locked to the external clock (EXCLK). a Improved ITU-T G.703 interference immunity for CEPT mode operation. DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates Page 3, Figure 1, Block Diagram, updated. Page 21, 28-Pin, Plastic SOJ, changed dimensions to millimeters. Page 22, 28-Pin, Plastic DIP, changed dimensions to millimeters. fF ON = Page 22, corrected Device Code. Lucent Technologies Inc. 23 M@ 0050026 0032733 267