HT9200A/B
DTMF Generators
Selection Table
Function
Part No.
Operating
Voltage
OSC
Frequency Interface Package
HT9200A 2V~5.5V 3.58MHz Serial 8 DIP/SOP
HT9200B 2V~5.5V 3.58MHz Serial/Parallel 14 SOP
Block Diagram
1 February 13, 2001
Features
·Operating voltage: 2.0V~5.5V
·Serial mode for the HT9200A
·Serial/parallel mode for the HT9200B
·Low standby current
·Low total harmonic distortion
·3.58MHz crystal or ceramic resonator
·HT9200A: 8-pin DIP/SOP package
HT9200B: 14-pin SOP package
General Description
The HT9200A/B tone generators are designed
for mC interfaces. They can be instructed by a
mC to generate 16 dual tones and 8 single tones
from the DTMF pin. The HT9200A provides a
serial mode whereas the HT9200B contains a
selectable serial/parallel mode interface for
various applications such as security systems,
home automation, remote control through tele-
phone lines, communication systems, etc.
S/P
C ontrol
Circuit
3.58M H z
C rystal/R esonator
O s c illa to r
Serial D ata
Input C ircuit
DTM F
G enerator
P a ra lle l D a ta
Input C ircuit
X1
X2
DATA
CLK
CE D0D3
DTM F
D2 D1
Pin Assignment
Pad Assignment Pad Coordinates Unit: mm
Pad
No. XY
Pad
No. XY
1-553.30 430.40 8 553.30 -523.50
2-553.30 -133.50 9 553.30 -190.30
3-553.30 -328.50 10 553.30 4.70
4-553.30 -523.50 11 553.30 340.30
5-220.10 -523.50 12 374.90 523.50
6-25.10 -523.50 13 -279.30 523.50
7 308.10 -523.50
Chip size: 1460 ´1470 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name I/O Internal
Connection Description
CE I CMOS IN
Pull-high Chip enable, active low
X2 O
Oscillator
The system oscillator consists of an inverter, a bias resistor, and
the required load capacitor on chip.
The oscillator function can be implemented by Connect a stan-
dard 3.579545MHz crystal to the X1 and X2 terminals.
X1 I
VSS ¾¾
Negative power suppl, ground
NC ¾¾
No connection
HT9200A/B
2 February 13, 2001
CE
S/P
1
8
29
3
10
4
11
5
12
6
13
7
(0 ,0 )
X2
X1
VSS
D1 D2
D0
D3
CLK
DATA
DTM F
VDD
CE
CE
1
2
3
4
8
7
6
5
X2
X1
VSS
VDD
DTM F
DATA
CLK
H T9200A
8 DIP/SO P
S/P
14
13
12
11
10
9
8
1
2
3
4
5
6
7
H T9200B
1 4 S O P
X2
X1
VSS
NC
D0
D1
VDD
DTM F
DATA
CLK
D3
D2
Pin Name I/O Internal
Connection Description
D0~D3 I
CMOS IN
Pull-high
or Floating
Data inputs for the parallel mode
When the IC is operating in the serial mode, the data input ter-
minals (D0~D3) are included with a pull-high resistor. When
the IC is operating in the parallel mode, these pins become
floating.
S/P I CMOS IN
Operation mode selection input
S/P="H": Parallel mode
S/P="L": Serial mode
CLK I
CMOS IN
Pull-high
or Floating
Data synchronous clock input for the serial mode
When the IC is operating in the parallel mode, the input termi-
nal (CLK) is included with a pull-high resistor. When the IC is
operating in the serial mode, this pin becomes floating.
DATA I
CMOS IN
Pull-high
or Floating
Data input terminal for the serial mode
When the IC is operating in the parallel mode, the input termi-
nal (DATA) is included with a pull-high resistor. When the IC is
operating in the serial mode, this pin becomes floating.
DTMF O CMOS OUT Output terminal of the DTMF signal
VDD ¾¾
Positive power supply, 2.0V~5.5V for normal operation
Approximate internal connection circuits
HT9200A/B
3 February 13, 2001
CMOS OUT
CMOS IN
Pull-high
CMOS IN
OSCILLATOR
X1 X2
EN
10M
20pF 10pF
VDD
VDD VDD
CMOS IN (For D0~D3,
CLK, DATA)
Absolute Maximum Ratings
Supply Voltage.................................-0.3V to 6V Storage Temperature.................-50°Cto125°C
Input Voltage....................VSS-0.3 to VDD+0.3V Operating Temperature ..............-20°Cto75°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maxi-
mum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
Electrical Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾¾ 2¾5.5 V
IDD Operating Current 2.5V S/P=VDD,D0~D3=VSS,
CE=VSS, No load
¾240 2500 mA
5.0V ¾950 3000
VIL "Low" Input Voltage ¾¾ VSS ¾0.2VDD V
VIH "High" Input Voltage ¾¾
0.8VDD ¾VDD V
ISTB Standby Current 2.5V S/P=VDD,CE=VDD,
No load
¾¾ 1mA
5.0V ¾¾ 2
RPPull-high Resistance 2.5V VOL=0V 120 180 270 kW
5.0V 45 68 100
tDE DTMF Output Delay
Time (Parallel Mode) 5V ¾¾
tUP+6 tUP+8 ms
VTDC DTMF Output DC
Level
2V~
5.5V DTMF Output 0.45VDD ¾0.75VDD V
ITOL DTMF Sink Current 2.5V VDTMF=0.5V -0.1 ¾¾
mA
VTAC DTMF Output AC
Level 2.5V Row group, RL=5kW0.12 0.15 0.18 Vrms
ACR Column Pre-emphasis 2.5V Row group=0dB 1 2 3 dB
RLDTMF Output Load 2.5V tHD £-23dB 5¾¾kW
tHD Tone Signal
Distortion 2.5V RL=5kW¾-30 -23 dB
fCLK Clock Input Rate
(Serial Mode) ¾¾ ¾
100 500 kHz
tUP Oscillator Starting
Time (When CE is low) 5.0V
The time from CE
falling edge to normal
oscillator operation
¾¾
10 ms
fOSC System Frequency ¾Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz
HT9200A/B
4 February 13, 2001
Table 1: Digits vs. input data vs. tone output frequency (serial mode)
Digit D4 D3 D2 D1 D0 Tone Output Frequency (Hz)
100001 697+1209
200010 697+1336
300011 697+1477
400100 770+1209
500101 770+1336
600110 770+1477
700111 852+1209
801000 852+1336
901001 852+1477
001010 941+1336
*010 1 1 941+1209
#011 0 0 941+1477
A01101 697+1633
B01110 770+1633
C01111 852+1633
D00000 941+1633
¾1 0 0 0 0 697
¾1 0 0 0 1 770
¾1 0 0 1 0 852
¾1 0 0 1 1 941
¾1 0 1 0 0 1209
¾1 0 1 0 1 1336
¾1 0 1 1 0 1477
¾1 0 1 1 1 1633
DTMF OFF 1 1 1 1 1 ¾
Note: The codes not listed in Table 1 are not used D4 is MSB
HT9200A/B
5 February 13, 2001
Functional Description
The HT9200A/B are DTMF generators for mC
interfaces. They are controlled by a mC in the se-
rial mode or the parallel mode (for the
HT9200B only).
Serial mode (HT9200A/B)
The HT9200A/B employ a data input, a 5-bit
code, and a synchronous clock to transmit a
DTMF signal. Every digit of a phone number to
be transmitted is selected by a series of inputs
which consist of 5-bit data. Of the 5 bits, the
D0(LSB) is the first received bit. The
HT9200A/B will latch data on the falling edge of
the clock (CLK pin). The relationship between
the digital codes and the tone output frequency
is shown in Table 1. As for the control timing di-
agram, refer to Figure 1.
Table 2: Digits vs. input data vs. tone output frequency (parallel mode)
Digit D3 D2 D1 D0 Tone Output Frequency (Hz)
10001 697+1209
20010 697+1336
30011 697+1477
40100 770+1209
50101 770+1336
60110 770+1477
70111 852+1209
81000 852+1336
HT9200A/B
6 February 13, 2001
When the system is operating in the serial
mode a pull-high resistor is attached to D0~D3
(for parallel mode) on the input terminal.
For the HT9200B, the S/P pin has to be connected
low for serial mode operation.
Parallel mode ( HT9200B)
The HT9200B provides four data inputs D0~D3
to generate their corresponding DTMF signals.
The S/P has to be connected high to select the
parallel operation mode. Then the input data
codes should be determined. Finally, the CE is
connected low to transmit the DTMF signal
from the DTMF pin.
The TDE time (about 6ms) will be delayed from
the CE falling edge to the DTMF signal output.
The relationship between the digital codes and
the tone output frequency is illustrated in Table
2. As for the control timing diagram, see Figure 2.
When the system is operating in the parallel
mode, D0~D3 are all in the floating state. Thus,
these data input pins should not float.
CE
S /P
X2
DATA
C L K
LSB M S B
DTM F
LSB M S B LSB M SB
11111
Digit 1 Digit 2
D ig it 1
D TM F signal
Digit 2
D TM F signal
Stop code
(O scillator)
tUP
Figure 1
Digit D3 D2 D1 D0 Tone Output Frequency (Hz)
91001 852+1477
01010 941+1336
*101 1 941+1209
#110 0 941+1477
A1101 697+1633
B1110 770+1633
C1111 852+1633
D0000 941+1633
Tone frequency
Output Frequency (Hz) %Error
Specified Actual
697 699 +0.29%
770 766 0.52%
852 847 0.59%
941 948 +0.74%
1209 1215 +0.50%
1336 1332 0.30%
1477 1472 0.34%
% Error does not contain the crystal frequency drift
HT9200A/B
7 February 13, 2001
S /P
CE
tDE
D0~D3
DTM F tDE
X2
(O scillator)
N ote: The data (D 0~D 3) should be ready before the C E becom es low .
Figure 2
Application Circuits
Serial mode
Serial/parallel mode
HT9200A/B
8 February 13, 2001
H T9200B
14
13
12
11
10
9
8
1
2
3
4
5
6
7
CE
X2
X1
VSS
NC
D0
D1
VDD
DTM F
DATA
CLK
S/P
D3
D2
3.579545M H z
mC
VDD
CE
D0
D1
D2
D3
S/P
CLK
DATA
VDD
Tone
O utput
VDD
VSS
20pF
20pF
VSS
H T9200A
VDD
DTM F
DATA
CLK
1
2
3
4
8
7
6
5
CE
X2
X1
VSS
3.579545M H z
V
DD
Tone
O utput
mC
V
DD
VDD
VSS
CE
CLK
DATA
20pF
20pF
HT9200A/B
9 February 13, 2001
Copyright Ó2001 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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