© 2005 Fairchild Semiconductor Corporation DS005212 www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC573 3-STATE Octal D-Type Latch
MM74HC573
3-STATE Octal D-Type Latch
General Descript ion
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the hi gh noise immun ity an d low power consu mption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and t he 3-STATE featu re, th ese de vices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the ou t-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTRO L OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protect ed from damage due to static di scharge by in ternal
diode clamps to VCC and ground.
Features
■Typical propagation delay: 18 ns
■Wide operat i ng voltage ran ge : 2 to 6 volts
■Low input current: 1
P
A maximum
■Low quiescent current: 80
P
A maximum ( 74HC Series)
■Compatible with bus-oriented systems
■Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Ta pe and Reel. Specif y by append ing the suffix let t er “X” to the or dering co de.
Connection Diagram
Top View
Truth Table
H
HIGH Level
L
LOW Le vel
Q0
Level of output bef ore stea dy -s ta te input cond it ions were es tab lis hed.
Z
High Impedance
X
Don't Care
Order Number Package Number Package Description
MM74HC573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output Latch Data Output
Control Enable
LHHH
LHLL
LLXQ
0
HXXZ
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MM74HC573
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-
age to the device may occur.
Note 2: Unle ss otherwi se s pec ified al l vo lta ges are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V
r
10% the worst-case output voltages (VOH, and VOL) occur for HC a t 4.5V. Thus the 4.5V values should be use d when
designing with this su pply. Worst-case VIH and VIL occur at VCC
5.5V and 4.5V respectively. (The VIH value at 5. 5V is 3.85 V.) The wo rs t -c as e leak age cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the hi gher voltage and so the 6.0V valu es s hould be u s ed.
Supply Voltage (VCC)
0.5 to
7.0V
DC Input Voltage (VIN)
1.5 to VCC
1.5V
DC Output Voltage (VOUT)
0.5 to VCC
0.5V
Clamp Diode Current (IIK, IOK)
r
20 mA
DC Output Current, per pin (IOUT)
r
35 mA
DC VCC or GND Current, per pin (ICC)
r
70 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 sec onds) 260
q
C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage 0 VCC V
(VIN, VOUT)
Operating Temperature Range (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) V
CC
2.0V 1000 ns
VCC
4.5V 500 ns
VCC
6.0V 400 ns
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V
Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level Output VIN
VIH or VIL
Voltage |IOUT|
d
20
P
A 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
d
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level Output VIN
VIH or VIL
Voltage |IOUT|
d
20
P
A 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
d
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input Current VIN
VCC or GND 6.0V
r
0.1
r
1.0
r
1.0
P
A
IOZ Maxim um 3-STATE Output VOUT
VCC or GND
Leakage Current OC
VIH 6.0V
r
0.5
r
5.0
r
10
P
A
ICC Maximum Quiescent Supply VIN
VCC or GND
Current IOUT
0
P
A 6.0V 8.0 80 160
P
A
'
ICC Quiescent Supply Current VCC
5.5V OE 1.0 1.5 1.8 2.0 mA
per Input Pin VIN
2.4V LE 0.6 0.8 1.0 1.1 mA
or 0.4V (Note 4) DATA 0.4 0.5 0.6 0.7 mA
3 www.fairchildsemi.com
MM74HC573
AC Electrical Characteristics
VCC
5V, TA
25
q
C, tr
tf
6 ns
AC Electrical Characteristics
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Propagation Delay, Da ta to Q CL
45 pF 16 20 ns
tPHL, tPLH Maximum Propagation Delay, L E to Q CL
45 pF 14 22 ns
tPZH, tPZL Maximum Output Enable Time RL
1 k
:
15 27 ns
CL
45 pF
tPHZ, tPLZ Maximum Output Disable Time RL
1 k
:
13 23 ns
CL
5 pF
tSMinimum Set Up Time, Data to LE 10 15 ns
tHMinimu m Hold Time, LE to Data 2 5 ns
tWMinimum Pulse Width, LE or Data 10 16 ns
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation CL
50 pF 2.0V 45 110 138 165 ns
Delay Data to Q CL
150 pF 2.0V 58 150 188 225 ns
CL
50 pF 4.5V 17 22 28 33 ns
CL
150 pF 4.5V 21 30 38 40 ns
CL
50 pF 6.0V 15 19 24 29 ns
CL
150 pF 6.0V 19 26 33 39 ns
tPHL, tPLH Maximum Propagation CL
50 pF 2.0V 46 115 138 165 ns
Delay, LE to Q CL
150 pF 2.0V 60 155 194 233 ns
CL
50 pF 4.5V 14 23 29 35 ns
CL
150 pF 4.5V 21 31 47 47 ns
CL
50 pF 6.0V 12 20 25 30 ns
CL
150 pF 6.0V 19 27 34 41 ns
tPZH, tPZL Maximum Output Enable RL
1 k
:
Time CL
50 pF 2.0V 55 140 175 210 ns
CL
150 pF 2.0V 67 180 225 270 ns
CL
50 pF 4.5V 15 28 35 42 ns
CL
150 pF 4.5V 24 36 45 54 ns
CL
50 pF 6.0V 14 24 30 36 ns
CL
150 pF 6.0V 22 31 39 47 ns
tPHZ, tPLZ Maximum Output Disable RL
1 k
:
2.0V 40 125 156 188 ns
Time CL
50 pF 4.5V 13 25 31 38 ns
6.0V 12 21 27 32 ns
tSMinimum Set Up Time 2.0V 30 75 95 110 ns
Data to LE 4.5V 10 15 19 22 ns
6.0V 9 13 16 19 ns
tHMinimum Hold Time 2.0V 25 31 38 ns
LE to Data 4.5V 5 6 7 ns
6.0V 4 5 6 ns
tWMinimum Pulse Width LE, 2.0V 30 80 100 120 ns
or Data 4.5V 9 16 20 24 ns
6.0V 8 14 18 20 ns
tTLH, tTHL Maximum Output Rise CL
50 pF 2.0V 25 60 75 90 ns
and Fall Time, Clock 4.5V 7 12 15 18 ns
6.0V 6 10 13 15 ns
CPD Power Dissipation Capacitance OC
VCC 5pF
(Note 5) (per latch) OC
GND 52 pF
CIN Maximum Input 5 10 10 10 pF
Capacitance
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MM74HC573
AC Electrical Characteristi cs (Continued)
Note 5: CPD determines the no load dynam ic pow er cons um ption, PD
CPD VCC2 f
ICC VCC, and th e no load dy namic current co ns um ption ,
IS
CPD VCC f
ICC.
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guara nt eed Lim its
COUT Maximum Output 15 20 20 20 pF
Capacitance
5 www.fairchildsemi.com
MM74HC573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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MM74HC573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide
Package Number M20D
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MM74HC573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
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MM74HC573 3-STATE Octal D-Type Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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